CN113078196B

CN113078196B - Display panel

Info

Publication number: CN113078196B
Application number: CN202110325905.6A
Authority: CN
Inventors: 李曼曼; 张露; 胡思明
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2022-10-11
Anticipated expiration: 2041-03-26
Also published as: CN113078196A

Abstract

The embodiment of the invention discloses a display panel, which comprises a substrate; an electrode layer on one side of the substrate, the electrode layer including a plurality of electrodes; the light emitting layer is positioned on one side of the electrode layer, which is far away from the substrate, and a plurality of light emitting areas are formed in the area where the light emitting layer is positioned; a plurality of metal layers between the substrate and the electrode layer; the multi-layer metal layer comprises a first metal layer, wherein the first metal layer comprises a plurality of first metal lines, a plurality of second metal lines and a plurality of third metal lines; at least part of the first metal lines, the second metal lines and the third metal lines are positioned in the luminous areas, in at least part of the luminous areas, the first metal lines are superposed with the central lines of the luminous areas, and the second metal lines and the third metal lines are symmetrically distributed around the first metal lines. The technical scheme of the embodiment of the invention is beneficial to balancing the display difference of the display panel under different observation visual angles so as to improve the color cast problem of the display panel and further improve the display effect.

Description

Display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel.

Background

With the development of display technology, the display quality requirements of users for display devices are increasing. The display device comprises a display panel, wherein in a film layer structure of the display panel, different display areas have flatness difference, and the flatness difference can cause color cast problem and influence the display effect of the display device.

Disclosure of Invention

Embodiments of the present invention provide a display panel to improve a color shift problem of the display panel, so as to improve a display effect.

An embodiment of the present invention provides a display panel, including:

a substrate;

an electrode layer on one side of the substrate, the electrode layer including a plurality of electrodes;

the light-emitting layer is positioned on one side, far away from the substrate, of the electrode layer, and a plurality of light-emitting areas are formed in the area where the light-emitting layer is positioned;

a plurality of metal layers between the substrate and the electrode layer; the multi-layer metal layer comprises a first metal layer, and the first metal layer comprises a plurality of first metal lines, a plurality of second metal lines and a plurality of third metal lines; at least part of the first metal line, the second metal line and the third metal line are positioned in the luminous zone, in at least part of the luminous zones, the first metal line is superposed with the central line of the luminous zone, and the second metal line and the third metal line are symmetrically distributed around the first metal line.

Further, in the thickness direction of the display panel, the first metal layer is a metal layer closest to the electrode layer in the multiple metal layers.

Further, the center lines of the light emitting region include a first center line, and the first center line, the first metal line, the second metal line, and the third metal line all extend in a first direction; each first metal line and each second metal line extend from the bottom of the display panel to the top of the display panel, and each first metal line and each second metal line are located in the plurality of light emitting areas; each third metal line is positioned in at least one light emitting area.

Furthermore, the first metal layer further includes a plurality of connection lines, two adjacent third metal lines in the first direction are electrically connected through the connection lines, and the third metal lines and the second metal lines in the same light emitting area are connected with the same signal.

Further, two adjacent third metal lines in the first direction are insulated;

preferably, the first metal layer further comprises a source/drain of a transistor in the pixel circuit, the electrode being connected to the source/drain through a via; at least part of the through holes are positioned in the light emitting area, and the source/drain electrodes are used as the third metal lines.

Further, the length of the third metal line along the first direction is greater than the length of the second metal line along the first direction in the light emitting area.

Further, in at least some of the light emitting regions, the first metal line, the second metal line, and the third metal line are all symmetrical about a second center line of the light emitting region, the second center line being perpendicular to the first center line.

Further, the first metal layer further comprises a plurality of fourth metal lines, each of at least some of the light emitting regions comprises at least some of the fourth metal lines, and the number of the fourth metal lines in each of the light emitting regions is at least two, and at least two of the fourth metal lines are symmetrically distributed with respect to the first metal line in the light emitting region;

preferably, the third metal line and the fourth metal line are arranged in the light emitting area in an insulated manner;

preferably, the fourth metal line is used to connect a storage capacitor and a transistor in the pixel circuit.

Further, the light emitting layers at least comprise a first color light emitting layer, a second color light emitting layer and a third color light emitting layer, and the light emitting areas comprise a first color light emitting area, a second color light emitting area and a third color light emitting area; in the light emitting areas with the same light emitting color, the distribution positions of the metal wires in the first metal layer are the same.

Further, one of the first metal line and the second metal line is a data line, and the other is a power line; the line width of the second metal line and the line width of the third metal line are both in negative correlation with the pixel density of the display panel.

The display panel provided by the embodiment of the invention comprises a substrate, an electrode layer, a light emitting layer and a plurality of metal layers, wherein a first metal layer in the plurality of metal layers comprises a plurality of first metal lines, a plurality of second metal lines and a plurality of third metal lines. Compared with the prior art, the scheme is favorable for balancing the display difference of the display panel under different observation visual angles so as to improve the color cast problem of the display panel and improve the display effect.

Drawings

FIG. 1 is a schematic diagram of a display panel in the prior art;

fig. 2 is a top view of a display panel according to an embodiment of the present invention;

fig. 3 is a cross-sectional view of a display panel according to an embodiment of the present invention;

FIG. 4 is a top view of another display panel provided in accordance with an embodiment of the present invention;

FIG. 5 is a top view of another display panel provided in accordance with an embodiment of the present invention;

fig. 6 is a cross-sectional view of another display panel provided in an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 8 is a top view of another display panel according to an embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background, different display areas of the conventional display device have flatness differences, and the flatness differences may cause color shift problems, which affect the display effect of the display device. The inventor researches and finds that the reason for the problems is that: the light-emitting device in the display panel comprises a first electrode layer, a light-emitting layer and a second electrode layer which are sequentially stacked from one side of a substrate of the display panel, a metal layer and a planarization layer are further arranged between the first electrode layer and the substrate, the first electrode layer comprises a first electrode, the first electrode is an anode of the light-emitting device, and the flatness of the planarization layer can be influenced by the fluctuation condition of the metal layer under the anode, so that the anode is inclined, the color change of a display area under different observation visual angles is large, and the problem of color cast of the light-emitting device is caused. For example, fig. 1 is a schematic structural diagram of a display panel in the prior art, and specifically is a schematic cross-sectional structural diagram of a display panel, as shown in fig. 1, a metal layer of the display panel includes a metal line 1, the metal line 1 is located in a light emitting region D0, a portion of a planarization layer 2 above the metal line 1 has a protrusion due to the metal line 1, a thickness h2 of a position in the planarization layer 2 where the metal line 1 is disposed below is greater than a thickness h1 of a position in the planarization layer 2 where the metal line 1 is not disposed below, which may cause an inclination of an anode 3 of a light emitting device, so that the planarization difference occurs between the planarization layer 2 and the anode 3, for example, when h2-h1 is about 0.15 to 0.2um, an inclination angle a of the anode 3 may reach 2 ° to 3 °, the inclination of the anode 3 may cause color shift, and the color shift conditions of the left-view and right-view light emitting regions of the D0 are different, which affects the display effect. In order to solve the above problems, the prior art generally improves the color shift problem by providing two planarization layers, i.e. a planarization layer is further disposed between the planarization layer 2 and the anode 3 to improve the flatness under the anode 3, or by increasing the thickness of the planarization layer 2 to improve the flatness under the anode 3, but both of the above two methods affect the production yield of the display panel.

In view of the foregoing problems, embodiments of the present invention provide a display panel. Fig. 2 is a top view of a display panel according to an embodiment of the present invention, where fig. 2 only shows a partial structure of a first metal layer under a light emitting area in the display panel; fig. 3 is a cross-sectional view of a display panel according to an embodiment of the present invention, which may be a cross-sectional view of the display panel shown in fig. 2 taken along a cross-sectional line AA'. Referring to fig. 2 and 3, the display panel includes a substrate 10, an electrode layer 20, a light emitting layer 30, and a plurality of metal layers; the electrode layer 20 is positioned at one side of the substrate 10, and the electrode layer 20 includes a plurality of electrodes 21; the light-emitting layer 30 is positioned on one side of the electrode layer 20 away from the substrate 10, and a plurality of light-emitting regions are formed in the region where the light-emitting layer 30 is positioned; a plurality of metal layers are positioned between the substrate 10 and the electrode layer 20; the multi-layer metal layer includes a first metal layer 40, the first metal layer 40 including a plurality of first metal lines 41, a plurality of second metal lines 42, and a plurality of third metal lines 43; at least part of the first metal line 41, the second metal line 42 and the third metal line 43 are located in the light emitting region, the first metal line 41 coincides with a center line of the light emitting region in at least part of the light emitting region, and the second metal line 42 and the third metal line 43 are symmetrically distributed with respect to the first metal line 41.

The substrate 10 may provide buffering, protection, or support for the display panel. The substrate 10 may be a flexible substrate, and the material of the flexible substrate may be Polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or the like, or may be a mixture of these materials. The substrate 10 may be a hard substrate formed of glass or the like.

And pixel circuits are formed in the multiple metal layers and can provide driving signals for the light-emitting devices in the display panel so as to drive the light-emitting devices in the display panel to emit light. The electrode layer 20, the Light-Emitting layer 30 and another electrode layer (not shown in the figure) form a plurality of Light-Emitting devices, which may be Organic Light-Emitting diodes (OLEDs), each of which includes an anode, a Light-Emitting layer and a cathode, and each of the Light-Emitting devices may be electrically connected to the pixel circuit through the anode, so that the pixel circuit provides a driving signal to the Light-Emitting device to drive the Light-Emitting device to emit Light. Here, the light emitting region 30 is formed in a plurality of light emitting regions, which are formed by vertical projection of the light emitting layer 30 in the thickness direction Z of the display panel, and fig. 2 and 3 only schematically show one light emitting region D. Between the electrode layer 20 and the first metal layer 40, a planarization layer 50 covering the first metal layer 40 is further included. The electrode 21 in the electrode layer 20 may be an anode of a light emitting device, and in this embodiment and the following embodiments, the electrode 21 is exemplified as the anode of the light emitting device.

Fig. 2 and 3 only schematically show one first metal line 41, one second metal line 42, and one third metal line 43 in the first metal layer 40, and each of the first metal line 41, the second metal line 42, and the third metal line 43 may be a trace for transmitting a signal to the pixel circuit in the display panel, or a signal trace within the pixel circuit, or a dummy metal line, where the trace for transmitting a signal to the pixel circuit may include a data line for transmitting a data voltage signal, a power line for transmitting a power supply signal (which may be the first power supply signal VDD), and the like, and the signal trace within the pixel circuit may include a trace for connecting the transistor and the anode of the light emitting device, and a trace for connecting the storage capacitor and the transistor, and the dummy metal line is a metal line additionally disposed in the first metal layer 40.

At least a portion of the first metal line 41, the second metal line 42, and the third metal line 43 are located in each light emitting region, for example, the light emitting region D includes at least a portion of the first metal line 41, at least a portion of the second metal line 42, and at least a portion of the third metal line 43. Exemplarily, the center line of the light emitting region D includes a first center line L1, the center of the first metal line 41 coincides with the first center line L1 of the light emitting region D in at least a part of the light emitting region in the display panel, for example, in the light emitting region D shown in fig. 2 and 3, and the second metal line 42 and the third metal line 43 are symmetrically distributed with respect to the first metal line 41. The second metal line 42 and the third metal line 43 are symmetrically distributed with respect to the first metal line 41, which means that the distribution positions of the second metal line 42 and the third metal line 43 are symmetrical with respect to the first metal line 41, and the shapes at the respective positions on the second metal line 42 and the third metal line 43 are also symmetrical with respect to the first metal line 41. Illustratively, a distance X1 between the third metal line 43 and the first metal line 41 is equal to a distance X2 between the second metal line 42 and the first metal line 41, a width of the third metal line 43 at each position in the first direction Y is equal to a width of the second metal line 42 at the same position in the first direction Y, and an area S1 of the third metal line 43 in the light emitting region D is equal to an area S2 of the second metal line 42 in the light emitting region D.

Although the presence of the first metal line 41, the second metal line 42 and the third metal line 43 may affect the flatness of the planarization layer 50 under the electrode 21 in the light emitting region D and further affect the flatness of the electrode 21, the presence of the third metal line 41, the second metal line 42 and the third metal line 43 on the left side of the first center line L1 of the light emitting region D and the presence of the second metal line 42 and the other half of the first metal line 41 on the right side of the first center line L1 of the light emitting region D may substantially match the fluctuation of the planarization layer 50 on the left side and the right side of the light emitting region D, which may substantially match the fluctuation of the electrode 21 on the left side and the right side of the light emitting region D, and further may substantially match the left and the right side of the light emitting region D, which may help to balance the display of different display regions under different viewing angles, thereby improving the display effect of the display panel.

Illustratively, in conjunction with fig. 2 and 3, before forming the first metal layer 40 of the multi-layer metal layers, the pixel density (Pixels Per inc, PPI) of the display panel, i.e., the number of Pixels Per Inch in the display area, is determined. If the pixel density PPI of the display panel is less than the predetermined pixel density, for example, the pixel density PPI of the display panel is less than 422, which indicates that the wiring space of the first metal layer 40 in each light-emitting region is sufficient, the display panel can be manufactured by using the scheme of the embodiment of the present invention. When the first metal layer 40 is formed, firstly, the positions of the first metal line 41 and the second metal line 42 are determined according to the position of the light emitting area D to be formed and the center line thereof, so that the center of the first metal line 41 is aligned with the position of the center line of the light emitting area D, the second metal line 42 is positioned on one side of the first metal line 41 in the light emitting area D, then, according to the position and the shape of the second metal line 42, the center line of the light emitting area D is taken as a symmetry axis, at least part of the second metal line 42 is mirrored to the other side of the first metal line 41 in the light emitting area D to form a third metal line 43, so that the second metal line 42 and the third metal line 43 in the light emitting area D are symmetrical, the fluctuation conditions of the second metal line 42 and the third metal line 43 in the light emitting area D are approximate, and further, the fluctuation conditions of the left side and the right side of the light emitting area D are equalized and the planarization layer is used for improving the color cast of the display panel and improving the display effect.

With reference to fig. 2 and 3, optionally, in the thickness direction Z of the display panel, the first metal layer 40 is a metal layer closest to the electrode 21 in the plurality of metal layers. Because the distribution of the metal layer closest to the electrode 21 most easily affects the flatness of the electrode 21 and the planarization layer 50 below the electrode 21, the first metal layer 40 is set to be the metal layer closest to the electrode layer 20 in the plurality of metal layers and is set in at least part of the light-emitting areas, the first metal line 41 is overlapped with the central line of the light-emitting area, and the second metal line 42 and the third metal line 43 are symmetrically distributed with respect to the first metal line 41, so that the fluctuation conditions of the planarization layer 50 at the left side and the right side in the light-emitting area can be ensured to be close, the fluctuation conditions of the electrode 21 at the left side and the right side in the light-emitting area can be ensured to be close, the effect of reducing the difference of flatness of the electrode 21 in the light-emitting area by the scheme is better, and the effect of improving the color cast problem is better.

Fig. 4 is a top view of another display panel according to an embodiment of the present invention, where fig. 4 shows a plurality of light emitting areas in the display panel and a distribution of the first metal layer under each light emitting area. Referring to fig. 2 to 4, optionally, the center line of the light emitting region D includes a first center line L1, and the first center line L1, the first metal line 41, the second metal line 42, and the third metal line 43 all extend in the first direction Y; each of the first metal lines 41 and each of the second metal lines 42 extend from the bottom of the display panel to the top of the display panel, and each of the first metal lines 41 and each of the second metal lines 42 are located in a plurality of light emitting regions D; each third metal line 43 is located in at least one light emitting region D.

Specifically, the first metal line 41, the second metal line 42, the third metal line 43, and the first center line L1 of the light emitting region D extend in the same direction. The bottom and the top of the display panel refer to two opposite sides of the display panel, and exemplarily, signal terminals connected to the driving chip, such as a power signal terminal and a data voltage signal terminal, are disposed on the display panel. Each third metal line 43 is located in at least one light emitting region D, for example, as shown in fig. 2, one third metal line 43 may be located in only one light emitting region D, that is, each third metal line 43 may be disposed in one-to-one correspondence with each light emitting region in the display panel, as shown in fig. 4, one third metal line 43 may be located in only one light emitting region D, or may be located in two light emitting regions D simultaneously, for example, the light emitting region D includes a first color light emitting region D1, a second color light emitting region D2, and a third color light emitting region D3, at least a part of the third metal lines 43 are located in only one second color light emitting region D2, and at least a part of the third metal lines 43 are located in one first color light emitting region D1 and one third color light emitting region D3 simultaneously.

According to the scheme, the first metal lines 41, the second metal lines 42, the third metal lines 43 and the first central lines L1 of the light emitting regions D are arranged to extend along the first direction Y, the first metal lines 41 and the second metal lines 42 extend from the bottom of the display panel to the top of the display panel, each first metal line 41 and each second metal line 42 are located in a plurality of light emitting regions D, so that each first metal line 41 and the corresponding second metal line 42 located in the same light emitting region are arranged corresponding to one column of light emitting regions in the display panel, the plurality of first metal lines 41 and the plurality of second metal lines 42 can be arranged corresponding to a plurality of columns of light emitting regions in the display panel, on the basis, each third metal line 43 is arranged in at least one light emitting region D, and the fluctuation conditions of the anode of the flattening layer and the anode of the light emitting device on the left and right sides in the plurality of columns of light emitting regions are balanced by maximally utilizing the arrangement of the first metal lines 41, the second metal lines 42 and the third metal lines 43, so that the color cast problem of the display panel is improved and the display effect is improved.

Referring to fig. 4, on the basis of the above scheme, optionally, the first metal layer further includes a plurality of connection lines 431, two adjacent third metal lines 43 in the first direction Y are electrically connected through the connection lines 431, and the third metal lines 43 and the second metal lines 42 in the same light emitting area D are connected to the same signal.

Since each third metal line 43 is located in at least one light emitting region D and the display panel has a plurality of columns of light emitting regions D, the third metal lines 43 are spaced in the first direction Y corresponding to each column of light emitting regions D in the display panel. In the scheme, two adjacent third metal lines 43 in the first direction Y are electrically connected through the connection line 431, so that one column of the third metal lines 43 corresponding to each column of the light emitting areas D are electrically connected with each other, and a whole metal line extending from the bottom of the display panel to the top of the display panel is formed, which is favorable for enabling the whole third metal line 43 to form a structure which is in mirror symmetry with the second metal line 42 about the first metal line 41, and is favorable for balancing the fluctuation conditions of the flattening layer and the anodes of the light emitting devices on the left side and the right side in each column of the light emitting areas.

The third metal line 43 and the second metal line 42 in the same light emitting area D are connected to the same signal, for example, a data voltage signal terminal or a power signal terminal may be connected to a whole third metal line 43 and a whole second metal line 42 in the same light emitting area D, and when the second metal line 42 is used to transmit a data voltage signal or a power signal to a pixel circuit in the display panel, compared with a scheme in which only the second metal line 42 is connected to the signal terminal at the bottom of the display panel, the scheme increases the cross-sectional area of the metal line formed by the third metal line 43 and the second metal line 42, which is equivalent to increasing the resistance of the metal line, thereby reducing the voltage Drop (IR Drop) generated on the metal line, and reducing the voltage loss generated on the second metal line 42. When the second metal line 42 is used for transmitting the data voltage signal to the pixel circuit in the display panel, the present scheme helps to reduce the voltage loss of the data voltage signal to ensure the display effect. When the second metal line 42 is used to transmit a power signal (the power signal may be the first power signal VDD) to the pixel circuit in the display panel, the second metal line 42 is a power line, and since the display panel is further provided with a plurality of power lines extending along the second direction X, the power line is electrically connected to the second metal line 42 and forms a mesh structure with the second metal line 42, on this basis, if each whole third metal line 43 is electrically connected to a plurality of rows of power lines extending along the second direction X, the voltage loss of the power signal can be further reduced, so as to reduce the power voltage difference between the display area near the bottom of the display panel and the display area near the top of the display panel, thereby improving the display uniformity of the display panel.

Fig. 5 is a top view of another display panel according to an embodiment of the invention, where fig. 5 only shows a partial structure of the first metal layer under one light emitting area in the display panel; fig. 6 is a cross-sectional view of another display panel provided in an embodiment of the present invention, which may be a cross-sectional view of the display panel shown in fig. 5 cut along a cross-sectional line BB'. In conjunction with fig. 5 and 6, or with reference to fig. 2 and 3, alternatively, two adjacent third metal lines 43 in the first direction Y may also be provided for insulation. When each third metal line 43 is arranged in one-to-one correspondence with at least a part of the light emitting areas in the display panel, it is ensured that the first metal line 41 in at least a part of the light emitting areas is located at the center line of the light emitting area, and the second metal line 42 and the third metal line 43 are symmetrically distributed with respect to the first metal line 41, and it is not necessary to electrically connect two adjacent third metal lines 43 in the first direction Y, so that the fluctuation of the planarization layer on the left and right sides in the light emitting area can be equalized, and the wiring space of the first metal layer 40 can be saved.

With reference to fig. 5 and fig. 6, on the basis of the above scheme, optionally, the first metal layer 40 is further arranged to further include a source/drain 60 of a transistor T in the pixel circuit, and the electrode 21 is connected to the source/drain 60 through a via H; at least a portion of the via H is in the light emitting region, and the source/drain electrodes 60 serve as the third metal lines 43.

Specifically, the pixel circuit includes a transistor T connected to the electrode 21 of the light emitting device, and the source/drain 60 of the transistor T refers to the source or drain of the transistor T. Exemplarily, fig. 7 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, where fig. 7 illustrates a case where the pixel circuit 100 is composed of seven thin film transistors and one storage capacitor Cst. As shown in fig. 7, the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst. A first electrode of the first transistor T1 is connected to the data voltage signal Vdata, a first electrode of the third transistor T3 and a first electrode of the fourth transistor T4 are both connected to the initialization signal Vref, a first electrode of the fifth transistor T5 is connected to the first power signal VDD, and a second electrode (for example, the second electrode may be a cathode) of the light emitting device D4 is connected to the second power signal VSS. The transistor T shown in fig. 6 may be the fourth transistor T4 or the sixth transistor T6 in fig. 7, i.e., the first electrode (i.e., the electrode 21) of the light emitting device D4 is connected to the second pole (i.e., the source/drain 60) of the fourth transistor T4 through the via H, or is connected to the second pole (i.e., the source/drain 60) of the sixth transistor T6. When at least a portion of the vias connecting the electrode 21 of the light emitting device and the source/drain 60 of the transistor T in the display panel is located in the light emitting region, for example, when the via H in fig. 6 is located in the light emitting region D, the source/drain 60, the first metal line 41 and the second metal line 42 may be disposed in the same layer, the source/drain 60 is used as the third metal line 43, and the source/drain 60 is disposed according to the position and shape of the second metal line 42 in the light emitting region D, so that the source/drain 60 and the second metal line 42 in the light emitting region D are symmetrically distributed with respect to the first metal line 41, which can effectively use the existing metal electrode source/drain 60 in the display panel as the third metal line 43, and it is not necessary to additionally provide a metal structure as the third metal line 43 in the first metal layer 40, so as to avoid occupying too much space in the first metal layer 40, and at the same time, it is also possible to balance the fluctuation of the planarization layer and the anode of the light emitting device on both sides in the light emitting region D.

With reference to fig. 5 and 6, optionally, the length a1 of the third metal line 43 along the first direction Y is set to be greater than the length a2 of the second metal line 42 along the first direction Y in the light emitting region D. Specifically, when the electrode layer 20 and the light emitting layer 30 are formed, it is necessary to perform alignment according to the distribution of the first metal layer 40 so that the first center line L1 of the light emitting region 30 and the first metal line 41 overlap in a direction perpendicular to the substrate 10. If the electrode layer 20, the light-emitting layer 30 and the first metal layer 40 are misaligned, for example, when the light-emitting region D is misaligned upward (or downward) along the first direction Y due to the misalignment, the upper end (or the lower end) of the third metal line 43 along the first direction Y may be completely located in the light-emitting region D, so that the second metal line 42 and the third metal line 43 in the light-emitting region D are asymmetric, in this embodiment, by setting the length a1 of the third metal line 43 along the first direction Y to be greater than the length a2 of the second metal line 42 along the first direction Y in the light-emitting region D, the total length of the third metal line 43 may be greater than the length of the region where the light-emitting region D corresponds to the third metal line 43, even if the misalignment may cause the position of the light-emitting region D to move upward or downward, because the total length of the third metal line 43 is greater than the length of the region where the light-emitting region D corresponds to the third metal line 43, this embodiment helps to avoid the asymmetry of the second metal line 42 and the third metal line 43 caused by the misalignment, so as to balance the fluctuation of the light-emitting region D.

Fig. 8 is a top view of another display panel according to an embodiment of the invention, where fig. 8 only shows a partial structure of the first metal layer under one light emitting area in the display panel. As shown in fig. 8, optionally, in at least a part of the light emitting regions D, the first metal line 41, the second metal line 42 and the third metal line 43 are all symmetrical about a second center line L2 of the light emitting regions D, and the second center line L2 is perpendicular to the first center line L1.

Specifically, the second center line L2 of the light emitting region D is a center line extending in the second direction X, which is perpendicular to the first direction Y. The first metal line 41, the second metal line 42 and the third metal line 43 are all symmetrical with respect to the second center line L2 of the light emitting region D, which means that in the upper and lower two partial regions where the light emitting region D is equally divided by the second center line L2, the first metal line 41 is distributed with mirror symmetry with respect to the second center line L2, the second metal line 42 is distributed with mirror symmetry with respect to the second center line L2, and the third metal line 43 is distributed with mirror symmetry with respect to the second center line L2. The advantage of this arrangement is that the half of the first metal line 41, the half of the second metal line 42, and the half of the third metal line 43 above the second center line L2 of the light emitting region D can be substantially consistent with the other half of the first metal line 41, the other half of the second metal line 42, and the other half of the third metal line 43 below the second center line L2 of the light emitting region D, so that the fluctuation of the planarization layer 50 at the upper and lower sides of the light emitting region D is substantially consistent, the fluctuation of the electrode 21 at the upper and lower sides of the light emitting region D is substantially consistent, and the upper and lower conditions of the light emitting region D are approximately the same, which helps further balance the display difference of the display panel at different viewing angles, so as to improve the color cast of the display panel, and further improve the display effect.

Referring to fig. 2, 4 or 5, optionally, the first metal layer 40 further includes a plurality of fourth metal lines 44, each light emitting region D of at least some of the light emitting regions D includes at least some of the fourth metal lines 44, and the number of the fourth metal lines 44 in each light emitting region D is at least two, and the at least two fourth metal lines 44 are symmetrically distributed about the first metal line 41 in the light emitting region D.

Illustratively, each light emitting region D of at least some of the light emitting regions D includes at least some regions of the fourth metal line 44, the number of the fourth metal lines 44 in each light emitting region D should be even, and the number of the fourth metal lines 44 in each light emitting region D is at least two, for example, when the light emitting region D in fig. 4 includes the first color light emitting region D1, the second color light emitting region D2, and the third color light emitting region D3, the number of the fourth metal lines 44 in the second color light emitting region D2 and the third color light emitting region D3 in fig. 4 and the light emitting regions D in fig. 2 and fig. 5 is two, and the number of the fourth metal lines 44 in the first color light emitting region D1 in fig. 4 is four (i.e., two fourth metal lines 44a and two fourth metal lines 44 b). Referring to fig. 2 and 5, two fourth metal lines 44 in the light emitting region D are symmetrically distributed with respect to the first metal line 41 in the light emitting region D. Referring to fig. 4, two fourth metal lines 44a in the light emitting region D1 of the first color are symmetrically distributed with respect to the first metal line 41 in the light emitting region D, and two fourth metal lines 44b are symmetrically distributed with respect to the first metal line 41 in the light emitting region D. When the light emitting region D includes the fourth metal lines 44, the number of the fourth metal lines 44 in each light emitting region D is at least two, and the at least two fourth metal lines 44 are symmetrically distributed in the light emitting region D with respect to the first metal line 41, so that the fluctuation conditions of the first metal layer 40 on the left and right sides of the light emitting region D can be balanced, the fluctuation conditions of the planarization layer and the anode of the light emitting device on the left and right sides of the light emitting region D are substantially consistent, the left-view condition and the right-view condition of the light emitting region D are approximately the same, the display difference of the display panel under different viewing angles can be balanced, the color cast of the display panel can be improved, and the display effect can be improved.

Referring to fig. 2, 4 or 5, on the basis of the above scheme, optionally, the third metal line 43 and the fourth metal line 44 are arranged in an insulated manner in the light emitting region D. For example, as shown in fig. 5, the middle of the fourth metal line 44 may be disposed at a distance X3 from the upper end of the third metal line 43, and the lower end of the fourth metal line 44 may be disposed at a distance X4 from the middle of the third metal line 43, so that the third metal line 43 and the fourth metal line 44 are insulated in the light emitting region D. When the third metal line 43 is a source/drain of a transistor in the pixel circuit and the fourth metal line 44 is a signal line in the pixel circuit, the third metal line 43 and the fourth metal line 44 are insulated in the light emitting region D, so that short circuit between the third metal line 43 and the fourth metal line 44 can be avoided, and normal operation of the pixel circuit is not affected.

Referring to fig. 2, 4 or 5, optionally, a fourth metal line 44 is used to connect the storage capacitor and the transistor in the pixel circuit. Exemplarily, when the source/drain of the transistor in the pixel circuit and the fourth metal line 44 are disposed at the same layer, one end of the fourth metal line 44 may be electrically connected to the source/drain of the transistor, and the other end may be electrically connected to the storage capacitor in the pixel circuit through a via, referring to fig. 7, where the fourth metal line 44 may be a metal line connecting the lower plate C1 of the storage capacitor Cst and the second transistor T2, or may also be a metal line connecting the lower plate C1 of the storage capacitor Cst and the third transistor T3. The lower plate C1 of the storage capacitor Cst is generally disposed on the same layer as the gate electrode G of the driving transistor DT, and the fourth metal line 44 may be a metal line connecting the gate electrode G of the driving transistor DT and the second transistor T2, or a metal line connecting the gate electrode G of the driving transistor DT and the third transistor T3. For example, the fourth metal line 44a in fig. 4 may be one of a metal line connecting the lower plate C1 of the storage capacitor Cst and the second transistor T2 and a metal line connecting the lower plate C1 of the storage capacitor Cst and the third transistor T3, and the fourth metal line 44b is another metal line. Alternatively, the fourth metal line 44a in fig. 4 may be a metal line connecting the gate G of the driving transistor DT and the second transistor T2, and a metal line connecting the gate G of the driving transistor DT and the third transistor T3, and the fourth metal line 44b may be another metal line. The advantage of setting up like this is that can utilize existing metal line in the display panel as the fourth metal line, need not additionally to set up the metal structure as the fourth metal line in first metal level, avoids taking up the space of first metal level, simultaneously, can also equalize the undulation condition of planarization layer and emitting device's positive pole left and right sides in the luminous zone.

Referring to fig. 4, on the basis of the above solutions, optionally, the light emitting layer 30 is provided to include at least a first color light emitting layer, a second color light emitting layer and a third color light emitting layer, and the light emitting region D includes a first color light emitting region D1, a second color light emitting region D2 and a third color light emitting region D3; in the light emitting regions with the same light emitting color, the metal lines in the first metal layer 40 are distributed at the same position. The first color light emitting layer, the second color light emitting layer and the third color light emitting layer have different light emitting colors, and correspondingly, the first color light emitting area D1, the second color light emitting area D2 and the third color light emitting area D3 have different light emitting colors. In the scheme, the luminous regions with the same luminous color are arranged, the metal wires in the first metal layer 40 are distributed at the same position, so that the fluctuation conditions of the first metal layer 40 under the luminous regions with the same luminous color are the same, the display difference of the luminous regions with the same luminous color is balanced, the color cast problem of the display panel is further improved, and the display effect is further improved.

Referring to fig. 2 to 6 and fig. 8, on the basis of the above solutions, optionally, one of the first metal line 41 and the second metal line 42 is set as a data line, and the other is set as a power line, and both the line width of the second metal line 42 and the line width of the third metal line 43 are in negative correlation with the pixel density of the display panel.

Specifically, the data line refers to a signal line for transmitting a data voltage signal Vdata to the pixel circuit, and the power line refers to a signal line for transmitting a first power signal VDD to the pixel circuit. Since each of the first metal lines 41 and each of the second metal lines 42 extend from the bottom of the display panel to the top of the display panel, and the data lines and the power lines existing in the display panel extend from the bottom of the display panel to the top of the display panel, and the data lines and the power lines are usually disposed in the same layer in a metal layer closer to the electrode layer 20, one of the data lines and the power lines can be used as the first metal lines 41 and the other as the second metal lines 42, so that the existing metal lines in the display panel can be effectively used as the first metal lines 41 and the second metal lines 42, and a metal structure as the first metal lines 41 and the second metal lines 42 does not need to be additionally disposed in the first metal layer 40, thereby avoiding occupying too much space in the first metal layer 40.

Illustratively, when the first metal line 41 is a data line and the second metal line 42 is a power line, the line width of the first metal line 41 is relatively small, so the line width of the first metal line 41 is less influenced by the pixel density PPI of the display panel, and the line width of the second metal line 42 is relatively large, so the line width of the second metal line 42 is more influenced by the pixel density PPI of the display panel. If the pixel density PPI of the display panel is relatively large, for example, the pixel density 422 < PPI < 450 of the display panel indicates that the wiring space of the first metal layer 40 in each light emitting region is limited, and therefore, the larger the pixel density PPI of the display panel is, the smaller the line width of the second metal line 42 and the line width of the third metal line 43 need to be set, so as to prevent the second metal line 42 and the third metal line 43 from being shorted with other metal lines in the first metal layer 40 and affecting the normal operation of the pixel circuit.

The embodiment of the invention also provides a display device, which can be a mobile phone, a computer, a tablet personal computer, an intelligent wearable device or other electronic equipment with a display function. The display device provided by the embodiment of the present invention includes the display panel provided by any of the above embodiments of the present invention, and thus has a corresponding structure and beneficial effects of the display panel, which are not described herein again.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, comprising:

a substrate;

the light emitting layer is positioned on one side of the electrode layer, which is far away from the substrate, and a plurality of light emitting areas are formed in the area where the light emitting layer is positioned;

a plurality of metal layers between the substrate and the electrode layer; the multi-layer metal layer comprises a first metal layer, and the first metal layer comprises a plurality of first metal lines, a plurality of second metal lines and a plurality of third metal lines; at least part of the first metal line, the second metal line and the third metal line are positioned in the light emitting areas, the first metal line is coincided with the central line of the light emitting areas in at least part of the light emitting areas, and the second metal line and the third metal line are symmetrically distributed relative to the first metal line;

and the third metal wire and the second metal wire in the same light emitting area are connected with the same signal.

2. The display panel according to claim 1, wherein the first metal layer is a metal layer closest to the electrode layer among the plurality of metal layers in a thickness direction of the display panel.

3. The display panel according to claim 1, wherein the center line of the light emitting region comprises a first center line, and the first center line, the first metal line, the second metal line, and the third metal line each extend in a first direction; each first metal line and each second metal line extend from the bottom of the display panel to the top of the display panel, and each first metal line and each second metal line are located in the plurality of light emitting areas; each third metal line is positioned in at least one light emitting area.

4. The display panel according to claim 3, wherein the first metal layer further comprises a plurality of connection lines, and two adjacent third metal lines in the first direction are electrically connected through the connection lines.

5. The display panel according to claim 3, wherein two adjacent third metal lines in the first direction are insulated;

the first metal layer further comprises a source/drain of a transistor in the pixel circuit, and the electrode is connected with the source/drain through a via hole; at least part of the through holes are positioned in the light emitting area, and the source/drain electrodes are used as the third metal lines.

6. The display panel according to claim 3, wherein a length of the third metal line in the first direction is greater than a length of the second metal line in the light emitting region in the first direction.

7. The display panel according to claim 3, wherein the first metal line, the second metal line, and the third metal line are each symmetrical with respect to a second center line of the light emitting region in at least some of the light emitting regions, the second center line being perpendicular to the first center line.

8. The display panel according to claim 3, wherein the first metal layer further comprises a plurality of fourth metal lines, each of at least some of the light emitting regions comprises at least some of the fourth metal lines, and the number of the fourth metal lines in each of the light emitting regions is at least two, and at least two of the fourth metal lines are symmetrically distributed with respect to the first metal line in the light emitting region.

9. The display panel according to any one of claims 1 to 8, wherein the light-emitting layers include at least a first color light-emitting layer, a second color light-emitting layer, and a third color light-emitting layer, and the light-emitting regions include a first color light-emitting region, a second color light-emitting region, and a third color light-emitting region; in the light emitting areas with the same light emitting color, the distribution positions of the metal wires in the first metal layer are the same.

10. The display panel according to any one of claims 1 to 8, wherein one of the first metal line and the second metal line is a data line, and the other is a power supply line; the line width of the second metal line and the line width of the third metal line are both in negative correlation with the pixel density of the display panel.