CN114203551A - Enhanced HEMT device structure and preparation method thereof - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The invention discloses an enhanced HEMT device structure and a preparation method thereof. The preparation method comprises the following steps: arranging a mask on a first semiconductor layer to cover a first region on the surface of the first semiconductor layer and expose a second region on the surface of the first semiconductor layer, wherein the first region comprises regions corresponding to a source electrode, a drain electrode and a grid electrode; growing a second semiconductor layer on the first semiconductor layer, enabling the second semiconductor layer to at least cover the second area, and enabling the first semiconductor layer and the second semiconductor layer to be matched to form a heterojunction structure; and removing the mask, manufacturing a source electrode, a drain electrode and a grid electrode in the first region, and electrically contacting the source electrode and the drain electrode with the second semiconductor layer respectively. The preparation method provided by the invention avoids the influence on the device performance caused by the etching process, and the prepared HEMT device has the advantages of high structural threshold voltage, high electron mobility, high current density, large transconductance, simple preparation process, low cost and suitability for large-scale production.
Description
Technical Field
The invention relates to an enhanced HEMT device structure and a preparation method thereof, belonging to the technical field of micro-nano manufacturing.
Background
The HEMT device is fabricated by making use of a two-dimensional electron gas formed by a heterojunction structure of a semiconductor. Group III nitride semiconductors are capable of forming a two-dimensional electron gas at a high concentration on a heterojunction structure (e.g., A1GaN/GaN) due to piezoelectric polarization and spontaneous polarization effects, as compared to a heterojunction structure (e.g., AlGaAs/GaAs) formed of group III-VI nitrides. The barrier layer generally does not need to be doped in HEMT devices made using group III nitrides. The III group nitride has the characteristics of large forbidden bandwidth, higher saturated electron drift velocity, high critical breakdown electric field, extremely strong radiation resistance and the like, and can meet the working requirements of a next generation of power electronic system on higher power, higher frequency, smaller volume and higher temperature of a power device.
In a conventional HEMT device structure, a source electrode and a drain electrode are naturally turned on, and a certain negative voltage needs to be applied to a gate electrode to cut off a channel. For large scale integrated circuits, it may bring about a certain false start-up hidden trouble. The enhancement type HEMT device can realize channel cutoff when the grid voltage is zero or no bias voltage is applied, is safer for a power electronic device, has higher system stability, can prevent misoperation for a radio frequency microwave device, and improves the compatibility of the system.
Currently, the methods for realizing the enhancement type HEMT device mainly include injecting F ions into a gate region of the device, forming a p-type cap layer in a device structure, and adopting a thin barrier layer or a groove gate structure. However, these techniques have certain disadvantages, for example, the barrier layer is etched by the F plasma during the implantation process, which results in the performance degradation of the device; although the thin barrier layer technology does not need to etch the barrier layer, the thinner barrier layer can cause the saturation current of the device to be smaller; the device adopting the p-type cap layer has the problems of small threshold voltage, complex gate drive circuit, small working voltage range, limited high-frequency application and the like; the concave gate structure has the problems of complex etching interface repairing process, low gate dielectric reliability, low gate channel electron mobility, poor threshold voltage stability, partial lattice damage and the like.
Disclosure of Invention
The invention mainly aims to provide an enhanced HEMT device structure and a preparation method thereof, so as to overcome the defects of the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a preparation method of an enhanced HEMT device structure, which comprises the following steps:
arranging a mask on a first semiconductor layer to cover a first region on the surface of the first semiconductor layer and expose a second region on the surface of the first semiconductor layer, wherein the first region comprises regions corresponding to a source electrode, a drain electrode and a grid electrode;
growing a second semiconductor layer on the first semiconductor layer, enabling the second semiconductor layer to at least cover the second area, and enabling the first semiconductor layer and the second semiconductor layer to be matched to form a heterojunction structure;
and removing the mask, manufacturing a source electrode, a drain electrode and a grid electrode in the first region, and electrically contacting the source electrode and the drain electrode with the second semiconductor layer respectively.
The embodiment of the invention also provides an enhanced HEMT device structure prepared by the method.
Compared with the prior art, the invention has the beneficial effects that:
1) the preparation of the enhanced HEMT device structure is realized by selecting the secondary growth barrier layer, the influence on the device performance caused by the etching process is avoided, the prepared HEMT device has high threshold voltage, high electron mobility, high current density, large transconductance, simple preparation process and low cost, and is suitable for large-scale production.
2) By processing the mask into a shape having a wide top and a narrow bottom so as to form the barrier layer without contact with the mask, the mask can be more easily peeled off.
3) By arranging the insertion layer between the channel layer and the barrier layer, the appearance smoothness of the channel interface can be ensured, and the electron mobility can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments recorded in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of an enhancement mode HEMT device structure provided in an off state in accordance with an exemplary embodiment of the present invention;
fig. 2 is a schematic diagram of an enhancement mode HEMT device structure in an on state according to an exemplary embodiment of the present invention;
fig. 3a to 3h are flow charts of manufacturing an enhancement mode HEMT device structure according to an exemplary embodiment of the present invention.
Detailed Description
In view of the defects of the prior art, the inventors of the present invention have made extensive studies and practice to provide a technical solution of the present invention, which can avoid the negative effects caused by the etching process, and the prepared HEMT device has the advantages of high threshold voltage, high electron mobility, large current density, and the like, and the technical solution, the implementation process thereof, and the principle thereof will be further explained as follows.
One aspect of the embodiments of the present invention provides a method for manufacturing an enhanced HEMT device structure, including:
arranging a mask on a first semiconductor layer to cover a first region on the surface of the first semiconductor layer and expose a second region on the surface of the first semiconductor layer, wherein the first region comprises regions corresponding to a source electrode, a drain electrode and a grid electrode;
growing a second semiconductor layer on the first semiconductor layer, enabling the second semiconductor layer to at least cover the second area, and enabling the first semiconductor layer and the second semiconductor layer to be matched to form a heterojunction structure;
and removing the mask, manufacturing a source electrode, a drain electrode and a grid electrode in the first region, and electrically contacting the source electrode and the drain electrode with the second semiconductor layer respectively.
The first semiconductor layer comprises a channel layer and an insertion layer arranged on the channel layer, the second semiconductor layer comprises a barrier layer, the channel layer, the insertion layer and the barrier layer form a heterojunction structure, two-dimensional electron gas is formed in the channel layer located right below the barrier layer, and after a source electrode is manufactured and a drain electrode is arranged, high-temperature rapid annealing is carried out on source electrode metal and drain electrode metal to enable the source electrode and the drain electrode to be connected with the two-dimensional electron gas.
Further, the channel layer, the insertion layer and the barrier layer are made of any one selected from group III nitride or group III-V compound semiconductor materials, and the group III nitride or group III-V compound semiconductor has a polarity set such that when a zero bias or no bias is applied to the gate of the HEMT device structure, no two-dimensional electron gas is accumulated in a local region of the heterojunction structure directly below the gate, and when the gate voltage is greater than the threshold voltage of the HEMT device structure, a two-dimensional electron gas can be formed in a local region of the heterojunction structure directly below the gate, thereby achieving the connection between the source and the drain.
Furthermore, the number of the masks is multiple, and the masks respectively cover the areas of the surface of the first semiconductor layer, which correspond to the source electrode, the drain electrode and the grid electrode.
Furthermore, the second semiconductor layer is not in contact with the mask, so that when the mask is removed by a wet etching method in the following step, the etching solution is more easily in contact with the lower portion of the mask through the gap between the second semiconductor layer and the mask.
In some embodiments, the mask may include a first portion and a second portion stacked in this order in a direction away from the first semiconductor layer, the first portion having a diameter smaller than that of the second portion, for example, the mask may be T-shaped in longitudinal section.
Further, the thickness of the second semiconductor layer is smaller than the thickness of the first portion of the mask.
The mask is processed into a shape with a wide upper part and a narrow lower part so as to be convenient for depositing and forming the second semiconductor layer which is not in contact with the mask, and the mask and the second semiconductor layer deposited on the mask are beneficial to be removed integrally in a follow-up process.
In some embodiments, the method of processing to form the mask may include: and arranging a continuous mask layer on the first semiconductor layer, and etching the mask layer to form the mask.
In some embodiments, the method for processing and forming the mask may specifically include:
sequentially arranging a continuous first mask layer and a continuous second mask layer on the first semiconductor layer;
and carrying out dry etching and/or wet etching on the first mask layer and the second mask layer so as to form the mask.
Further, after the growth of the second semiconductor layer is completed, the mask is removed by wet etching.
Further, the preparation method further comprises the following steps: and forming a dielectric layer on the second semiconductor layer, continuously covering the region of the surface of the first semiconductor layer, which corresponds to the grid electrode, with the dielectric layer, and then manufacturing the grid electrode on the dielectric layer.
Further, the preparation method specifically comprises the following steps: and firstly, manufacturing a source electrode and a drain electrode on the first semiconductor layer, then forming the dielectric layer on the second semiconductor layer and the first semiconductor layer, and then manufacturing a grid electrode on the dielectric layer.
And the dielectric layer is also used as a passivation layer on the surface of the device.
Further, the HEMT device structure is formed on a substrate, and the substrate may be made of any one of sapphire, silicon carbide, and silicon, but is not limited thereto.
In some cases, a buffer layer may be formed on the substrate, and then the HEMT device structure may be fabricated on the buffer layer to relieve stress caused by lattice mismatch between different material layers, and the material of the buffer layer may include, but is not limited to, A1GaN, AlN or GaN/AlN superlattice.
In another aspect, the embodiment of the invention also provides an enhanced HEMT device structure prepared by the method.
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings and specific embodiments, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Unless otherwise specified, the embodiments of the present invention involving, for example, epitaxy, dry etching, wet etching, and metal deposition are well known to those skilled in the art, and the embodiments involving, for example, processing masks, applying photoresist, removing photoresist, etc. during the manufacturing process are also common means in the art.
Referring to fig. 1, an enhancement HEMT device structure includes: a substrate 1, and a buffer layer 2, a GaN channel layer 3 and an AlN insert layer 4 formed on the substrate 1 in this order, the AlN insertion layer 4 is formed with a barrier layer 5 on regions thereof other than the source electrode 6, the drain electrode 8 and the gate electrode 7, a heterojunction structure is formed between the barrier layer 5 and the channel layer 2, so that a two-dimensional electron gas 9 is formed in the channel layer 3 right below the barrier layer 5, and partial regions of the source electrode 6 and the drain electrode 8 are covered on the barrier layer 5, so that the source electrode 6 and the drain electrode 8 form good ohmic contact with the heterojunction structure, a dielectric layer 10 is continuously covered on the barrier layer 5 and the insertion layer 4 between the source electrode 6 and the drain electrode 8, the area of the dielectric layer 10 corresponding to the grid electrode 7 is downwards sunken, the grid electrode 7 is manufactured at the sunken position to form a concave grid, and the grid 7 is laterally expanded towards two sides above the concave part so as to better realize grid control.
In the HEMT device structure provided in the embodiment of the present invention, when zero bias or no bias is applied to the gate 7, the source 6 and the drain 8 are in an off state because there is no two-dimensional electron gas 9 in the channel layer 3 under the gate 7, as shown in fig. 1; when a positive bias is applied to the gate 7 and Vg > Vth (Vg represents a gate voltage and Vth represents a device threshold voltage), electrons accumulate in the channel layer 3 under the gate 7, the channel is turned on, and the source 6 and the drain 8 are in a connected state, as shown in fig. 2.
In practical operation, the HEMT device structure provided in this embodiment has higher system safety and reduces leakage loss of the system compared to a depletion mode HEMT device, because the device is in an off state when zero bias or no bias is applied to the gate 7.
Specifically, the preparation method of the enhanced HEMT device structure comprises the following steps:
1) epitaxially growing a buffer layer 2, a GaN channel layer 3 and an AlN insertion layer 4 in this order on a substrate 1, as shown in fig. 3 a;
2) sequentially growing a silicon dioxide mask layer 11 with the thickness of 300nm and a silicon nitride hard mask layer 12 with the thickness of 300nm on the AlN insertion layer 4, wherein the silicon dioxide mask layer 11 and the silicon nitride mask layer 12 may be grown by Plasma Enhanced Chemical Vapor Deposition (PECVD), inductively coupled plasma enhanced chemical vapor deposition (ICPCVD), Low Pressure Chemical Vapor Deposition (LPCVD), or the like, as shown in fig. 3 b;
3) coating photoresist on a selected area on the silicon nitride mask layer 12, etching away the silicon nitride mask layer 12 in an area which is not coated with the photoresist in a dry etching mode, over-etching a silicon dioxide mask layer 11 with a part of thickness, forming a corresponding groove in the selected area, and then removing the photoresist, wherein the selected area specifically comprises a source electrode, a drain electrode and a gate electrode area of the HEMT device structure, and the dry etching mode can be Reactive Ion Etching (RIE), inductively coupled plasma etching (ICP), magnetic enhanced reactive ion etching (MERLE) and the like, as shown in FIG. 3 c;
4) wet etching the device structure formed in the step 3) by hydrofluoric acid (HF) or hydrofluoric acid buffer solution (BOE, BHF), removing the silicon dioxide mask layer at the bottom of the groove and the local regions of the silicon dioxide mask layer and the silicon nitride mask layer at the side wall of the groove, and finally etching to form the T-shaped hard mask 13 and expose the surface of the corresponding source, drain and gate regions on the AlN insertion layer 4 in the etching process, wherein the reaction speed of the etching solution and the silicon dioxide is far faster than that of the silicon nitride (the reaction formula of the silicon dioxide and the hydrofluoric acid is SiO2+6HF ═ H2+ SiF6+2H2O), the top width of the T-shaped hard mask 13 corresponding to the source and drain regions is 200 μm, the bottom width is 199 μm, and the top width of the T-shaped hard mask 13 corresponding to the gate region is 2 μm, the bottom width is 1 μm, and the top height (i.e. the thickness of the silicon nitride hard mask layer 11) of all the T-shaped masks 13 is 300nm, and the bottom height (i.e. the thickness of the silicon dioxide mask layer 10) is 300nm, as shown in fig. 3 d;
5) cleaning the device structure formed in the step 4) with inorganic and organic chemicals, removing surface impurities, then transferring to a PVD (physical vapor deposition) device for high temperature, high vacuum, plasma treatment and the like to further remove the surface impurities, and depositing a certain thickness of III-group nitride or III-V compound semiconductor as a barrier layer 5 on the surface of the T-shaped hard mask 13 and the surface of the AlN insert layer 4 between the T-shaped hard masks 13, wherein a heterojunction structure is formed between the barrier layer 5 and the channel layer 3, and a two-dimensional electron gas 9 is formed in the channel layer 3 right below the barrier layer 5, wherein the thickness of the barrier layer 5 is smaller than the bottom height of the T-shaped hard mask 13, and the specific thickness of the barrier layer 5 can be set according to the device requirements, as shown in FIG. 3 e;
6) removing the T-shaped hard mask 13 by etching with chemicals such as BOE, BHF, HF, etc. (the III-group nitride or III-V compound semiconductor on the surface of the T-shaped hard mask 13 is also removed), as shown in FIG. 3 f;
7) depositing metal on the surface of the device structure formed in the step 6), stripping off the metal outside the source and drain regions to form a source 6 and a drain 8, wherein the source 6 and the drain 8 cover partial regions of the barrier layer 5, so that the source 6 and the drain 8 form good ohmic contact with the heterojunction structure, and then performing rapid annealing at 850 ℃ for 30 seconds to connect the source 6 and the drain 8 with two-dimensional electron gas 9, as shown in fig. 3g, wherein the metal forming the source 6 and the drain 8 can be selected from multiple layers of metals such as titanium/aluminum/nickel/gold, and the thickness can be 15nm/220nm/40nm/50 nm;
8) and forming a dielectric layer 10 on the surfaces of the barrier layer 5 and the insertion layer 4 between the source electrode 6 and the drain electrode 8, and depositing a grid electrode 7 on the dielectric layer 10 corresponding to the grid electrode region to enable the grid electrode 7 to form Schottky contact with the heterojunction structure, wherein the dielectric layer 10 is provided with a recess in the region corresponding to the grid electrode, and the grid electrode 7 is of a recessed grid structure, as shown in fig. 3h, two layers of metals such as nickel/gold and the like can be selected as the metal for forming the grid electrode 7, and the thickness can be correspondingly 20nm/200nm, so that the preparation of the enhanced HEMT device structure is completed.
According to the preparation method of the HEMT device structure provided by the embodiment of the invention, on one hand, the barrier layer is formed in a mode of carrying out secondary epitaxial growth on the III group nitride or III-V group compound semiconductor in the selected area, so that the etching process is avoided, a grid area channel without lattice damage can be realized, and a higher threshold voltage can be realized because two-dimensional electron gas is not formed in the area below the electrode; on the other hand, the problems of low electron mobility, reduced two-dimensional surface density and the like caused by the damage of a pure concave gate structure formed by an etching process to two-dimensional electron gas under a gate in the traditional technology are solved, the concave gate structure formed by the preparation method in the embodiment of the invention has more controllable groove depth uniformity and repeatability, the two-dimensional electron gas density among the gate, the source, the gate and the drain is high, and the enhancement type HEMT device with high current density and large transconductance can be realized; meanwhile, the AlN insert layer is arranged between the channel layer and the barrier layer, so that the smoothness of the appearance of the channel interface can be ensured, and the electron mobility can be improved.
In summary, the preparation method provided in the embodiment of the invention avoids the damage of the etching process in the conventional method to the device, and has the advantages of simple preparation process, low cost and easy mass production.
In addition, the inventors of the present invention have also made experiments with reference to the above examples and by using other raw materials, process operations, and process conditions described in the present specification, and have obtained preferable results.
It should be understood that the technical solution of the present invention is not limited to the above specific embodiments, and all technical modifications made according to the technical solution of the present invention fall within the protection scope of the present invention without departing from the spirit of the present invention and the protection scope of the claims.
Claims (12)
1. A preparation method of an enhanced HEMT device structure is characterized by comprising the following steps:
arranging a mask on a first semiconductor layer to cover a first region on the surface of the first semiconductor layer and expose a second region on the surface of the first semiconductor layer, wherein the first region comprises regions corresponding to a source electrode, a drain electrode and a grid electrode;
growing a second semiconductor layer on the first semiconductor layer, enabling the second semiconductor layer to at least cover the second area, and enabling the first semiconductor layer and the second semiconductor layer to be matched to form a heterojunction structure;
and removing the mask, manufacturing a source electrode, a drain electrode and a grid electrode in the first region, and electrically contacting the source electrode and the drain electrode with the second semiconductor layer respectively.
2. The method of claim 1, wherein: the mask is multiple and covers the areas of the surface of the first semiconductor layer corresponding to the source electrode, the drain electrode and the grid electrode respectively.
3. The method of claim 2, wherein: the second semiconductor layer is not in contact with the mask.
4. The production method according to claim 3, characterized in that: the mask comprises a first part and a second part which are sequentially overlapped in the direction far away from the first semiconductor layer, and the diameter of the first part is smaller than that of the second part.
5. The method of claim 4, wherein: the thickness of the second semiconductor layer is less than the thickness of the first portion of the mask.
6. The production method according to claim 5, characterized by comprising: and arranging a continuous mask layer on the first semiconductor layer, and etching the mask layer to form the mask.
7. The method according to claim 6, comprising:
sequentially arranging a continuous first mask layer and a continuous second mask layer on the first semiconductor layer;
and carrying out dry etching and/or wet etching on the first mask layer and the second mask layer so as to form the mask.
8. The method of claim 7, further comprising: and after the growth of the second semiconductor layer is finished, removing the mask by adopting a wet etching mode.
9. The method of claim 8, further comprising: and forming a dielectric layer on the second semiconductor layer, continuously covering the region of the surface of the first semiconductor layer, which corresponds to the grid electrode, with the dielectric layer, and then manufacturing the grid electrode on the dielectric layer.
10. The method according to claim 9, comprising: and firstly, manufacturing a source electrode and a drain electrode on the first semiconductor layer, then forming the dielectric layer on the second semiconductor layer and the first semiconductor layer, and then manufacturing a grid electrode on the dielectric layer.
11. The method of claim 1, wherein: the first semiconductor layer includes a channel layer and an insertion layer disposed on the channel layer, and the second semiconductor layer includes a barrier layer.
12. An enhancement mode HEMT device structure made by the method of any one of claims 1-11.
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