CN114189637A - A/D conversion method, device and converter applied to image sensor - Google Patents
A/D conversion method, device and converter applied to image sensor Download PDFInfo
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Abstract
A/D conversion method, device and converter for image sensor application, through dividing N-bit of N-bit converter into the first sector to M section sequentially from low bit to high bit, confirm the target bit in the target sector, compare the sampling voltage with the binary reference voltage that the target bit corresponds to, if the sampling voltage is smaller than the binary reference voltage that the target bit corresponds to, from the next high bit to converter lowest bit successive approximation conversion from this sector, otherwise transfer to the next sector, confirm the target bit in the target sector, compare the sampling voltage with the binary reference voltage that the target bit corresponds to. And if the sampling voltage is smaller than the binary reference voltage corresponding to the target bit, performing successive approximation conversion from the second highest bit to the lowest bit of the converter from the section, and so on, and if the conversion to the lowest bit still has residual conversion times, performing oversampling on the binary reference voltage corresponding to the lowest bit in the N-bit by using the residual conversion times.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to an A/D conversion method, device and converter applied to an image sensor.
Background
Dynamic range is an important index parameter for image sensors. It is defined as the ratio of the maximum and minimum values of the variation signal. The maximum value is determined by the maximum high-illumination scene signal and the minimum value is determined by the readout noise in the low-illumination scene.
Signal-to-noise ratio (SNR) is another important indicator parameter for image sensors. Which is defined as the ratio of signal to noise.
Successive approximation a/D converters have the advantages of high speed (compared to ramp a/D converters) and small area (compared to parallel comparison a/D converters), and are therefore widely used in data acquisition circuits. The successive approximation algorithm compares the sampled signals (voltage, current, etc. …) with the estimated approximate values, reduces the estimated range according to the previous comparison result, and provides new approximate values to compare with the sampled signals. And obtaining the conversion result after approximation through multiple comparisons.
The conventional algorithm for successive approximation a/D conversion is to sequentially compare the MSB (most significant bit) to the LSB (least significant bit). Take a 12-bit voltage A/D converter as an example. The estimated approximation may be expressed as Vref(b 122-1+b 112-2+…b12-12) In the above conversion process, the successive approximation a/D principle is adopted, so that the high-order band is needed when the low-order generation reference voltage is needed in the calculation process. The first step is to sample the voltage with b12The predicted values are compared for 1 (i.e., binary 100000000000). MSB (b) if the sampled voltage is greater than the estimated value12) The value will remain "1", MSB (b) if less12) The estimated value is changed to "0". The (MSB-1) bits are compared next until LSB.
Disclosure of Invention
Embodiments of the present invention provide an a/D conversion method, apparatus and converter for image sensor application, so as to provide an a/D converter with a higher dynamic range.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
an a/D conversion method for an image sensor application, comprising:
dividing N-bits of an N-bit converter into a first section to an Mth section from low bits to high bits in sequence, wherein the value of M is not less than 2, and the value of N is not less than 2;
acquiring sampling voltage, and selecting a target section;
comparing the sampled voltage with a binary reference voltage corresponding to the target segment, and if the sampled voltage is less than the binary reference voltage corresponding to the target segment, setting all remaining segments to 0, then determining a target bit from the target section, comparing the sampling voltage with a binary reference voltage corresponding to the target bit, and records the comparison result to judge whether the target bit is the lowest bit in the N-bit, if not, selecting a next target bit from the target sector based on a predetermined priority, and performing an action to compare the sampled voltage to a binary reference voltage corresponding to the target bit, if the binary reference voltage is the lowest bit in the N-bit, oversampling is carried out on the binary reference voltage corresponding to the lowest bit in the N-bit by adopting the residual conversion times;
if the sampling voltage is larger than the binary reference voltage corresponding to the target section, taking the next section as the target section, and continuing to repeat the operation: comparing the sampled voltage with a binary reference voltage corresponding to the target segment, and subsequent actions
Alternatively, in the a/D conversion method applied to the image sensor,
the N-bit converter is a 12-bit converter, and the first section to the Mth section comprise: a first section, a second section, and a third section.
Alternatively, in the a/D conversion method applied to the image sensor,
the range of the first section is 5-1bit, the range of the second section is 9-6bit, and the range of the third section is 12-10 bit.
Alternatively, in the a/D conversion method applied to the image sensor,
when the target bit is the first segment, oversampling a binary reference voltage corresponding to a lowest bit of the N-bits by using a remaining number of conversion times includes:
oversampling a binary reference voltage corresponding to the least significant bit LSB in the N-bit by adopting the remaining 7 conversion times;
when the target bit is the second segment, oversampling the binary reference voltage corresponding to the lowest bit of the N-bit by using the remaining conversion times includes:
and oversampling the binary reference voltage corresponding to the LSB of the lowest bit in the N-bit by adopting the residual 2 times of conversion.
Optionally, the a/D conversion method applied to the image sensor further includes:
editing the interval range from the first section to the Mth section based on a user input instruction.
An a/D conversion apparatus for an image sensor application, comprising:
the section dividing unit is used for sequentially dividing the N-bit of the N-bit converter into a first section to an Mth section from low order to high order, wherein the value of M is not less than 2, and the value of N is not less than 2;
the voltage acquisition unit is used for acquiring sampling voltage;
a comparison unit for:
selecting a target section;
comparing the sampled voltage with a binary reference voltage corresponding to the target segment, and if the sampled voltage is less than the binary reference voltage corresponding to the target segment, setting all remaining segments to 0, then determining a target bit from the target section, comparing the sampling voltage with a binary reference voltage corresponding to the target bit, and records the comparison result to judge whether the target bit is the lowest bit in the N-bit, if not, selecting a next target bit from the target sector based on a predetermined priority, and performing an action to compare the sampled voltage to a binary reference voltage corresponding to the target bit, if the binary reference voltage is the lowest bit in the N-bit, oversampling is carried out on the binary reference voltage corresponding to the lowest bit in the N-bit by adopting the residual conversion times;
if the sampling voltage is larger than the binary reference voltage corresponding to the target section, taking the next section as the target section, and continuing to repeat the operation: and comparing the sampling voltage with a binary reference voltage corresponding to the target section, and performing subsequent actions.
Optionally, in the a/D conversion apparatus applied to the image sensor, the N-bit converter is a 12-bit converter, and the first section to the M-th section include: a first section, a second section, and a third section.
Optionally, in the a/D conversion device for image sensor application,
the range of the first section is 5-1bit, the range of the second section is 9-6bit, and the range of the third section is 12-10 bit.
Optionally, in the a/D conversion device for image sensor application,
when the target bit is the first segment, oversampling a binary reference voltage corresponding to a lowest bit of the N-bits by using a remaining number of conversion times includes:
oversampling a binary reference voltage corresponding to the least significant bit LSB in the N-bit by adopting the remaining 7 conversion times;
when the target bit is the second segment, oversampling the binary reference voltage corresponding to the lowest bit of the N-bit by using the remaining conversion times includes:
and oversampling the binary reference voltage corresponding to the LSB of the lowest bit in the N-bit by adopting the residual 2 times of conversion.
An a/D converter to which an a/D conversion device having any of the image sensor applications described above is applied. Based on the technical scheme, in the scheme provided by the embodiment of the invention,
according to the scheme, the N-bit of the N-bit converter is sequentially divided into a first section to an Mth section from low order to high order, a target bit is determined in the target section, a sampling voltage is compared with a binary reference voltage corresponding to the target bit, and if the sampling voltage is smaller than the binary reference voltage corresponding to the target bit, successive approximation conversion is carried out from the next high order to the lowest order of the converter from the section. And if the sampling voltage is greater than the binary reference voltage corresponding to the target bit, switching to the next section, determining the target bit in the target section, and comparing the sampling voltage with the binary reference voltage corresponding to the target bit. If the sampling voltage is less than the binary reference voltage corresponding to the target bit, the section is gradually converted from the second highest bit to the lowest bit of the converter, and so on, the highest section can be converted to the M section, and if the conversion to the lowest bit still has the residual conversion times during the partition conversion, the binary reference voltage corresponding to the lowest bit of the N-bit is oversampled by using the residual conversion times. According to the scheme, the reading noise in a low-illumination scene can be reduced on the premise of not reducing the signal to noise ratio, and the dynamic range is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic flow chart of an A/D conversion method applied to an image sensor according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an a/D conversion device applied to an image sensor disclosed in an embodiment of the present application;
fig. 3 is a schematic structural diagram of an a/D conversion device disclosed in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. To more particularly emphasize implementation independence, this description refers to a number of modules or units. For example, a module or unit may be implemented by hardware circuits comprising custom VLSI circuits or gate arrays, such as logic chips, transistors, or other components. A module or unit may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.
Modules or units may also be implemented in software for execution by various forms of processors. An executable code module may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be formed as an object, procedure, or function. Nevertheless, the executables of an identified module or element need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module or element and achieve the desired result for the module or element.
Indeed, a module or unit of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Similarly, operational data may be identified and illustrated herein within modules or units, and may be embodied in any suitable form and organized within any suitable data structure. The operational data may be collected as a single data set, or may be distributed over different locations having different storage devices, and may exist, at least partially, merely as electronic signals on a system or network.
Reference throughout this specification to "one embodiment" or similar language means that a feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment. Furthermore, the described features, structures, or characteristics of the invention may be combined in any suitable manner in one or more embodiments. The following description will provide many specific details such as examples of programming, software modules, user selections, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., to provide an understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown in detail to avoid obscuring the invention.
Aiming at the application of an image sensor, the application provides a novel algorithm of a reverse segmented successive approximation type A/D converter, which can reduce the read-out noise in a low-illumination scene and improve the dynamic range under the condition of not losing the signal-to-noise ratio. This algorithm is based on the following three theories.
1. Multiple oversampling re-averaging may reduce readout noise. The relationship between readout noise and oversampling number is: the readout noise of multiple oversampling re-averaging is single sampling noise/(the square of the oversampling number of times);
2. the image sensor has optical shot noise. The relationship of the optical shot noise to the signal is: shot noise-the evolution of the signal;
3. the theoretical SNR (signal-to-noise ratio) of an ideal N-bit ADC is given by the following equation: SNR 6.02N +1.76 dB.
Based on the above principle, the present application discloses an a/D conversion method applied to an image sensor, referring to fig. 1, the method comprising:
step S101: sequentially dividing N-bits of the N-bit converter into a first section to an Mth section from low bits to high bits;
in the scheme, the N-bit converter refers to an A/D converter, N refers to a total bit number, the value of N is greater than 2, and when N is 12, the N-bit converter can be a 12-bit converter.
In the present scheme, the N-bit is divided into M sections, the value of M is as small as 2, for example, 2, 3, 4, etc., and the range size of each section can be set by itself according to the user requirement, taking 12-bit as an example, in the present scheme, the N-bit is divided into a first section, a second section, and a third section, the first section, the second section, and the third section can be equally divided into 12-bit, the first section can be configured as 5-1bit, the second section can be configured as 9-6bit, and the third section can be configured as 12-10bit, etc.
In the scheme, the range from the first section to the Mth section can be edited based on a user input instruction.
Step S102: acquiring a sampling voltage;
the sampling voltage is analog quantity voltage which needs to be subjected to A/D conversion in the application;
step S103: selecting a target section;
in this step, when the conversion starts, the first section may be directly used as a target section, and the values of the bits in the target section may be configured.
Step S104: comparing the sampling voltage with a binary reference voltage corresponding to the target section;
each target segment corresponds to a binary reference voltage, in this step, the sampling voltage is compared with the binary reference voltage corresponding to the target segment, when the sampling voltage is smaller than the binary reference voltage corresponding to the target segment, step S105 is executed, otherwise, step S1011 is executed;
step S105: all remaining segments are set to 0;
step S106: determining a target bit from the target sector;
when configuring the value of each bit in a target section, firstly configuring the highest bit in each section, namely firstly taking the highest bit as a target bit, and after the highest bit configuration is finished, taking the next highest bit in the target section as the target bit until the lowest bit in the N-bit is taken as the target bit;
step S107: comparing the sampling voltage with a binary reference voltage corresponding to the target bit, and recording a comparison result;
in this step, the most significant bit MSB in the target segment is configured first, and during comparison, the binary reference voltage corresponding to the most significant bit is obtained first, for example, the most significant bit in the first segment is 10000, and the corresponding target voltage is a preset reference voltage, at this time, the sampling voltage is compared with the preset reference voltage, and the comparison result is: if the sampling voltage is greater than the preset reference voltage, keeping the target bit to be 1, and if the sampling voltage is less than the preset reference voltage, modifying the target bit to be 0;
in the technical solution disclosed in the embodiment of the present application, in two adjacent target bits, the binary reference voltage corresponding to the target bit with the higher order is 2 times that corresponding to the target bit with the lower order.
Step S108: judging whether the target bit is the lowest bit in the N-bit, if so, executing step S109; otherwise, executing step S1010;
step S109: oversampling a binary reference voltage corresponding to the lowest bit in the N-bit by using the residual conversion times;
in the scheme, for example, a 12-bit converter is used, the range of the first section is 5-1bit, the range of the second section is 9-6bit, and the range of the third section is 12-10bit, when the binary reference voltage corresponding to the least significant bit LSB in the first section is compared with the sampling voltage, oversampling is performed for the remaining number of times, that is, oversampling is performed on the binary reference voltage corresponding to the least significant bit LSB in the N-bit by using the remaining (12-5) to 7 conversion times; by oversampling, it is meant that the sampled voltage is compared with a binary reference voltage corresponding to 1 to determine whether the least significant bit LSB of the N-bit is 1 or 0 for the remaining 7 times.
And after comparing the binary reference voltage corresponding to the least significant bit LSB in the second section with the sampling voltage, oversampling the binary reference voltage corresponding to the least significant bit LSB in the N-bit by using the remaining (12-1-9) ═ 2 conversion times.
Step S1010: selecting a next target bit from the target section based on a preset priority, and performing an action to compare the sampled voltage with a binary reference voltage corresponding to the target bit;
step S1011: taking the next section as the target section, and continuing to repeat the operation: and comparing the sampling voltage with a binary reference voltage corresponding to the target section, and performing subsequent actions.
The step of using the next sector as the target sector means that the selection is performed sequentially from the low sector to the high sector, and the target bit inside each sector is from the high bit ratio to the low bit ratio.
In this scheme, if the sampling voltage is low, for example, in the range of the first section, the second and third sections are set to 0, and the ratio from high to low in the first section is set. If the sampling voltage is high, the sampling voltage jumps from the first section to the second section, even to the third section, and then goes from the high position of the target section to the low position. The highest bit to the lowest bit in the high segment will continue to be higher than the highest bit to the lowest bit in the low segment. Until it is compared to N-bit or until the number of transitions is exhausted.
According to the technical scheme disclosed by the embodiment of the application, the algorithm of the type reverse inter-partition successive approximation type A/D converter can reduce the read noise in a low-illumination scene on the premise of not reducing the signal to noise ratio, the dynamic range is improved, and the method has a wide application prospect in the application of an image sensor.
Specifically, in the scheme, the N-bit of the N-bit converter is sequentially divided into a first section to an Mth section from a low bit to a high bit, a target bit is determined in the target section, the sampling voltage is compared with the binary reference voltage corresponding to the target bit, and if the sampling voltage is smaller than the binary reference voltage corresponding to the target bit, successive approximation conversion is performed from the second high bit to the lowest bit of the converter in the section. And if the sampling voltage is greater than the binary reference voltage corresponding to the target bit, switching to the next section, determining the target bit in the target section, and comparing the sampling voltage with the binary reference voltage corresponding to the target bit. If the sampling voltage is less than the binary reference voltage corresponding to the target bit, the section is gradually converted from the second highest bit to the lowest bit of the converter, and so on, the highest section can be converted to the M section, and if the conversion to the lowest bit still has the residual conversion times during the partition conversion, the binary reference voltage corresponding to the lowest bit of the N-bit is oversampled by using the residual conversion times. According to the scheme, the reading noise in a low-illumination scene can be reduced on the premise of not reducing the signal to noise ratio, and the dynamic range is improved.
In correspondence with the above method, an a/D conversion apparatus for an image sensor application, comprising:
a section dividing unit 100, configured to divide the N-bit of the N-bit converter from a low bit to a high bit into a first section to an M-th section in sequence;
a voltage acquisition unit 200 for acquiring a sampling voltage;
a comparison unit 300 for:
comparing the sampled voltage with a binary reference voltage corresponding to the target segment, and if the sampled voltage is less than the binary reference voltage corresponding to the target segment, setting all remaining segments to 0, then determining a target bit from the target section, comparing the sampling voltage with a binary reference voltage corresponding to the target bit, and records the comparison result to judge whether the target bit is the lowest bit in the N-bit, if not, selecting a next target bit from the target sector based on a predetermined priority, and performing an action to compare the sampled voltage to a binary reference voltage corresponding to the target bit, if the binary reference voltage is the lowest bit in the N-bit, oversampling is carried out on the binary reference voltage corresponding to the lowest bit in the N-bit by adopting the residual conversion times;
if the sampling voltage is larger than the binary reference voltage corresponding to the target section, taking the next section as the target section, and continuing to repeat the operation: and comparing the sampling voltage with a binary reference voltage corresponding to the target section, and performing subsequent actions.
The device provided by the embodiment of the application can be applied to A/D conversion equipment, such as a PC terminal, a cloud platform, a server cluster and the like. Alternatively, fig. 3 shows a block diagram of a hardware structure of the a/D conversion device, and referring to fig. 3, the hardware structure of the a/D conversion device may include: at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4;
in the embodiment of the application, the number of the processor 1, the communication interface 2, the memory 3 and the communication bus 4 is at least one, and the processor 1, the communication interface 2 and the memory 3 complete mutual communication through the communication bus 4;
the processor 1 may be a central processing unit CPU, or an application Specific Integrated circuit asic, or one or more Integrated circuits configured to implement embodiments of the present invention, etc.;
the memory 3 may include a high-speed RAM memory, and may further include a non-volatile memory (non-volatile memory) or the like, such as at least one disk memory; wherein the memory stores a program and the processor can call the program stored in the memory, the program for:
dividing N-bits of an N-bit converter into a first section to an Mth section from low bits to high bits in sequence, wherein the value of M is not less than 2, and the value of N is not less than 2;
acquiring sampling voltage, and selecting a target section;
comparing the sampled voltage with a binary reference voltage corresponding to the target segment, and if the sampled voltage is less than the binary reference voltage corresponding to the target segment, setting all remaining segments to 0, then determining a target bit from the target section, comparing the sampling voltage with a binary reference voltage corresponding to the target bit, and records the comparison result to judge whether the target bit is the lowest bit in the N-bit, if not, selecting a next target bit from the target sector based on a predetermined priority, and performing an action to compare the sampled voltage to a binary reference voltage corresponding to the target bit, if the binary reference voltage is the lowest bit in the N-bit, oversampling is carried out on the binary reference voltage corresponding to the lowest bit in the N-bit by adopting the residual conversion times;
if the sampling voltage is larger than the binary reference voltage corresponding to the target section, taking the next section as the target section, and continuing to repeat the operation: and comparing the sampling voltage with a binary reference voltage corresponding to the target section, and performing subsequent actions.
An a/D converter to which an a/D conversion device for an image sensor application described in any one of the above embodiments of the present application can be applied.
For convenience of description, the above system is described with the functions divided into various modules, which are described separately. Of course, the functionality of the various modules may be implemented in the same one or more software and/or hardware implementations as the present application.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the system or system embodiments are substantially similar to the method embodiments and therefore are described in a relatively simple manner, and reference may be made to some of the descriptions of the method embodiments for related points. The above-described system and system embodiments are only illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An a/D conversion method for an image sensor application, comprising:
dividing N-bits of an N-bit converter into a first section to an Mth section from low bits to high bits in sequence, wherein the value of M is not less than 2, and the value of N is not less than 2;
acquiring sampling voltage, and selecting a target section;
comparing the sampled voltage with a binary reference voltage corresponding to the target segment, and if the sampled voltage is less than the binary reference voltage corresponding to the target segment, setting all remaining segments to 0, then determining a target bit from the target section, comparing the sampling voltage with a binary reference voltage corresponding to the target bit, and records the comparison result to judge whether the target bit is the lowest bit in the N-bit, if not, selecting a next target bit from the target sector based on a predetermined priority, and performing an action to compare the sampled voltage to a binary reference voltage corresponding to the target bit, if the binary reference voltage is the lowest bit in the N-bit, oversampling is carried out on the binary reference voltage corresponding to the lowest bit in the N-bit by adopting the residual conversion times;
if the sampling voltage is larger than the binary reference voltage corresponding to the target section, taking the next section as the target section, and continuing to repeat the operation: and comparing the sampling voltage with a binary reference voltage corresponding to the target section, and performing subsequent actions.
2. The A/D conversion method for image sensor application according to claim 1, wherein the N-bit converter is a 12-bit converter, and the first section to M-th section include: a first section, a second section, and a third section.
3. The A/D conversion method for image sensor application according to claim 2, wherein the range of the first section is 5-1bit, the range of the second section is 9-6bit, and the range of the third section is 12-10 bit.
4. The A/D conversion method applied to the image sensor according to claim 3, wherein when the target bit is the first section, the oversampling the binary reference voltage corresponding to the lowest bit of the N-bits with the remaining conversion times comprises:
oversampling a binary reference voltage corresponding to the least significant bit LSB in the N-bit by adopting the remaining 7 conversion times;
when the target bit is the second segment, oversampling the binary reference voltage corresponding to the lowest bit of the N-bit by using the remaining conversion times includes:
and oversampling the binary reference voltage corresponding to the LSB of the lowest bit in the N-bit by adopting the residual 2 times of conversion.
5. The a/D conversion method for an image sensor application according to claim 1, further comprising:
editing the interval range from the first section to the Mth section based on a user input instruction.
6. An a/D conversion apparatus for an image sensor application, comprising:
the section dividing unit is used for sequentially dividing the N-bit of the N-bit converter into a first section to an Mth section from low order to high order, wherein the value of M is not less than 2, and the value of N is not less than 2;
the voltage acquisition unit is used for acquiring sampling voltage;
a comparison unit for:
selecting a target section;
comparing the sampled voltage with a binary reference voltage corresponding to the target segment, and if the sampled voltage is less than the binary reference voltage corresponding to the target segment, setting all remaining segments to 0, then determining a target bit from the target section, comparing the sampling voltage with a binary reference voltage corresponding to the target bit, and records the comparison result to judge whether the target bit is the lowest bit in the N-bit, if not, selecting a next target bit from the target sector based on a predetermined priority, and performing an action to compare the sampled voltage to a binary reference voltage corresponding to the target bit, if the binary reference voltage is the lowest bit in the N-bit, oversampling is carried out on the binary reference voltage corresponding to the lowest bit in the N-bit by adopting the residual conversion times;
if the sampling voltage is larger than the binary reference voltage corresponding to the target section, taking the next section as the target section, and continuing to repeat the operation: and comparing the sampling voltage with a binary reference voltage corresponding to the target section, and performing subsequent actions.
7. The A/D conversion apparatus for image sensor application according to claim 6, wherein the N-bit converter is a 12-bit converter, and the first section to M-th section include: a first section, a second section, and a third section.
8. The A/D conversion apparatus for image sensor application according to claim 7, wherein the range of the first section is 5-1bit, the range of the second section is 9-6bit, and the range of the third section is 12-10 bit.
9. The A/D conversion apparatus for image sensor application according to claim 8, wherein said oversampling a binary reference voltage corresponding to a lowest bit of the N-bits with a remaining number of conversion times when the target bit is the first section comprises:
oversampling a binary reference voltage corresponding to the least significant bit LSB in the N-bit by adopting the remaining 7 conversion times;
when the target bit is the second segment, oversampling the binary reference voltage corresponding to the lowest bit of the N-bit by using the remaining conversion times includes:
and oversampling the binary reference voltage corresponding to the LSB of the lowest bit in the N-bit by adopting the residual 2 times of conversion.
10. An a/D converter characterized by being applied with an a/D conversion device for an image sensor application according to any one of claims 6 to 9.
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