CN114188472A - Superconducting circuit with large inductance layer and preparation method thereof - Google Patents

Superconducting circuit with large inductance layer and preparation method thereof Download PDF

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Publication number
CN114188472A
CN114188472A CN202111492420.2A CN202111492420A CN114188472A CN 114188472 A CN114188472 A CN 114188472A CN 202111492420 A CN202111492420 A CN 202111492420A CN 114188472 A CN114188472 A CN 114188472A
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layer
large inductance
superconducting
material layer
superconducting circuit
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应利良
张雪
何桂香
任洁
彭炜
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H10N60/12—Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/805—Constructional details for Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/82—Current path
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

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  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

The present invention provides a superconducting circuit having a large inductance layer and a method for manufacturing the same, the superconducting circuit including: a substrate; a shunt resistor formed on the substrate; a Josephson junction formed on the shunt resistor; a large inductance layer formed on the Josephson junction; a wiring layer formed on the large inductance layer; and the insulating material layer is used for electrically isolating the shunt resistor, the Josephson junction, the large inductance layer and the wiring layer respectively. The superconducting circuit utilizes the design of the medium and small inductors of the original wiring layer, and then designs and adds a special large inductor layer to be applied to the superconducting circuit needing the large inductor, thereby effectively enlarging the size range of the inductor in the superconducting circuit, widening the application scene of the superconducting circuit and improving the integration level of the superconducting circuit; in addition, the large inductance layer made of a specific material can also be used as a large resistance layer at the same time, so that the integration degree of the superconducting circuit can be further improved.

Description

Superconducting circuit with large inductance layer and preparation method thereof
Technical Field
The invention relates to the technical field of superconducting circuit design, in particular to a superconducting circuit with a large inductance layer and a preparation method thereof.
Background
The superconducting circuit includes a circuit using a superconducting josephson junction, such as a superconducting quantum interference device (SQUID), a single flux quantum device (SFQ), and the like.
The superconducting quantum interference device (SQUID) is based on the Josephson effect and flux quantization principle, and its basic structure is that two Josephson junctions are inserted into the superconducting ring, and the SQUID is the most sensitive magnetic flux detecting sensor known at present, and the magnetic flux noise of typical SQUID device is at mu phi0/Hz1/2Magnitude (1 phi)0＝2.07×10-15Wb) with magnetic field noise at fT/Hz1/2Magnitude (1fT ═ 1 × 10)-15T), because of its extremely high sensitivity, can be widely applied to medical heart magnetism brain magnetism, material detection, earth magnetic field, military affairs, earthquake and archaeology, etc. the magnetic flux microscope prepared with it can be engaged in basic research.
Single Flux Quantum devices (SFQ) are superconducting circuit technologies that use a Single Flux Quantum within a josephson junction to represent logic "1" and "0". The clock frequency of the superconducting digital circuit based on the frequency can reach 770GHz, and the superconducting digital circuit can be used for ultra-wideband analog-digital/digital-analog converters, wideband network exchangers, radio astronomical digital autocorrelators, superconducting computers and the like of radar and communication systems. Because of its advantages of high speed and low power consumption, the strategic research is invested in the united states and japan.
The superconducting circuit is generally composed of a Josephson junction and some resistors, inductors and the like which are matched with each other. At present, there are many methods for increasing the integration level of superconducting circuits, and researchers in various countries mainly focus on reducing the size of josephson junctions and increasing the critical current density thereof. In practice, the maximum integration limit in superconducting integrated circuits is not the josephson junction, but rather the parallel connection of resistors and inductors. Some units are researching self-parallel Josephson junctions, parallel resistors can be removed, but the requirement on inductance is not well realized, because the inductance is an indispensable piece of a superconducting integrated circuit and cannot be removed, and meanwhile, the inductances with different sizes are required in the circuit, and if the unit inductance is simply improved, the circuit design of the small inductance is disturbed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a superconducting circuit having a large inductance layer and a method for manufacturing the same, which are used to solve the problems of the superconducting circuit of the prior art, such as the narrow range of the inductance, the limited application scenarios of the superconducting circuit, and the limited integration level of the superconducting circuit.
To achieve the above and other related objects, the present invention provides a method for manufacturing a superconducting circuit having a large inductance layer, the method comprising:
1) providing a substrate, and forming a bypass resistor on the substrate;
2) forming a patterned first insulating material layer with a first opening on the surface of the obtained structure, wherein the bypass resistor is exposed from the first opening;
3) sequentially forming a three-layer film structure of a first superconducting material layer, a barrier material layer and a second superconducting material layer on the surface of the obtained structure;
4) etching the three-layer thin film structure with different patterns from top to bottom to form a Josephson junction;
5) forming a second patterned insulating material layer on the surface of the obtained structure, and forming a large inductance layer on the second insulating material layer;
6) forming a patterned third insulating material layer with a plurality of second openings on the surface of the obtained structure, wherein the second openings respectively expose the large inductance layer and the upper surface of the Josephson junction;
7) and forming a third superconducting material layer on the surface of the obtained structure, and etching the third superconducting material layer to form a wiring layer.
Optionally, step 7) is followed by:
8) forming a fourth insulating material layer on the surface of the structure obtained in the step 7), and patterning the fourth insulating material layer;
9) and forming a fourth superconducting material layer on the surface of the obtained structure, and etching the fourth superconducting material layer to form a grounding layer.
Optionally, step 5) further comprises: etching the second insulating material layer to form a third opening exposing an upper surface of the Josephson junction.
Optionally, the shunt resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.
Based on the above preparation method, the present invention also provides a superconducting circuit having a large inductance layer, the superconducting circuit including:
a substrate;
a shunt resistor formed on the substrate;
a Josephson junction formed on the shunt resistor;
a large inductance layer formed on the Josephson junction;
a wiring layer formed on the large inductance layer;
an insulating material layer electrically isolating the shunt resistor, the Josephson junction, the large inductance layer, and the wiring layer, respectively.
Optionally, the method further comprises: a ground layer formed on the wiring layer, the insulating layer also electrically isolating the ground layer.
Optionally, the shunt resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.
The present invention also provides another method for manufacturing a superconducting circuit having a large inductance layer, the method comprising:
1) providing a substrate, and respectively forming a bypass resistor and a large inductance layer on the substrate;
2) forming a first insulating material layer with a plurality of first openings on the surface of the obtained structure, wherein the bypass resistor and the large inductance layer are respectively exposed from the plurality of first openings;
3) sequentially forming a three-layer film structure of a first superconducting material layer, a barrier material layer and a second superconducting material layer on the surface of the obtained structure;
4) etching the three-layer thin film structure with different patterns from top to bottom to form a Josephson junction;
5) forming a second insulating material layer with a second opening on the surface of the obtained structure, wherein the second opening exposes the upper surface of the Josephson junction;
6) and forming a third superconducting material layer on the surface of the obtained structure, and etching the third superconducting material layer to form a wiring layer.
Optionally, step 6) is followed by:
7) forming a third insulating material layer on the surface of the structure obtained in the step 6), and patterning the third insulating material;
8) and forming a fourth superconducting material layer on the surface of the obtained structure, and etching the fourth superconducting material layer to form a grounding layer.
Optionally, the shunt resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.
Based on the above preparation method, the present invention also provides a superconducting circuit having a large inductance layer, the superconducting circuit including:
a substrate;
a shunt resistor and a large inductance layer formed on the substrate;
a Josephson junction formed on the shunt resistance and the bulk inductance layer;
a wiring layer formed on the Josephson junction;
an insulating material layer electrically isolating the shunt resistor, the Josephson junction, the large inductance layer, and the wiring layer, respectively.
Optionally, the method further comprises: a ground layer formed on the wiring layer, the insulating layer also electrically isolating the ground layer.
Optionally, the shunt resistor is a Mo layer, or a stack of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.
As described above, the superconducting circuit with a large inductance layer and the method for manufacturing the same according to the present invention utilize the design of the medium and small inductances on the original wiring layer, and then design and add a special large inductance layer to be applied to the superconducting circuit requiring the large inductance, thereby effectively expanding the size range of the inductance in the superconducting circuit, widening the application scenarios of the superconducting circuit, and improving the integration level of the superconducting circuit; in addition, the large inductance layer made of a specific material can also be used as a large resistance layer at the same time, so that the integration degree of the superconducting circuit can be further improved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a superconducting circuit with a large inductance layer according to a first embodiment of the present invention.
Fig. 2 to 15 are schematic cross-sectional views of the steps in the method for manufacturing a superconducting circuit with a large inductance layer according to the first embodiment of the present invention.
Fig. 16 is a schematic cross-sectional view showing the structure of step S1 in the method for manufacturing a superconducting circuit having a large inductance layer according to the second embodiment of the present invention.
Description of the element reference numerals
100 substrate
101 shunt resistor
102 first layer of insulating material
103 first opening
104 first layer of superconducting material
105 layer of barrier material
106 second layer of superconducting material
107 upper electrode
108 barrier layer
109 lower electrode
110 second layer of insulating material
111 large inductance layer
112 second opening hole
113 a third layer of insulating material
114 third layer of superconducting material
115 wiring layer
116 fourth insulating material layer
117 fourth layer of superconducting material
118 ground plane
119 third opening
S1-S7
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 16. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed according to actual needs, and the layout of the components may be more complicated.
Example one
As shown in fig. 1, the present embodiment provides a method for manufacturing a superconducting circuit having a large inductance layer, the method comprising the steps of:
s1, providing a substrate and forming a shunt resistor on the substrate;
s2, forming a patterned first insulating material layer having a first opening on the surface of the obtained structure, wherein the first opening exposes the shunt resistor;
s3, sequentially forming a three-layer film structure of a first superconducting material layer, a barrier material layer and a second superconducting material layer on the surface of the obtained structure;
s4, etching the three-layer thin film structure with different patterns from top to bottom to form a Josephson junction;
s5, forming an imaged second insulating material layer on the surface of the obtained structure, and forming a large inductance layer on the second insulating material layer;
s6, forming a patterned third insulating material layer having a plurality of second openings on the surface of the obtained structure, wherein the second openings expose the large inductance layer and the upper surface of the josephson junction;
and S7, forming a third superconducting material layer on the surface of the obtained structure, and etching the third superconducting material layer to form a wiring layer.
The method for manufacturing the superconducting circuit having the large inductance layer according to this embodiment will be described in detail with reference to the drawings.
As shown in S1 of fig. 1 and fig. 2, step S1 is performed to provide a substrate 100, and a shunt resistor 101 is formed on the substrate 100.
The substrate 100 may include at least one of a silicon substrate, a silicon oxide substrate, a magnesium oxide substrate, a sapphire substrate, and a silicon carbide substrate, but is not limited thereto, and any substrate suitable for preparing a superconducting circuit may be used.
As an example, a specific method of forming the shunt resistor 101 includes: forming a layer of shunt resistance material on the substrate 100; and then, carrying out photoetching-etching on the bypass resistance material layer to realize patterning on the bypass resistance material layer, so as to obtain the bypass resistor 101. The bypass resistor 101 can be selected as a single Mo layer; the structure of the multilayer structure can also be a Pd layer and a Ti layer, wherein the Ti layer serves as an adhesion layer, the Pd layer serves as a main resistance material layer, the Ti layer can achieve good adhesion between the substrate and the Pd layer, the thickness of the Ti layer is generally thinner between about 6nm and 20nm, and the thickness of the Pd layer is set according to the requirement of specific resistance, and is generally between 20nm and 100 nm.
As shown in S2 of fig. 1 and fig. 3, step S2 is performed to form a patterned first insulating material layer 102 having a first opening 103 on the surface of the obtained structure, wherein the first opening 103 exposes the shunt resistor 101. The shape and layout of the bypass resistor 101 can be designed according to actual requirements
As a specific example method: forming the first insulating material layer 102 by the above-obtained structure surface PECVD process; then, the first insulating material layer 102 is patterned by photolithography-etching, and the first opening 103 is formed.
The material of the first insulating material layer 102 includes SiO2Or SiNx, but is not limited thereto, and other materials with better insulating property may be used.
As shown in S3 in fig. 1 and fig. 4, step S3 is performed to form a three-layer thin film structure of the first superconducting material layer 104, the barrier material layer 105, and the second superconducting material layer 106 on the surface of the obtained structure in this order.
Specifically, the first superconducting material layer 104 includes at least one of a niobium nitride layer and a niobium layer, that is, may be one of them, or may be a stacked structure of two kinds of layers; the second superconducting material layer 106 includes at least one of a niobium nitride layer and a niobium layer, that is, may be one of them, or may have a stacked structure of two kinds of layers; the barrier material layer 105 is an aluminum-containing material layer including at least one of an aluminum layer, an aluminum oxide layer, and an aluminum nitride layer, and may have one of them, or may have a stacked structure of two or more kinds. In this embodiment, the first superconducting material layer 104 is an Nb layer; the second superconducting material layer 106 is an Nb layer; the barrier material layer 105 is an Al-AlOx layer.
As shown in S4 of fig. 1 and fig. 5, step S4 is performed to etch the three-layer thin film structure with different patterns from top to bottom to form josephson junctions. The method specifically comprises the following steps: firstly, photoetching and etching the second superconducting material layer 106 to obtain an upper electrode layer 107; then, photoetching and etching are carried out on the barrier material layer 105, so as to obtain a barrier layer 108; and finally, photoetching and etching the first superconducting material layer 104 to obtain a lower electrode layer 109, wherein the lower electrode layer 109 is electrically connected with the bypass resistor 101. The josephson junction is formed by the upper electrode layer 107, the barrier layer 108 and the lower electrode layer 109. The shapes and layouts of the upper electrode layer 107, the barrier layer 108, and the lower electrode layer 109 are designed according to actual needs.
As shown in S5 of fig. 1 and fig. 6 to 9, step S5 is performed to form a patterned second insulating material layer 110 on the surface of the structure obtained above, and form a large inductance layer 111 on the second insulating material layer 110. The shape and layout of the large inductance layer are designed according to actual needs.
As shown in fig. 6, after the second insulating material layer 110 is formed, the second insulating material layer 110 may not be etched first to form an opening exposing the upper surface of the josephson junction; as shown in fig. 9, a large inductance layer 111 is then formed on the second insulating material layer 110. In this way, after the third insulating material layer 113 is formed subsequently, the second insulating material layer 110 and the third insulating material layer 113 are etched together to form an opening exposing the upper surface of the josephson junction, as shown in fig. 10.
As shown in fig. 7, after the second insulating material layer 110 is formed, the second insulating material layer 110 may also be etched to form a third opening 119 exposing the upper surface of the josephson junction; as shown in fig. 8, a large inductance layer 111 is then formed on the second insulating material layer 110. In this way, after the third insulating material layer 113 is formed subsequently, only the third insulating material layer 113 is etched to form an opening exposing the upper surface of the josephson junction, as shown in fig. 10.
As an example, the material of the second insulating material layer 110 includes SiO2Or SiNx, but is not limited thereto, and other materials with better insulating property may be used.
As an example, the material of the large inductance layer 111 is NbN or MoN. If the material of the large inductance layer 111 is selected to be MoN, the large inductance layer 111 can also be used as a large resistance layer at the same time, so that the integration degree of the superconducting circuit can be further improved.
As shown in S6 of fig. 1 and fig. 10, step S6 is performed to form a patterned third insulating material layer 113 having a plurality of second openings 112 on the surface of the structure, wherein the second openings 112 expose the large inductance layer 111 and the upper surface of the josephson junction, respectively.
As an example, the material of the third insulating material layer 113 includes SiO2Or SiNx, but is not limited thereto, and other materials with better insulating property may be used.
As shown in S7 in fig. 1 and fig. 11 and 12, step S7 is finally performed to form a third superconducting material layer 114 on the surface of the structure obtained as described above, and the third superconducting material layer 114 is etched to form a wiring layer 115, so that a corresponding electrical signal is extracted. The material of the wiring layer 115 may be at least one of niobium nitride and niobium, and in this embodiment, the material of the wiring layer 115 is selected to be niobium.
In addition, in some scenarios, the superconducting circuit needs to be grounded to shield external noise, and at this time, a ground layer needs to be formed in the superconducting circuit, and the specific preparation method includes: as shown in fig. 13, a fourth insulating material layer 116 is formed on the surface of the structure obtained above, and the fourth insulating material layer 116 is patterned, wherein the material of the fourth insulating material layer 116 includes SiO2Or SiNx, but not limited thereto, other materials with better insulating property may also be used; as shown in fig. 14, a fourth superconducting material layer 117 is then formed on the surface of the structure obtained above, as shown in fig. 15, and the fourth superconducting material layer 117 is etched to form a ground layer 118, so as to extract the corresponding electrical signal.
It should be noted that the insulating material layers used in the method for manufacturing a superconducting circuit according to this embodiment, for example, the materials of the first insulating material layer 102, the second insulating material layer 110, the third insulating material layer 113, and the fourth insulating material layer 116, may be kept consistent, so as to realize an insulating material layer with homogeneous growth, and no obvious interface exists during homogeneous growth, and no influence is exerted on the subsequent processes.
Based on the above manufacturing method of the superconducting circuit, as shown in fig. 12 and referring to fig. 1 to 11, the present embodiment also provides a superconducting circuit having a large inductance layer, the superconducting circuit including:
a substrate 100; a shunt resistor 101 formed on the substrate 100; a josephson junction formed on the shunt resistor 101, the josephson junction consisting of the upper electrode layer 107, the barrier layer 108 and the lower electrode layer 109; a large inductance layer 111 formed on the josephson junction; a wiring layer 115 formed on the large inductance layer 111; insulating material layers electrically isolating the shunt resistor 101, the josephson junction, the large inductance layer 111, and the wiring layer 115, respectively, the insulating material layers including the first insulating material layer 102, the second insulating material layer 110, and the third insulating material layer 113.
As shown in fig. 15 and referring to fig. 13 to 14, the superconducting circuit further includes, as an example, a ground layer 118 formed on the wiring layer 115, the insulating layer also electrically isolating the ground layer 118, i.e., the insulating material layer further includes the fourth insulating material layer 116.
As an example, the shunt resistor 101 is a stack of a Mo layer or a Pd layer and a Ti layer; the material of the large inductance layer 111 is NbN or MoN, and if the material of the large inductance layer 111 is MoN, the large inductance layer 111 can also be used as a large resistance layer, so that the integration level of the superconducting circuit can be further improved.
Based on the preparation method of the superconducting circuit and the superconducting circuit, a special large inductance layer is designed and added in the design of the medium and small inductances of the original wiring layer to be applied to the superconducting circuit needing the large inductance, so that the size range of the inductance in the superconducting circuit is effectively expanded, the application scene of the superconducting circuit is widened, and the integration level of the superconducting circuit is improved; in addition, the large inductance layer made of a specific material can also be used as a large resistance layer at the same time, so that the integration degree of the superconducting circuit can be further improved.
Example two
This example provides another method for manufacturing a superconducting circuit having a large inductance layer, which is substantially the same as the superconducting circuit of example one except that: as shown in fig. 16, after providing a substrate 100, the large inductance layer 111 is prepared at the same time as the shunt resistor 101 is prepared on the substrate 100, that is, the large inductance layer 111 formed by the preparation method of this embodiment is formed on the substrate. The preparation method specifically comprises the following steps:
s1, providing a substrate, and respectively forming a shunt resistor and a large inductance layer on the substrate;
s2, forming a first insulating material layer having a plurality of first openings on the surface of the obtained structure, wherein the first openings expose the shunt resistor and the large inductance layer respectively;
s3, sequentially forming a three-layer film structure of a first superconducting material layer, a barrier material layer and a second superconducting material layer on the surface of the obtained structure;
s4, etching the three-layer thin film structure with different patterns from top to bottom to form a Josephson junction;
s5, forming a second insulating material layer having a second opening on the surface of the structure, the second opening exposing the upper surface of the josephson junction;
and S6, forming a third superconducting material layer on the surface of the obtained structure, and etching the third superconducting material layer to form a wiring layer.
As an example, in some scenarios, a superconducting circuit needs to be grounded to shield external noise, and at this time, a ground layer needs to be formed in the superconducting circuit, and the specific preparation method is as follows: firstly, forming a third insulating material layer on the surface of the obtained structure, and patterning the third insulating material; and then forming a fourth superconducting material layer on the surface of the obtained structure, and etching the fourth superconducting material layer to form a grounding layer.
As an example, the shunt resistance is a stack of a Mo layer or a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN, and if the material of the large inductance layer is MoN, the large inductance layer can also be used as a large resistance layer, so that the integration level of the superconducting circuit can be further improved.
Based on the manufacturing method, the present embodiment also provides a superconducting circuit having a large inductance layer, the superconducting circuit including:
a substrate; a shunt resistor and a large inductance layer formed on the substrate; a Josephson junction formed on the shunt resistance and the bulk inductance layer; a wiring layer formed on the Josephson junction; an insulating material layer electrically isolating the shunt resistor, the Josephson junction, the large inductance layer, and the wiring layer, respectively.
As an example, the superconducting circuit further includes a ground layer formed on the wiring layer, and the insulating material layer further electrically isolates the ground layer, i.e., the insulating material layer further includes the third insulating material layer.
As an example, the shunt resistance is a stack of a Mo layer or a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN, and if the material of the large inductance layer is MoN, the large inductance layer can also be used as a large resistance layer, so that the integration level of the superconducting circuit can be further improved.
Based on the preparation method of the superconducting circuit and the superconducting circuit, a special large inductance layer is designed and added in the design of the medium and small inductances of the original wiring layer to be applied to the superconducting circuit needing the large inductance, so that the size range of the inductance in the superconducting circuit is effectively expanded, the application scene of the superconducting circuit is widened, and the integration level of the superconducting circuit is improved; in addition, the large inductance layer made of a specific material can also be used as a large resistance layer at the same time, so that the integration degree of the superconducting circuit can be further improved.
In summary, the invention provides a superconducting circuit with a large inductance layer and a preparation method thereof, which utilizes the design of the medium and small inductances on the original wiring layer, and then designs and adds a special large inductance layer to be applied to the superconducting circuit needing the large inductance, thereby effectively expanding the size range of the inductance in the superconducting circuit, widening the application scene of the superconducting circuit and improving the integration level of the superconducting circuit; in addition, the large inductance layer made of a specific material can also be used as a large resistance layer at the same time, so that the integration degree of the superconducting circuit can be further improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (13)

1. A method for manufacturing a superconducting circuit having a large inductance layer, comprising:
1) providing a substrate, and forming a bypass resistor on the substrate;
2) forming a patterned first insulating material layer with a first opening on the surface of the obtained structure, wherein the bypass resistor is exposed from the first opening;
3) sequentially forming a three-layer film structure of a first superconducting material layer, a barrier material layer and a second superconducting material layer on the surface of the obtained structure;
4) etching the three-layer thin film structure with different patterns from top to bottom to form a Josephson junction;
5) forming a second patterned insulating material layer on the surface of the obtained structure, and forming a large inductance layer on the second insulating material layer;
6) forming a patterned third insulating material layer with a plurality of second openings on the surface of the obtained structure, wherein the second openings respectively expose the large inductance layer and the upper surface of the Josephson junction;
7) and forming a third superconducting material layer on the surface of the obtained structure, and etching the third superconducting material layer to form a wiring layer.
2. The method for preparing a superconducting circuit with a large inductance layer according to claim 1, further comprising after step 7):
8) forming a fourth insulating material layer on the surface of the structure obtained in the step 7), and patterning the fourth insulating material layer;
9) and forming a fourth superconducting material layer on the surface of the obtained structure, and etching the fourth superconducting material layer to form a grounding layer.
3. The method for preparing a superconducting circuit with a large inductance layer according to claim 1, wherein the step 5) further comprises: etching the second insulating material layer to form a third opening exposing an upper surface of the Josephson junction.
4. The method for manufacturing a superconducting circuit having a large inductance layer according to claim 1, wherein: the bypass resistor is a Mo layer or a lamination of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.
5. A method for manufacturing a superconducting circuit having a large inductance layer, comprising:
1) providing a substrate, and respectively forming a bypass resistor and a large inductance layer on the substrate;
2) forming a first insulating material layer with a plurality of first openings on the surface of the obtained structure, wherein the bypass resistor and the large inductance layer are respectively exposed from the plurality of first openings;
3) sequentially forming a three-layer film structure of a first superconducting material layer, a barrier material layer and a second superconducting material layer on the surface of the obtained structure;
4) etching the three-layer thin film structure with different patterns from top to bottom to form a Josephson junction;
5) forming a second insulating material layer with a second opening on the surface of the obtained structure, wherein the second opening exposes the upper surface of the Josephson junction;
6) and forming a third superconducting material layer on the surface of the obtained structure, and etching the third superconducting material layer to form a wiring layer.
6. The method for preparing a superconducting circuit with a large inductance layer according to claim 5, further comprising after step 6):
7) forming a third insulating material layer on the surface of the structure obtained in the step 6), and patterning the third insulating material;
8) and forming a fourth superconducting material layer on the surface of the obtained structure, and etching the fourth superconducting material layer to form a grounding layer.
7. The method for manufacturing a superconducting circuit having a large inductance layer according to claim 5, wherein: the bypass resistor is a Mo layer or a lamination of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.
8. A superconducting circuit having a large inductance layer, comprising:
a substrate;
a shunt resistor formed on the substrate;
a Josephson junction formed on the shunt resistor;
a large inductance layer formed on the Josephson junction;
a wiring layer formed on the large inductance layer;
an insulating material layer electrically isolating the shunt resistor, the Josephson junction, the large inductance layer, and the wiring layer, respectively.
9. The superconducting circuit with a large inductance layer according to claim 8, further comprising: a ground layer formed on the wiring layer, the insulating layer also electrically isolating the ground layer.
10. The superconducting circuit with a large inductance layer according to claim 8, wherein: the bypass resistor is a Mo layer or a lamination of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.
11. A superconducting circuit having a large inductance layer, comprising:
a substrate;
a shunt resistor and a large inductance layer formed on the substrate;
a Josephson junction formed on the shunt resistance and the bulk inductance layer;
a wiring layer formed on the Josephson junction;
an insulating material layer electrically isolating the shunt resistor, the Josephson junction, the large inductance layer, and the wiring layer, respectively.
12. The superconducting circuit with a large inductance layer according to claim 11, further comprising: a ground layer formed on the wiring layer, the insulating layer also electrically isolating the ground layer.
13. The superconducting circuit with a large inductance layer as claimed in claim 11, wherein: the bypass resistor is a Mo layer or a lamination of a Pd layer and a Ti layer; the material of the large inductance layer is NbN or MoN.
CN202111492420.2A 2021-12-08 2021-12-08 Superconducting circuit with large inductance layer and preparation method thereof Pending CN114188472A (en)

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