CN114173274A

CN114173274A - Audio processing chip, multi-channel system and audio processing method

Info

Publication number: CN114173274A
Application number: CN202010947870.5A
Authority: CN
Inventors: 陈昶志; 庄宗朋
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-09-10
Filing date: 2020-09-10
Publication date: 2022-03-11

Abstract

The audio processing chip comprises a detection circuit, a first-in first-out circuit and an adjusting circuit system. The detection circuit is used for detecting the audio streaming to output an enabling signal. The FIFO circuit is used for outputting audio data corresponding to the channel in the audio stream as a first signal according to the enable signal. The adjusting circuit system is used for processing the first signal to generate an output signal to the loudspeaker.

Description

Audio processing chip, multi-channel system and audio processing method

Technical Field

The present invention relates to an audio processing chip, and more particularly, to an audio processing chip, a multi-channel system and an audio processing chip using detection of audio streams for synchronization with a timing sequence.

Background

Therefore, the multi-channel system can superpose the audio output from several speakers to generate surround sound (surround sound). In some techniques, multiple speakers are each driven by a different amplifier circuit. If the amplifier circuits start processing audio data at different timings, there may be a phase difference between sounds output by the speakers. Thus, the superimposed sound effect is not good, and the user experience is reduced.

Disclosure of Invention

In some embodiments, the audio processing chip includes a detection circuit, a first-in first-out circuit, and an adjustment circuitry. The detection circuit is used for detecting the audio streaming to output an enabling signal. The FIFO circuit is used for outputting audio data corresponding to the channel in the audio stream as a first signal according to the enable signal. The adjusting circuit system is used for processing the first signal to generate an output signal to the loudspeaker.

In some embodiments, a multi-channel system includes a first audio processing chip and a second audio processing chip. The first audio processing chip is used for processing first audio data in the audio streaming to generate a first output signal. The second audio processing chip is used for processing second audio data in the audio streaming to generate a second output signal, wherein each of the first audio processing chip and the second audio processing chip comprises a detection circuit, a first-in first-out circuit and an adjustment circuit system. The detection circuit is used for detecting the audio streaming to output an enabling signal. The FIFO circuit is used for outputting one of the first audio data and the second audio data as a first signal according to the enable signal. The adjusting circuit system is used for processing the first signal to generate a first output signal corresponding to the first audio data or a second output signal corresponding to the second audio data.

In some embodiments, the audio processing method comprises the following operations: detecting an audio stream to output an enable signal; outputting audio data in the audio series flow as a first signal by a first-in first-out circuit according to an enabling signal; and processing the first signal to generate an output signal to the speaker.

The features, implementations and effects of the present invention will be described in detail below with reference to the preferred embodiments of the fermented bean curd.

Drawings

FIG. 1A is a schematic diagram depicting a multi-channel system according to some embodiments of the present invention;

FIG. 1B is a flow chart depicting various operations of the multi-channel system of FIG. 1A, in accordance with some embodiments of the present invention;

FIG. 2A is a schematic diagram depicting a multi-channel system according to some embodiments of the present invention;

FIG. 2B is a flow chart depicting various operations of the multi-channel system of FIG. 2A, in accordance with some embodiments of the present invention; and

fig. 3 is a flow chart depicting an audio processing method according to some embodiments of the present invention.

Description of the symbols:

100. 200: multi-channel system

110. 120: audio processing chip

111. 121: multiplexer circuit

112. 122: digital audio detector circuit

113. 123: first-in first-out (FIFO) circuit

114. 124: adjusting circuit system

114A, 124A: digital signal processor circuit

114B, 124B: filter circuit

114C, 124C: digital-to-analog converter (DAC) circuit

114D, 124D: amplifier circuit

AS: audio streaming

CK: bit frequency signal

EN, EN': enabling signal

S1-S4, S1 '-S4': signal

SEL1, SEL 2: setting signal

SL, SR: audio data

SO1, SO 2: output signal

SPL, SPR: loudspeaker

CS: synchronizing instructions

CT1, CT 2: count value

SV: validation signal

S151 to S153, S251 to S255, S310, S320, S330: operation of

300: audio processing method

Detailed Description

The embodiments are described in detail below with reference to the drawings, but the embodiments are only used for explaining the invention and not for limiting the application, the description of the structural operation is not used for limiting the execution sequence, and any structure with equivalent functions produced by the recombination of components falls within the scope of the present application.

All words used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the word examples discussed herein in the context of this invention are exemplary only and should not be construed as limiting the scope and meaning of the invention. Similarly, the present invention is not limited to the various embodiments shown in this specification.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to the mutual operation or action of two or more elements. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuitry" may be a device connected by at least one transistor and/or at least one active and passive component in a manner to process a signal.

As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like are used herein to describe and distinguish between various components. Thus, a first component may also be referred to herein as a second component without departing from the spirit of the invention. For ease of understanding, similar components in the various figures will be designated with the same reference numerals.

FIG. 1A is a schematic diagram depicting a multi-channel system 100 according to some embodiments of the present invention. The multi-channel system 100 includes a host (host) device 100A, an audio processing chip 110, an audio processing chip 120, a speaker SPL, and a speaker SPR. The host device 100A may provide an audio stream AS. In some embodiments, the host device 100A can be, but is not limited to, a music player, a computer, a mobile device, or a carry-on player.

In some embodiments, the audio stream AS includes a bit frequency (bit clock) signal CK, audio data SL corresponding to the left channel, and audio data SR corresponding to the right channel. The audio processing chip 110 is used for processing the audio data SL corresponding to the left channel to generate an output signal SO1 to the speaker SPL. The audio processing chip 120 is configured to process the audio data SR corresponding to the right channel to generate an output signal SO2 to the speaker SPR. The speakers SPL and SPR may convert the output signals SO1 and SO2 into corresponding sounds, respectively.

The audio processing chip 110 includes a multiplexer circuit 111, a detection circuit 112, a first-in-first-out (FIFO) circuit 113 (hereinafter, referred to as FIFO circuit), and an adjustment circuit 114. The multiplexer circuit 111 outputs the audio data SL corresponding to the left channel (labeled L) in the audio stream AS to the FIFO circuit 113 according to the setting signal SEL1 from the host device 100A. The detection circuit 112 is configured to detect the audio stream AS to output the enable signal EN. In these embodiments, the detecting circuit 112 may be a digital audio detector circuit, which can be used to detect a non-zero data value in the audio stream AS to generate the enabling signal EN. Operations related thereto will be described below with reference to fig. 1B. In some embodiments, the digital audio detector circuit may be implemented by a plurality of logic circuits and/or Digital Signal Processor (DSP) circuits. The FIFO circuit 113 operates as a data buffer between the host device 100A and the adjustment circuitry 114. The FIFO circuit 113 is activated to start outputting the audio data SL as the signal S1 according to the enable signal EN, and transmits the signal S1 to the adjusting circuit 114. The adjusting circuit 114 processes the signal S1 to generate an output signal SO 1.

In some embodiments, the adjustment circuitry 114 includes a digital signal processor circuit (hereinafter referred to as DSP circuit) 114A, a filter circuit 114B, a digital-to-analog converter (DAC) circuit (hereinafter referred to as DAC circuit) 114C, and an amplifier circuit 114D. The DSP circuit 114A is used to adjust the volume and sound effect of the signal S1 to generate a signal S2. The filter circuit 114B is used for filtering the signal S2 to reduce noise on the signal S2 and generate the signal S3. The DAC circuit 114C is used to convert the digital signal S3 into an analog signal S4. The amplifier circuit 114D amplifies the signal S4 to generate the output signal SO 1. The above embodiments of the adjustment circuitry 114 are provided for illustration and the invention is not limited thereto.

In some embodiments, the audio processing chip 120 includes a multiplexer circuit 121, a detection circuit 122, a FIFO circuit 123, and an adjustment circuit 124. The multiplexer circuit 121 outputs the audio data SR corresponding to the right channel (labeled R) in the audio stream AS to the FIFO circuit 123 according to the setting signal SEL2 from the host device 100A. Similar to the detection circuit 121, the detection circuit 122 can be a digital audio detector circuit, which can detect a non-zero data value in the audio stream AS to generate the enable signal EN'. The FIFO circuit 123 is activated according to the enable signal EN ' to start outputting the audio data SR as the signal S1', and transmits the signal S1' to the adjusting circuitry 124. Similar to the adjustment circuitry 114, the adjustment circuitry 124 includes a DSP circuit 124A, a filter circuit 124B, DAC circuit 124C, and an amplifier circuit 124D. The DSP circuit 124A may adjust the volume and sound effect of the signal S1 'to generate the signal S2'. The filter circuit 124B filters the signal S2' to reduce noise on the signal S2' and generate the signal S3 '. The DAC circuit 124C converts the signal S3 'in digital form into a signal S4' in analog form. The amplifier circuit 124D amplifies the signal S4' to generate the output signal SO 2.

In some embodiments, the host device 100A further exchanges control signals (e.g., the setting signal SEL1 and the setting signal SEL2) and/or clock signals to the audio processing chip 110 and the audio processing chip 120 through a transmission interface (not shown). The audio processing chip 110 and the audio processing chip 120 can configure the plurality of circuits through the control signals and/or the frequency signals. In some embodiments, the aforementioned transmission interface may be, but is not limited to, an inter-integrated circuit (I2C) bus.

FIG. 1B is a flow chart depicting various operations of the multi-channel system 100 of FIG. 1A, in accordance with some embodiments of the present invention. In some embodiments, operation S151 is performed by the host device 100A shown in fig. 1A, and operations S152 to S153 are performed by the audio processing chip 110 and the audio processing chip 120 shown in fig. 1A.

In operation S151, a host device (e.g., host device 100A) sends an audio stream. In operation S152, the detection circuit (e.g., the detection circuit 112, the detection circuit 122) confirms whether a non-zero data value occurs in the audio stream. If a non-zero data value occurs in the audio stream, operation S153 is performed. Alternatively, if the audio stream does not have a non-zero data value, operation S152 is performed again. In operation S153, an enable signal is output to cause the FIFO circuits (e.g., FIFO circuit 113, FIFO circuit 123) to start outputting audio data.

For example, the audio data included in the audio stream AS is digital data encoded by pulse-code modulation (pcm). As previously mentioned, in this example, the detection circuit 112 is a digital audio detector circuit. The detection circuit 112 may analyze whether a non-zero data value is present in the digital data. In some embodiments, when the audio data in the audio stream AS has a non-zero data value, it represents that the host device 100A has started to transmit the audio to be played. Therefore, in response to the non-zero data value in the audio stream AS, the detection circuit 112 may output the enable signal EN to control the FIFO circuit 113 to start outputting the audio data SL. Similarly, the detection circuit 122 can output an enable signal EN' to control the FIFO circuit 123 to start outputting the audio data SR. With this detection mechanism, the audio processing chip 110 and the audio processing chip 120 can synchronously process the audio data to generate the output signal SO1 and the output signal SO 2. As a result, the phase difference between the output signal SO1 and the output signal SO2 can be reduced, SO as to improve the sound effect of the multi-channel system 100.

In some embodiments, the detection circuit 112 (and/or the detection circuit 122) can record two consecutive audio data in the audio stream AS and determine whether the Least Significant Bit (LSB) of the two audio data is toggled. If the least significant bit of the two audio data is effectively switched, it represents that a non-zero data value appears in the audio stream AS. Otherwise, if the least significant bit is not toggled, it means that no non-zero data value is present in the audio stream AS. The above-mentioned detection method for non-zero data value is used for example, and the invention is not limited thereto.

Fig. 2A is a schematic diagram depicting a multi-channel system 200 according to some embodiments of the invention. Compared to fig. 1A, each of the detection circuit 112 and the detection circuit 122 in fig. 2A is a counter circuit. In this example, the host device 100A is provided with a broadcast (broadcast) function, which can send a synchronization command CS to the audio processing chip 110 and the audio processing chip 120. In response to the synchronous command CS, the detecting circuit 112 detects the frequency signal CK of the audio stream AS and counts at least one pulse of the frequency signal CK to generate a count value CT 1. Similarly, in response to the synchronization command CS, the detection circuit 122 detects the frequency signal CK of the audio stream AS and counts at least one pulse of the frequency signal CK to generate the count value CT 2. The detection circuit 112 and the detection circuit 122 respectively return the count value CT1 and the count value CT2 to the host device 100A, and the host device 100A can determine whether to issue the valid signal SV according to the count value CT1 and the count value CT 2. In this case, the detecting circuit 112 and the detecting circuit 122 are configured to output the enable signal EN and the enable signal EN' according to the asserted signal SV, respectively, so that the FIFO circuit 113 and the FIFO circuit 123 start outputting the audio data SL and the audio data SR, respectively. Operations related thereto will be described below with reference to fig. 2B.

In this example, each of the detection circuit 112 and the detection circuit 122 detects a frequency signal in the audio stream AS instead of audio data. Therefore, the operations of the detection circuit 112 and the detection circuit 122 may not be limited by the timing of receiving the frequency signal or the audio data. In some embodiments, as shown in FIG. 2A, detection circuit 112 is independent of FIFO circuit 113, and detection circuit 122 is independent of FIFO circuit 123. In other embodiments, the detection circuit 112 and the FIFO circuit 113 may be integrated into a single circuit, and the detection circuit 122 and the FIFO circuit 123 may be integrated into a single circuit.

Fig. 2B is a flow chart depicting various operations of the multi-channel system 200 of fig. 2A, in accordance with some embodiments of the present invention. In some embodiments, operations S251, S253, and S254 are performed by the host device 100A shown in fig. 2A, and operations S252 and S255 are performed by the audio processing chip 110 and the audio processing chip 120 shown in fig. 2A.

In operation S251, a host device (e.g., the host device 100A) sends a synchronization command with an audio stream. In operation S252, the detection circuit (e.g., the detection circuit 112, the detection circuit 122) counts at least one pulse of the frequency signal in the audio stream for a predetermined period in response to the synchronization command to generate a count value. In operation S253, the host device confirms whether all count values are the same. If all the count values are the same, operation S254 is performed. On the contrary, if one of the count values is different from the other count values, the host device re-executes operation S251 to re-send the synchronization command, so that the plurality of detection circuits re-count the at least one pulse to update the count value. In operation S254, the host device outputs a validation signal. In operation S255, the detection circuit outputs an enable signal in response to the validate signal to cause the FIFO circuit (e.g., FIFO circuit 113, FIFO circuit 123) to start outputting the audio data.

For example, the frequency signal included in the audio stream AS may be the bit frequency signal CK. The host device 100A may issue a synchronization command CS. In response to the synchronization command CS, the detection circuit 112 and the detection circuit 122 can count at least one pulse of the bit clock signal CK. If the detection circuit 112 and the detection circuit 122 start counting at the same time in response to the synchronous command CS, the count value CT1 generated by the detection circuit 112 during the predetermined period is the same as the count value CT2 generated by the detection circuit 122 during the predetermined period. Therefore, if the count value CT1 is the same as the count value CT2, it means that the bit clock signal CK received by the audio processing chip 110 and the audio processing chip 120 have the same phase. In this condition, host device 100A may output validate signal SV. The

detection circuits

112 and 122 can output the enable signal EN and the enable signal EN' in response to the asserted signal SV respectively, so that the

FIFO circuits

113 and 123 start outputting the audio data SL and SR.

Alternatively, if the count value CT1 is different from the count value CT2, it indicates that the bit clock signal CK received by the audio processing chip 110 and the audio processing chip 120 have different phases. In this condition, the host device 100A may resend the synchronization instruction CS. In response to the synchronization command CS, the

detection circuits

112 and 113 re-count the bit clock signal CK to update the count values CT1 and CT 2. If the updated count value CT1 is the same as the updated count value CT2, the host device 100A outputs the validate signal SV. With this detection mechanism, the audio processing chip 110 and the audio processing chip 120 can synchronously process the audio data to generate the output signal SO1 and the output signal SO 2. As a result, the phase difference between the output signal SO1 and the output signal SO2 can be reduced, SO as to improve the sound effect of the multi-channel system 200.

In the above examples, the number of channels, audio processing chips and speakers is only an example, and the invention is not limited thereto. The number of the sound channels, the audio processing chip and the loudspeakers can be adjusted according to actual application. For example, the multi-channel system 100 (or the multi-channel system 200) may be applied not only to the left and right channels but also to the bass channel, the treble channel, and the like.

Fig. 3 is a flow chart depicting an audio processing method 300 according to some embodiments of the present invention. In some embodiments, the audio processing method 300 may be performed by, but is not limited to, the multi-channel system 100 or the multi-channel system 200 described above.

In operation S310, an audio stream is detected to output an enable signal. In operation S320, the FIFO circuit starts outputting the audio data in the audio stream as a first signal according to the enable signal. In operation S330, the first signal is processed to generate an output signal to a speaker.

For a plurality of operation descriptions of the audio processing method 300, reference may be made to the foregoing embodiments, and therefore, the description thereof is omitted here. The above operations are merely examples, and need not be performed in the order in this example. Various operations under the audio processing method 300 may be added, substituted, omitted, or performed in a different order, as appropriate, without departing from the manner of operation and scope of embodiments of the invention. Alternatively, one or more of the operations under the audio processing method 300 may be performed simultaneously or partially simultaneously.

In summary, in some embodiments of the invention, the audio processing chip, the multi-channel system and the audio processing method can utilize the detection of the audio stream sent by the host device for synchronization. Therefore, the phase difference between output signals generated by the audio chips can be reduced, so that the sound effect presented by the multi-channel system is improved, and the user experience is further improved.

Although the present disclosure has been described with reference to the specific embodiments, it should be understood that the present disclosure is not limited thereto, and that various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the present disclosure.

Claims

1. An audio processing chip, comprising:

a detection circuit for detecting the audio stream to output an enable signal;

the first-in first-out circuit is used for outputting audio data corresponding to a sound channel in the audio streaming as a first signal according to the enabling signal; and

and adjusting circuitry to process the first signal to generate an output signal to a speaker.

2. The audio processing chip of claim 1, wherein the detection circuit is configured to output the enable signal when a non-zero data value in the audio stream is detected.

3. The audio processing chip of claim 1, wherein the detection circuit is configured to detect a clock signal in the audio stream in response to a synchronization command issued by a host device, count at least one pulse of the clock signal to generate a first count value, and return the first count value to the host device, wherein the host device is further configured to determine whether to output a validation signal according to the first count value, and the detection circuit is further configured to generate the enable signal in response to the validation signal.

4. The audio processing chip of claim 3, wherein the host device is configured to output the validate signal when the first count value is the same as the second count values from the other chips.

5. The audio processing chip of claim 1, wherein the adjustment circuitry comprises:

a digital signal processor circuit for adjusting the volume and sound effect of the first signal to generate a second signal;

a filter circuit for filtering the second signal to generate a third signal;

a digital-to-analog converter circuit for converting the third signal to a fourth signal; and

an amplifier circuit to amplify the fourth signal to generate the output signal.

6. A multi-channel system, comprising:

the first audio processing chip is used for processing first audio data in the audio streaming to generate a first output signal; and

a second audio processing chip for processing second audio data in the audio stream to generate a second output signal, wherein each of the first and second audio processing chips comprises:

the detection circuit is used for detecting the audio streaming to output an enabling signal;

a first-in first-out circuit for outputting one of the first audio data and the second audio data as a first signal according to the enable signal; and

adjustment circuitry to process the first signal to generate the first output signal corresponding to the first audio data or the second output signal corresponding to the second audio data.

7. The multi-channel system of claim 6, wherein the detection circuit is configured to output the enable signal when a non-zero data value in the audio stream is detected.

8. The multi-channel system of claim 6, wherein the detection circuit is configured to detect a frequency signal in the audio stream in response to a synchronization command issued by a host device, count at least one pulse in the frequency signal to generate a count value and return the first count value to the host device, wherein the host device is further configured to output a validation signal when the count value returned by the first audio processing chip is the same as the count value returned by the second audio processing chip, and the detection circuit is further configured to generate the enable signal in response to the validation signal.

9. The multi-channel system of claim 8, wherein the host device outputs the synchronization command again if the count value returned by the first audio processing chip is different from the count value returned by the second audio processing chip, and the detection circuit is further configured to re-count the at least one pulse in the clock signal in response to the synchronization command to update the count value.

10. An audio processing method, comprising:

detecting an audio stream to output an enable signal;

outputting audio data in the audio streaming as a first signal by a first-in first-out circuit according to the enabling signal; and

the first signal is processed to produce an output signal to a speaker.