JP2012155233A - Information transmission device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce mute sections at the time of switching a sound source stream and efficiently transmit decoding information for an audio signal.SOLUTION: A sound decoding part 11 receives input of a sound stream, and executes decoding by a decoding method corresponding to the encoding method used to acquire a PCM signal which is a 24-bit digital audio signal and decoding information, for example. A bit rounding part 12 applies rounding for rounding off lower bits to the PCM signal in accordance with bit number information . A decoding information conversion part 13 applies conversion processing to the decoding information in accordance with the bit number information. A multiplexer 14 generates an IS-format signal including 24-bit audio data with the PCM signal after bit rounding representing a higher bit signal and the decode information after conversion by the decode information conversion part 13 representing a lower bit signal, and outputs the generated signal to a post-processing processor 20.

Description

  The present invention relates to an information transmission apparatus, and more particularly to an information transmission apparatus that transmits decode information obtained by decoding an encoded audio signal together with the decoded audio signal.

  In a conventional DVD (Digital Versatile Disc) player, an audio signal is encoded in a predetermined so-called DVD back end (for example, Dolby digital, dts (digital theater system), AAC (Advanced Audio Coding), etc. The encoded audio signal obtained by compression encoding is decoded into a pulse code modulation (PCM) signal.

In addition, in a DVD player, post processing such as virtual surround processing, headphone surround, and bass enhancement may be added in addition to the decoding processing of the encoded audio signal. In this case, the decoded PCM signal is sent to a DSP (Digital Signal Processor) arranged in a subsequent stage in a format called I ² S, and post processing is performed (for example, see Patent Document 1).

  Here, in the preceding decoding process, various audio information such as the sampling frequency, the decoder type, and the number of effective channels are decoded, but these decoding information is required when post-processing is performed by the succeeding DSP. For example, it is necessary to switch the post processing filter coefficient according to the sampling frequency. In addition, it is necessary to switch between cases where post processing is necessary and cases where it is unnecessary depending on the number of effective channels.

  In the conventional information transmission apparatus, the host processor transmits the decoding information of the previous stage to the post processing of the subsequent stage. For example, the host processor periodically acquires decode information from the preceding decoder, and monitors changes in the decode information due to switching of sound source streams. Examples of changes in the decoding information include the decoding type (for example, Dolby Digital / dts / AAC / mp3), the number of decoding channels and the number of channels actually output (for example, mono / 2ch / 5.1ch, etc.), decoding Channel configuration (speaker arrangement) and output channel configuration, decode sample frequency and output sample frequency, stream bit rate, etc.

  When the decode information changes, the host processor notifies the subsequent DSP of the decode information. The DSP performs post processing corresponding to the change of the decode information by the notification of the decode information (for example, when it is notified that the output sample frequency has changed, the filter coefficient is changed).

JP 2002-95100 A

  In the conventional information transmission apparatus described above, a time lag occurs before the decoding information is notified to the DSP due to the intervention of the host processor. For example, when the decoder information changes due to switching of the sound source stream, the decoded audio signal is immediately output to the subsequent DSP, but the subsequent DSP has not yet received the change of the decoding information at the time of output. The post processing before the decoding information notification is continued.

  Noise occurs at the moment when the decoding information changes due to this time lag. In order to suppress noise, an analog mute at the subsequent stage is used. However, if the time lag is long, the mute section at the time of switching the sound source stream becomes long, and the sound output after the change of the decoding information is interrupted.

  In addition, since the host processor needs to acquire the decode information regularly, the load on the host processor also increases. As necessary decoding information increases, a high-performance host processor is required.

  The present invention has been made in view of the above points, and an object of the present invention is to provide an information transmission apparatus capable of efficiently transmitting decoded information of an audio signal by reducing the mute interval when switching sound source streams.

  In order to achieve the above object, an information transmission apparatus according to the present invention decodes an encoded audio signal, separates a digital audio signal having a first number of bits, and decode information, and outputs the digital signal. Bit rounding processing means for truncating the signal of the second bit number on the lower side of the audio signal, decoding information converting means for converting the decoded information into decoded information after conversion of the second bit number, and bit rounding processing means The decoded decoding information of the second number of bits output from the decoding information converting means is synthesized on the lower bit side of the rounded digital audio signal output from the signal, and the decoded decoding information is embedded in the lower bits. A digital audio signal having the first number of bits is generated and output to a post processing processor for performing post processing. And having a means.

  In order to achieve the above object, the information transmission apparatus according to the present invention decodes an encoded audio signal in which audio signals of a plurality of channels including at least a front left and right channel and a rear channel are encoded, Decoding means for separating and outputting the digital audio signal of each channel of the number of bits and the decoding information, and a signal of the second bit number on the lower side of the digital audio signal of the rear channel among the digital audio signals of each channel Bit rounding processing means for truncating, decoding information converting means for converting decoded information into decoded information after conversion of the second number of bits, and a rounded digital audio signal of the rear channel output from the bit rounding processing means Is output from the decoding information conversion means to the lower bit side of Post-processing processor for combining post-conversion decoded information of the number of bits, generating a digital audio signal of the rear channel of the first bit number in which the converted decoding information is embedded in the lower bits, and performing post processing And a synthesizing means for outputting to the apparatus.

In order to achieve the above object, the information transmission apparatus of the present invention includes a decoding information conversion means,
Count means for generating a counter value whose value changes at a constant period, sync pattern generating means for generating a sync pattern having a predetermined second number of bits, and a sync pattern from the sync pattern generating means in accordance with the counter value And selecting the decoding information of the second number of bits of each decoding content according to the counter value from the decoding information including a plurality of decoding contents supplied from the decoding means, and outputting as the decoded decoding information after conversion Means.

  Furthermore, in order to achieve the above object, the information transmission apparatus of the present invention comprises a host processor that supplies bit number information specifying the second number of bits to the bit rounding processing means and the decode information conversion means. Features.

  According to the present invention, decoding information is embedded in the decoded digital audio data and output to the post-processing processor, so that the decoding information can be efficiently transmitted and the mute interval at the time of switching the sound source stream can be reduced. It becomes.

It is a block diagram of one embodiment of an information transmission device of the present invention. It is a timing chart for explaining a known I ² S format. It is operation | movement explanatory drawing of the bit rounding process part in FIG. It is a block diagram of an example of the decoding information conversion part in FIG. It is a figure which shows the transmission format of each example of decoding information. It is a figure which shows an example of the content of the decoding information which shows a counter value, the content of decoding information, and a value in the case of utilizing the lower 4 bits of an I ² S signal as decoding information. It is a block diagram of an example of the decoding information analysis part in FIG. It is a block diagram of other embodiment of the information transmission apparatus which becomes this invention. It is a diagram illustrating an example of channels allocation of I ² S signals in Fig.

  Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of an information transmission apparatus according to the present invention. In the figure, an information transmission apparatus 1 constitutes an audio signal reproduction apparatus, and a decoding processor 10 to which an audio stream is input and an I ² S signal obtained by decoding the audio stream by the decoding processor 10. A post-processing processor 20 that performs post-processing, a host processor 30 that supplies bit number information to the decoding processor 10 and the post-processing processor 20, and a post-processing digital audio signal output from the post-processing processor 20 as analog audio. It comprises a D / A converter 41 that converts the signal, an amplifier 42, and a speaker 43.

  The decoding processor 10 includes an audio decoding unit 11, a bit rounding processing unit 12, a decoding information conversion unit 13 and a multiplexer 14. The audio decoding unit 11 receives an audio stream in which digital audio data compression-encoded in a predetermined format such as Dolby Digital, dts, or AAC is synthesized in time series, and is a decoding method corresponding to the encoding method. Thus, a PCM signal, which is a 24-bit digital audio signal, and decode information are obtained.

  The bit rounding processing unit 12 performs a bit rounding process, which will be described later, on the 24-bit PCM signal supplied from the audio decoding unit 11 according to the bit number information specified by the host processor 30, and the PCM signal subjected to the bit rounding process Is supplied to the multiplexer 14 as an upper bit signal. On the other hand, the decode information conversion unit 13 performs conversion processing on the decode information supplied from the audio decoding unit 11 in accordance with the bit number information specified by the host processor 30, and sends the converted decode information to the multiplexer 14 in the lower bits. Supply as information.

The multiplexer 14 uses the PCM signal subjected to the bit rounding processing from the bit rounding processing unit 12 as an upper bit signal, and includes I-bit including 24-bit audio data having the decoded information from the decoding information conversion unit 13 as the lower bit signal. ^{A 2} S format signal (hereinafter referred to as an I ² S signal) is generated and output to the post processor 20.

Here, the I ² S format will be described with reference to the timing chart of FIG. The I ² S format is a known digital audio signal transmission format, and transmits data with reference to a word lock called LRCK shown in FIG. 2A and a bit clock called BCK shown in FIG. . Normally, two channels can be transmitted at the sampling frequency, and the left and right channels are discriminated based on the LRCK 'L' level or 'H' level. By setting BCK to a frequency 64 times that of LRCK, it is possible to transmit 32-bit data per channel. FIG. 2C shows 32-bit data SDATA (I ² S signal). A digital signal SDATA (I ² S signal) shown in FIG. 2C indicates a format when 24-bit audio data is transmitted MSB left justified. Depending on the connected device, transmission data may be shifted backward by 1 bit.

  As shown in FIG. 2C, even in the case of digitally 24-bit audio data, the performance of the analog circuit after the DA converter may be only about 16 bits. That is, in the case of 24-bit audio data, an SN ratio of 140 dB or more can be secured, but the SN ratio of an analog circuit in a general audio system is about 90 dB. Therefore, there is no practical problem even if several bits on the LSB side of 24-bit audio data are used for information transmission. In an inexpensive system, for example, even if the lower 4 bits of 24-bit audio data are allocated for decoding information transmission, there is no significant problem in sound quality.

  Therefore, in the present embodiment, the bit rounding processing unit 12 truncates the lower bits of the number of bits indicated by the bit number information from the host processor 30 in the PCM signal, which is 24-bit audio data, and also decodes the decoding information conversion unit 13. Thus, the converted decoding information corresponding to the number of bits is generated as the lower bits of the audio data, and both are synthesized.

  For example, when the bit number information from the host processor 30 is 4 bits, the bit rounding processing unit 12 rounds off the lower 4 bits of 24-bit audio data (PCM signal) schematically shown in FIG. The upper 20-bit audio data schematically shown in FIG. 3B is output as an upper-bit signal. On the other hand, the decode information conversion unit 13 generates 4-bit converted decode information and outputs it as lower bits of audio data.

As schematically shown in FIG. 3C, the multiplexer 14 has the rounded 20-bit audio data (PCM signal) on the upper bit side, and the 4-bit converted decoding information on the lower bit side. The S ² I signal including the data that has been combined and made up to a total of 24 bits is generated and output. That is, the 24-bit audio data schematically shown in FIG. 3C is data in which the decoded information is embedded in the lower 4 bits and is transmitted in the signal form of the S ² I signal. Here, the host processor 30 designates only the number of bits of the decoding information embedded in the lower bits of the 24-bit audio data to the decoding processor 10 and the post processing processor 20.

Next, the configuration and operation of the decode information conversion unit 13 in FIG. 1 will be further described. FIG. 4 is a block diagram illustrating an example of the decode information conversion unit 13. In FIG. 4, the decode information conversion unit 13 counts the word clock LRCK defined in the I ² S format by the counter 131, supplies the count value to the transfer information selection unit 133, and syncs according to the counter value. In this configuration, one of the sync pattern and the decode information from the pattern generation unit 132 is selected. Here, the transfer information selection unit 133 selects the sync pattern generated by the sync pattern generation unit 132 when the count value is “0”, and decode information as described later when the count value is other than that. By selecting predetermined decoding information corresponding to the counter value, the decoded decoding information is generated and output. The decode information conversion unit 13 can change the number of bits of the sync pattern and the number of bits of the decode information according to the bit number information designated by the host processor 30.

FIG. 5 shows each example of the transmission format of decode information to be carried on the I ² S signal. FIG. 5A shows the relationship between the counter value of the counter 131, the word lock LRCK, and the post-conversion decoded information of the lower 4 bits when the decoding information is put on the lower 4 bits of the I ² S signal. As shown in FIG. 5A, in this example, 8 bits (1 byte) of two left and right channels can be transmitted in one cycle of word lock LRCK (sampling). The converted decode information is handled in units of 1 byte.

  First, a specific sync pattern (0xFF) is detected, and the converted decoding information includes data following the sync pattern, as shown in FIG. 5A, the number of valid data bytes (n), the decoder type number, and the sampling frequency. The number is followed by the effective channel allocation, and the last byte has a check sum to prevent transmission errors. However, since there should be no 0xFF pattern other than the sync pattern, the most significant bit of the checksum is ignored during checksum verification.

FIG. 5B shows the relationship between the counter value of the counter 131, the word lock LRCK, and the post-conversion decoded information of the lower 2 bits when decoding information is put on the lower 2 bits of the I ² S signal. As shown in FIG. 5B, this example is basically the same as the case where the post-conversion decoded information is put in the lower 4 bits, but one byte of decoding information in two cycles of word lock LRCK (sampling). The only difference is that the decoding information is put on the lower 4 bits.

FIG. 6 shows the LRCK counter value, the content of the decode information, and the value when the lower 4 bits of the I ² S signal are used as the decode information. As shown in FIG. 6, when the counter value is “0”, it is a sync pattern, when it is “1”, the number of valid data bytes (bytes), when it is “2”, it is a decode type number, and when it is “3”, it is sampled Frequency number, “4” indicates valid channel allocation, and “n” indicates checksum. As shown in FIG. 6, the decode value is selected so that the decoder information that is actually sent does not overlap the sync pattern (0xFF). This is why when the number of possible channels is 8 or more, the effective channel allocation pattern requires 2 bytes.

Returning again to FIG. The host processor 20 includes a demultiplexer 21, a decode information analyzer 22, and an audio post processor 23. The demultiplexer 21 separates the supplied I ² S signal into an upper bit side PCM signal and a lower bit side converted decoding information in accordance with the number of bits designated by the host processor 30. At this time, it is preferable to set zero to the lower bits of the PCM signal after the decoding information is removed. Thereby, when the decoding information repeats a specific bit pattern, regular noise can be prevented from being mixed into the PCM signal. It is also possible to generate a pseudo random bit pattern in the voice post processing unit and set the pseudo random number as the lower bits of the PCM signal. In this way, the S / N ratio on hearing is improved by the dither effect.

  The decode information analysis unit 22 is supplied with the post-conversion decode information separated by the demultiplexer 14 and restores / extracts information necessary for post processing according to the number of bits specified by the host processor 30, Output as a parameter of the processing unit 23. The audio post processing unit 23 executes equalizing processing, virtual surround processing, bus management processing, etc. of the PCM signal separated by the demultiplexer 14 according to the parameters required for the post processing from the decoding information analysis unit 22, The obtained post-processed PCM signal is generated and supplied to the D / A converter 41.

  Next, the configuration and operation of the decode information analysis unit 22 in FIG. 1 will be further described. FIG. 7 is a block diagram illustrating an example of the decode information analysis unit 22. As shown in FIG. 7, the decode information analysis unit 22 includes a counter 221, a sync pattern detection unit 222, and a transfer information selection unit 223, and performs an operation reverse to that of the decode information conversion unit 13.

  In the decode information analysis unit 22, the sync pattern detection unit 222 detects the sync pattern in the decoded information after conversion, and supplies the detection signal to the counter 221. When the sync pattern detection signal is supplied from the sync pattern detection unit 222, the counter 221 starts counting the word clock LRCK and supplies the counter value to the transfer information selection unit 223. The transfer information selection unit 223 selects post-conversion decoding information corresponding to the counter value and outputs it as a parameter for host processing. Similarly to the decode information conversion unit 13, the decode information analysis unit 22 can change the number of bits of the sync pattern and the number of bits of the converted decode information to the number of bits according to the bit number information from the host processor 30.

  Returning again to FIG. The D / A conversion unit 41 converts the PCM signal post-processed by the audio post-processing unit 23 into an audio signal that is an analog signal, further amplifies the audio signal to a required level by the amplifier 42, and then the speaker 43 It is electro-acoustic converted and output as sound.

  As described above, according to the present embodiment, the rounding process of truncating the lower bits of the predetermined number of bits of the audio data (PCM signal) is performed, and the decoded decoding information is embedded in the lower bits of the rounded audio data. Since the data is generated and transmitted to the post processor 20, it is possible to transmit the decode information with a small delay (that is, efficient) between the decode processor 10 and the post processor 20, and when the sound source stream is switched. It is possible to reduce the mute interval. Further, according to the present embodiment, since the mediation of the host processor 30 is not necessary, the processing load on the host processor 30 can be reduced.

  Next, another embodiment of the present invention will be described.

In the above embodiment, the decoder processor 10 and the post processor 20 are connected by a one-path I ² S signal. However, an ordinary audio decoder that decodes an encoded audio signal of an encoding method such as Dolby Digital needs to transmit data of 6 channels or more. For this reason, as shown in FIG. 8, the decoder processor and the host processing processor are usually connected with I ² S signals of 3 to 4 paths, and the present invention can also be applied to such a case. .

FIG. 8 shows a block diagram of another embodiment of the information transmission apparatus according to the present invention. The information transmission apparatus 50 according to the present embodiment is configured to generate four types of I ² S signals I ² S — 0, I ² S — 1, I ² S — ² , and I ² S — 3 by the decoder processor 51 and supply them to the host processor 52 in parallel.

FIG. 9 shows an example of channel allocation of the I ² S signal in FIG. As shown in FIG. 9, I2S_0 is an I ² S signal that transmits audio signals of the left channel (Left) and the right channel (Right), and I2S_1 is an audio signal of the center channel (Center) and the subwoofer channel (Subwoofer). I ² S signal to be transmitted, I2S_2 is an I ² S signal to transmit the audio signal of the left surround channel (Left surround) and the right surround channel (Right surround), I2S_3 is the left rear surround channel (Left back surround) and the right This is an I ² S signal for transmitting an audio signal of a rear surround channel (Right back surround).

Among these audio signals, the audio signal of a predetermined channel is, for example, the lower-order predetermined bits of 24 bits are cut off, and the decoder information is embedded in the lower-order bits, and the above I ² S signals I2S_0, I2S_1, I2S_2, I2S_3 And transmitted to the post processor 52.

Here, if decoding information is placed on the left and right channels and the center / subwoofer channel, it is considered that the influence of deterioration in sound quality due to bit dropping of the PCM signal is great. Therefore, it is possible to avoid the deterioration of sound quality as much as possible by selecting the I ² S path of the channel (for example, the left rear surround channel and the right rear surround channel) that is less affected by the sound quality deterioration.

  Since the sound of the rear channel such as the left rear surround channel and the right rear surround channel is not as high as the sensitivity of human hearing to the sound of the front channel, it can be said that the sound quality is less affected. Further, in a general 5.1 channel audio signal, the audio signal power of the left channel, the center channel, and the right channel is relatively larger than the power of the audio signal of the surround channel. That is, the sound of the front channel is always present, while the sound of the rear channel is present only in a scene with a large acoustic effect. From this fact, it can be said that the rear channel is a channel with little influence of quality deterioration.

  According to the present embodiment, rounding processing is performed to discard lower bits of a predetermined number of bits of rear channel audio data (PCM signal), and post-conversion decoding information is embedded in lower bits of the rounded rear channel audio data. Since the audio data is generated and transmitted to the post processor 52, it is possible to transmit decode information with a small delay between the decode processor 51 and the post processor 52, and to reduce the mute section when switching the sound source stream. It becomes possible.

DESCRIPTION OF SYMBOLS 1 Information transmission apparatus 11 Voice decoding part 12 Bit rounding process part 13 Decoding information conversion part 14 Multiplexer 20 Post-processing processor 21 Demultiplexer 22 Decoding information analysis part 23 Voice post-processing part 30 Host processor 41 D / A conversion part 42 Amplifier 43 Speakers 131 and 221 Counter 132 Sync pattern generation unit 133 and 223 Transfer information selection unit 222 Sync pattern detection unit

Claims (4)

Decoding means for decoding the encoded audio signal to separate and output the digital audio signal of the first number of bits and the decoding information;
Bit rounding processing means for truncating a signal of the second number of bits on the lower side of the digital audio signal;
Decode information conversion means for converting the decode information into decoded information after conversion of the second number of bits and outputting the decoded information;
The post-conversion decoding information of the second number of bits output from the decoding information conversion unit is synthesized on the lower bit side of the rounded digital audio signal output from the bit rounding processing unit, and the post-conversion An information transmission apparatus comprising: a synthesizing unit that generates a digital audio signal having the first number of bits in which decoding information is embedded in lower bits and outputs the digital audio signal to a post processing processor for performing post processing. Decode the encoded audio signal in which a plurality of channels of audio signals including at least the front left and right channels and the rear channel are encoded, and separate the digital audio signal of each channel of the first number of bits from the decoding information. Decoding means for outputting;
Bit rounding processing means for truncating a signal of the second number of bits on the lower side of the digital audio signal of the rear channel among the digital audio signals of each channel;
Decode information conversion means for converting the decode information into decoded information after conversion of the second number of bits and outputting the decoded information;
The post-conversion decoded information of the second number of bits output from the decoding information conversion means is synthesized on the lower bit side of the rounded digital audio signal of the rear channel output from the bit rounding processing means. And a synthesis means for generating a digital audio signal of the rear channel of the first number of bits in which the decoded decoding information is embedded in lower bits and outputting the digital audio signal to a post processing processor for performing post processing. A characteristic information transmission apparatus. The decode information conversion means includes
Counting means for generating a counter value whose value changes at a constant period;
Sync pattern generating means for generating a sync pattern of the second number of bits determined in advance;
After selecting the sync pattern from the sync pattern generation unit according to the counter value, the decoding information including a plurality of decoding contents supplied from the decoding unit is used for the decoding contents of each decoding content according to the counter value. 3. The information transmission apparatus according to claim 1, further comprising selection means for selecting decoding information having a bit number of 2 and outputting the decoded decoding information as the converted decoding information.   4. The host processor according to claim 1, further comprising: a host processor that supplies bit number information specifying the second number of bits to the bit rounding processing unit and the decode information conversion unit. Information transmission equipment.