CN114172372A - Current equalizing circuit and current equalizing system based on COT buck converter - Google Patents

Current equalizing circuit and current equalizing system based on COT buck converter Download PDF

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Publication number
CN114172372A
CN114172372A CN202111502538.9A CN202111502538A CN114172372A CN 114172372 A CN114172372 A CN 114172372A CN 202111502538 A CN202111502538 A CN 202111502538A CN 114172372 A CN114172372 A CN 114172372A
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tube
current
voltage
electrode
pmos
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李海波
尹虎君
刘天杰
刘真
张磊
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Jiangyin Xinji Technology Co ltd
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Jiangyin Xinji Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

Abstract

The invention discloses a current equalizing circuit and a current equalizing system based on a COT (chip on top of a test) buck converter, wherein the current equalizing circuit comprises: the current sampling unit is used for acquiring a current sampling signal representing the magnitude of the inductive current in the COT buck converter; and the current balance control unit is used for converting the current sampling signal into a reference voltage signal which is gradually reduced along with the increase of the inductive current in the COT buck converter, so that current sharing control is realized. The invention can realize the current sharing control when the multi-phase parallel connection is used under the COT framework.

Description

Current equalizing circuit and current equalizing system based on COT buck converter
Technical Field
The invention belongs to the technical field of COT (chip on the go) buck converters, and particularly relates to a current equalizing circuit and a current equalizing system based on a COT buck converter.
Background
Referring to FIG. 1, a circuit diagram of a prior art buck converter is shown, the buck converter including a circuit configured to receive an input voltage VINAnd a pair of power switches M1 and M2, and are alternately turned on and off to generate a switching output voltage V at a switching node (SW)SW. Switch output voltage VSWIs directly coupled to a circuit comprising an output inductor L and an output capacitor COUTTo generate at the output a regulated output voltage V having a substantially constant magnitudeOUT. The output voltage V can then be usedOUTTo drive a load, whereby the buck converter provides a load current to cause the output voltage VOUTIs maintained at a constant level.
The buck converter includes a feedback control circuit to regulate energy transfer to the LC filter circuit to maintain the constant output voltage within desired load limits of the circuit. More specifically, the feedback control circuit causes the power switches M1 and M2 to turn on and off to output the voltage VOUTRegulated to be equal to reference voltage VREFOr with a reference voltage VREFThe voltage value concerned. In the present embodiment, the output voltage V is divided using a voltage divider including voltage dividing resistors R1 and R2OUTWhich is then taken as the feedback voltage V on the feedback nodeFBFed back to the buck converter. The comparator will feed back the voltage VFBAnd a reference voltage VREFAnd (6) comparing. The comparator outputs are coupled to the controller and gate drive circuitry to generate control voltages for the power switches based on the buck converter control scheme, which are used to generate drive signals for the power switches M1 and M2.
Constant On Time (COT) -based buck converters are widely used in industry due to certain important advantages, such as fast loading transient response and easy control of relatively large off time and very small constant on time to regulate high input voltages to low output voltages. A constant on-time regulator is one type of voltage regulator that employs ripple mode control in which the output voltage is regulated based on a ripple component in the output signal. All switch-mode regulators generate an output ripple current by switching an output inductor due to the switching action at the power switch. This current ripple itself is mainly due to the output capacitor C placed in parallel with the loadOUTThe equivalent series resistance in (b) appears as an output voltage ripple.
However, in the prior art, in a system in which a plurality of power management chips (a plurality of power levels) are connected in parallel, the load current on each chip is different, which affects the overall efficiency of the system. And when the load current exceeds the loading capacity of a single chip, the system may not work normally and enter an overload protection mode.
Therefore, in order to solve the above technical problems, it is necessary to provide a current sharing circuit and a current sharing system based on a COT buck converter.
Disclosure of Invention
In view of the above, the present invention provides a current-sharing circuit and a current-sharing system based on a COT buck converter.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a current sharing circuit based on a COT buck converter, the current sharing circuit comprising:
the current sampling unit is used for acquiring a current sampling signal representing the magnitude of the inductive current in the COT buck converter;
and the current balance control unit is used for converting the current sampling signal into a reference voltage signal which is gradually reduced along with the increase of the inductive current in the COT buck converter, so that current sharing control is realized.
In one embodiment, the COT buck converter includes a comparator, a controller, a gate driving circuit, a first switch tube, a second switch tube, a first voltage-dividing resistor, a second voltage-dividing resistor, an output inductor, and an output capacitor, wherein:
the first switch tube and the second switch tube are sequentially connected in series with an input voltage VINA node between the first switching tube and the second switching tube and the reference potential is a switching node;
the first voltage-dividing resistor and the second voltage-dividing resistor are sequentially connected in series with the output voltage VOUTBetween the reference potential and the first voltage dividing resistor, the voltage between the first voltage dividing resistor and the second voltage dividing resistor is a divided signal;
the output inductor is connected with the switch node and the output voltage VOUTAn output capacitor connected to the output voltage VOUTAnd a reference potential;
the comparator is used for receiving the divided voltage signal and the reference voltage signal and outputting a comparison signal;
the controller and the grid driving circuit are used for generating a grid control signal according to the comparison signal so as to control the first switching tube and the second switching tube to be alternately switched on and off, so that a switching output voltage is generated at a switching node.
In one embodiment, the first switch tube is a PMOS tube, and the second switch tube is an NMOS tube, wherein:
the source electrode of the first switch tube and the input voltage VINThe drain electrode is connected with the switch node, and the grid electrode is connected with the controller and the grid electrode driving circuit;
and the source electrode of the second switching tube is connected with the reference potential, the drain electrode of the second switching tube is connected with the switching node, and the grid electrode of the second switching tube is connected with the controller and the grid electrode driving circuit.
In one embodiment, the current sampling signal is a current signal or a voltage signal.
In one embodiment, the current sampling unit includes a plurality of sampling pipes, a first PMOS pipe, a second PMOS pipe, a third PMOS pipe, a fourth PMOS pipe, a fifth PMOS pipe, a first NMOS pipe and a second NMOS pipe, a first current source, a second current source, a third resistor, and a filtering unit, wherein:
the sampling tube is connected in series with an input voltage VINBetween the first node and the source electrode of the sampling tube and the input voltage VINOr the drain electrode of the previous sampling tube is connected with the drain electrode of the first node or the source electrode of the next sampling tube, the grid electrodes of all the sampling tubes are connected with the reference potential, and the voltage of the first node is equal to the voltage of the switch node;
the source electrode of the first PMOS tube is connected with a first node, the drain electrode of the first PMOS tube is connected with a first current source and then is connected with a reference potential, and the grid electrode of the first PMOS tube is in short circuit with the drain electrode;
the source electrode of the second PMOS tube is connected with the switch node, the drain electrode of the second PMOS tube is connected with the reference potential after being connected with a second current source, and the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube;
the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the third PMOS tube is connected with the first node, the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube is in short circuit with the drain electrode, and the source electrode of the third PMOS tube is connected with the reference potential;
the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode is connected with the reference potential, the drain electrode is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is in short circuit with the drain electrode, and the source electrode is connected with the input voltage VINConnecting;
the source electrode of the fifth PMOS tube and the input voltage VINThe grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, and the drain electrode of the third PMOS tube is connected with the reference potential after being connected with the third resistor;
the filtering unit is used for filtering the voltage at the two ends of the third resistor to obtain a direct current voltage signal, namely a current sampling signal VSENSE。
In one embodiment, the filtering unit includes a first switch, a fourth resistor, and a first capacitor, wherein:
the first end of the first switch is connected with the first end of the third resistor, the second end of the first switch is connected with the first end of the fourth resistor, the second end of the fourth resistor is connected with the first pole plate of the first capacitor, the second pole plate of the first capacitor is connected with the second end of the third resistor, and the second end of the fourth resistor outputs a current sampling signal VSENSE；
The first switch is closed when being opened relative to the first switch tube and is opened when the first switch tube is closed.
In one embodiment, the current balancing control unit includes a third NMOS transistor, a fourth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth resistor, a sixth resistor, a first error amplifier, and a second error amplifier, wherein:
the source electrode of the sixth PMOS tube and the input voltage VINThe grid electrode is in short circuit with the drain electrode, the drain electrode is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the third node, and the fifth resistor is connected between the third node and the reference potential;
the source electrode of the seventh PMOS tube and the input voltage VINThe grid electrode of the third NMOS tube is in short circuit with the drain electrode, and the source electrode of the third NMOS tube is connected with the reference potential;
the source electrode of the eighth PMOS tube and the input voltage VINThe grid electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, the source electrode of the fourth NMOS tube is connected with the reference potential, and the sixth resistor is connected between the drain electrode of the eighth PMOS tube and the drain electrode of the fourth NMOS tube;
a first input terminal of the first error amplifier and a current sampling signal VSENSEThe second input end of the first NMOS tube is connected with the third node, and the output end of the first NMOS tube is connected with the grid electrode of the fifth NMOS tube;
a first input terminal of the second error amplifier and a reference voltage VREFThe second input end and the output end are both connected with a second node;
the drain electrode of the fourth NMOS tube outputs a reference voltage signal VREF_LOOP。
In one embodiment, the voltage of the second node is equal to the reference voltage VREFReference voltage signal VREF_LOOPEqual to the difference between the voltage at the second node and the voltage drop across the sixth resistor.
In one embodiment, the reference voltage signal VREF_LOOPComprises the following steps:
Figure BDA0003402298250000051
wherein K is the current sampling coefficient, IOUTTo output a current.
The technical scheme provided by another embodiment of the invention is as follows:
a current equalizing system based on a COT (chip on top of technology) buck converter comprises a plurality of power management chips, wherein each power management chip comprises the current equalizing circuit, so that inductive currents of the plurality of power management chips are equal.
The invention has the following beneficial effects:
according to the invention, the current sampling unit is used for acquiring the current sampling signal representing the magnitude of the inductive current, and the current balance control unit is used for converting the current sampling signal into the reference voltage signal gradually reduced along with the increase of the inductive current, so that the current sharing control in the multi-phase parallel connection use under the COT framework is realized.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a circuit diagram of a prior art buck converter;
FIG. 2 is a circuit diagram of a current equalizing circuit based on a COT buck converter according to the present invention;
FIG. 3 is a circuit diagram of a current sampling unit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a current balancing control unit according to an embodiment of the present invention;
FIG. 5 is a diagram of an application circuit for two chips used in parallel according to an embodiment of the present invention;
fig. 6 is a simulation waveform diagram of current sharing when two chips are used in parallel according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, the present invention discloses a current-sharing circuit based on a COT BUCK converter (COT BUCK), which includes:
the Current sampling unit (Current Sense) is used for acquiring a Current sampling signal representing the magnitude of the inductive Current in the COT buck converter;
and the Current balancing control unit (Current sharing control unit) is used for converting the Current sampling signal into a reference voltage signal which is gradually reduced along with the increase of the inductive Current in the COT buck converter, so that Current sharing control is realized.
Wherein the COT BUCK converter (COT BUCK) comprises a Comparator (Comparator), a controller and a gate drive circuit (Control Logic)&Driver), a first switch tube M1, a second switch tube M2, a first voltage-dividing resistor R1, a second voltage-dividing resistor R2, an output inductor L and an output capacitor COUTWherein:
the first switch tube M1 and the second switch tube M2 are sequentially connected in series with the input voltage VINBetween the first switch tube M1 and the second switch tube M2 and the reference potential, the node is a switch node SW;
the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are sequentially connected in series with the output voltage VOUTBetween the reference potential and the first voltage dividing resistor R1 and the second voltage dividing resistor R2, the voltage is the divided voltage signal VFB；
An output inductor L connected to the switch node SW and the output voltage VOUTBetween, the output capacitance COUTIs connected to the output voltage VOUTAnd a reference potential;
the comparator is used for receiving the voltage division signal VFBAnd a reference voltage signal VREF_LOOPAnd outputs a comparison signal;
the controller and the gate driving circuit are used for generating a gate control signal according to the comparison signal to control the first switch tube M1 and the second switch tube M2 to be alternately turned on and off to generate a switch output voltage V at the switch node SWSW。
Specifically, the first switch transistor M1 is a PMOS transistor, and the second switch transistor M2 is an NMOS transistor, wherein:
the source of the first switch transistor M1 and the input voltage VINThe drain electrode is connected with the switch node SW, and the grid electrode is connected with the controller and the grid electrode driving circuit;
the second switch transistor M2 has a source connected to the reference potential, a drain connected to the switch node SW, and a gate connected to the controller and the gate driving circuit.
The reference potential in the present embodiment is preferably the ground potential (GND) as an example, but may be another reference potential in other embodiments.
The current sampling signal in the invention is a current signal or a voltage signal. The current sampling unit can sample the current of the first switching tube M1, sample the current of the second switching tube M2, and sample any other signal representing the magnitude of the inductor current in the circuit.
Referring to fig. 3, in an embodiment of the invention, the current sampling unit samples the current of the first switch transistor M1.
Specifically, the current sampling unit in this embodiment includes a plurality of sampling tubes sense fet, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first NMOS tube MN1, a second NMOS tube MN2, a first current source I1, a second current source I2, a third resistor R3, and a filtering unit, where:
the sampling tube sense fet is connected in series with the input voltage VINBetween the first node A and the source of the sampling tube sense fet and the input voltage VINOr the drain electrode of the last sampling tube sense fet is connected, the drain electrode of the sampling tube sense fet is connected with the first node A or the source electrode of the next sampling tube sense fet, the grid electrodes of all the sampling tube sense fets are connected with the reference potential, and the voltage of the first node A is equal to the voltage of the switch node SW;
the source electrode of the first PMOS tube MP1 is connected with the first node A, the drain electrode is connected with the first current source I1 and then is connected with the reference potential, and the grid electrode is in short circuit with the drain electrode;
the source electrode of the second PMOS tube MP2 is connected with the switch node SW, the drain electrode is connected with the second current source I2 and then connected with the reference potential, and the grid electrode is connected with the grid electrode of the first PMOS tube MP 1;
the grid electrode of the third PMOS tube MP3 is connected with the drain electrode of the second PMOS tube MP2, the source electrode is connected with the first node A, the drain electrode is connected with the drain electrode of the first NMOS tube MN1, the grid electrode of the first NMOS tube MN1 is in short circuit with the drain electrode, and the source electrode is connected with the reference potential;
the grid electrode of the second NMOS transistor MN2 is connected with the grid electrode of the first NMOS transistor MN1, the source electrode is connected with the reference potential, the drain electrode is connected with the drain electrode of the fourth PMOS transistor MP4, the grid electrode and the drain electrode of the fourth PMOS transistor MP4 are in short circuit, and the source electrode is connected with the input voltage VINConnecting;
the source of the fifth PMOS transistor MP5 and the input voltage VINThe grid electrode of the PMOS tube MP4 is connected with the grid electrode of the fourth PMOS tube MP4, and the drain electrode of the PMOS tube MP4 is connected with the reference potential after being connected with the third resistor R3;
the filtering unit is used for filtering the voltage at the two ends of the third resistor R3 to obtain a direct-current voltage signal, namely a current sampling signal VSENSE。
Preferably, the filtering unit in this embodiment includes a first switch1, a fourth resistor R4, and a first capacitor C1, wherein:
a first end of the first switch1 is connected to a first end of the third resistor R3, a second end of the first switch is connected to a first end of the fourth resistor R4, a second end of the fourth resistor R4 is connected to a first plate of the first capacitor C1, a second plate of the first capacitor C1 is connected to a second end of the third resistor R3, and a second end of the fourth resistor R4 outputs a current sampling signal VSENSE；
The first switch1 is closed when the first switch M1 is turned on and is opened when the first switch M1 is turned off.
In this embodiment, the current sampling unit samples the current of the first switch transistor M1, and when the first switch transistor M1 is turned on, V is setINAnd SW is respectively connected with the source end and the drain end of the first switch tube M1, and the voltage generated at the node A after the sampling current flows through the sampling tube is just equal to the voltage of the SW node. At this time, the source terminal, the drain terminal and the gate voltage of the sampling tube are equal to those of M1, and the extracted current is related to the W/L ratio of the sampling tube to M1.
After the sampling current is mirrored through two pairs of current mirrors of MN1/MN2 and MP4/MP5, the sampling current is converted into a voltage signal through a resistor R3, a first switch1 is closed when a first switch tube M1 is opened, and is opened when the first switch tube M1 is closed, and the voltage on the R3 is filtered into a direct-current voltage signal V through switches 1, R4 and C1SENSEAnd the voltage signal is proportional to the average value of the inductor current.
Of course, in other embodiments, the current sampling unit may also sample the current of the second switch transistor M2, or for a sampling circuit that samples any other signal representing the magnitude of the inductor current, the circuit structure is similar, and it is not described here by way of example.
Referring to fig. 4, the current balancing control unit in an embodiment of the invention includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a fifth resistor R5, a sixth resistor R6, a first error amplifier EA1, and a second error amplifier EA2, where:
the source of the sixth PMOS transistor MP6 and the input voltage VINThe grid electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the fifth NMOS tube MN5 in a short circuit mode, the source electrode of the fifth NMOS tube MN5 is connected with a third node C, and a fifth resistor R5 is connected between the third node C and a reference potential;
the source of the seventh PMOS transistor MP7 and the input voltage VINThe grid electrode of the third NMOS tube MN3 is in short circuit with the drain electrode, and the source electrode is connected with the reference potential;
the source of the eighth PMOS transistor MP8 and the input voltage VINThe gate of the sixth PMOS transistor MP6 is connected to the drain of the sixth PMOS transistor MP6, the drain of the fourth NMOS transistor MN4 is connected to the gate of the third NMOS transistor MN3, the source of the fourth NMOS transistor MN4 is connected to the reference potential, and the sixth resistor R6 is connected between the drain of the eighth PMOS transistor MP8 and the drain of the fourth NMOS transistor MN 4;
first input terminal of first error amplifier EA1 and current sampling signal VSENSEThe second input end of the NMOS transistor is connected with the third node C, and the output end of the NMOS transistor is connected with the grid electrode of the fifth NMOS transistor MN 5;
first input terminal of second error amplifier EA2 and reference voltage VREFThe second input end and the output end are both connected with a second node B;
the drain electrode of the fourth NMOS tube MN4 outputs a reference voltage signal VREF_LOOP。
The current balance control unit in this embodiment converts the current sampling signal into the current following inductanceReference voltage signal V with slowly decreasing flow increasingREF_LOOP. The larger the inductive current is, the current sampling signal VSENSEThe larger the current, and thus the larger the current generated at resistor R5, the larger the current flowing through R6.
The voltage of the second node B is equal to the reference voltage V under the action of EA2REFReference voltage signal VREF_LOOPEqual to the difference between the voltage at the second node B and the voltage drop across the sixth resistor R6.
I.e. the reference voltage signal VREF_LOOPComprises the following steps:
Figure BDA0003402298250000091
wherein K is the current sampling coefficient, IOUTTo output a current.
The invention also discloses a current-sharing system based on the COT buck converter, which comprises a plurality of power management chips, wherein each power management chip comprises the current-sharing circuit, so that the inductive currents of the power management chips are equal.
Referring to fig. 5, in the embodiment of the present invention, two power management chips chip1 and chip2 are taken as examples for explanation, chip1 and chip2 respectively include the current equalizing circuits (the current sampling unit and the current equalization control unit) in the above embodiments, and output inductors corresponding to chip1 and chip2 are L1 and L2, respectively.
When the chip1 and the chip2 do not use the current sharing circuit, it is easy to happen that one chip provides most of the load current, and the other chip provides a little of the load current, which affects the overall efficiency of the system. When the load greatly exceeds the loading capacity of a single chip, the system may not work normally and enter an overload protection mode.
In this embodiment, both the chip1 and the chip2 use current sharing circuits, which can avoid the above situation, when the current provided by one chip (assume chip1) is greater than the current provided by the other chip (assume chip2), the current sampling units can respectively collect two inductive currents, and the current balancing control unit will make the chip1 have a current sharing functionReference voltage VREF_LOOP1Reference voltage V of reduced ratio chip2REF_LOOP2Lower so that the turn-off time of each cycle of the chip1 is longer than that of the chip2, the inductor current of the chip1 will gradually decrease and the inductor current of the chip2 will gradually increase until the inductor currents of the chip1 and the chip2 are equal to reach the equilibrium state, thereby stabilizing in the equilibrium state.
Referring to fig. 6, which is a simulated waveform diagram in the present embodiment, it can be seen that when the load dynamically changes, the inductor currents of L1 and L2 tend to equally share the load current and change uniformly, which indicates that the present invention can achieve a good current sharing effect.
According to the technical scheme, the invention has the following advantages:
according to the invention, the current sampling unit is used for acquiring the current sampling signal representing the magnitude of the inductive current, and the current balance control unit is used for converting the current sampling signal into the reference voltage signal gradually reduced along with the increase of the inductive current, so that the current sharing control in the multi-phase parallel connection use under the COT framework is realized.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (10)

1. A current share circuit based on a COT buck converter, the current share circuit comprising:
the current sampling unit is used for acquiring a current sampling signal representing the magnitude of the inductive current in the COT buck converter;
and the current balance control unit is used for converting the current sampling signal into a reference voltage signal which is gradually reduced along with the increase of the inductive current in the COT buck converter, so that current sharing control is realized.
2. The COT buck converter based current sharing circuit according to claim 1, wherein the COT buck converter comprises a comparator, a controller, a gate driving circuit, a first switch tube, a second switch tube, a first voltage dividing resistor, a second voltage dividing resistor, an output inductor and an output capacitor, and wherein:
the first switch tube and the second switch tube are sequentially connected in series with an input voltage VINA node between the first switching tube and the second switching tube and the reference potential is a switching node;
the first voltage-dividing resistor and the second voltage-dividing resistor are sequentially connected in series with the output voltage VOUTBetween the reference potential and the first voltage dividing resistor, the voltage between the first voltage dividing resistor and the second voltage dividing resistor is a divided signal;
the output inductor is connected with the switch node and the output voltage VOUTAn output capacitor connected to the output voltage VOUTAnd a reference potential;
the comparator is used for receiving the divided voltage signal and the reference voltage signal and outputting a comparison signal;
the controller and the grid driving circuit are used for generating a grid control signal according to the comparison signal so as to control the first switching tube and the second switching tube to be alternately switched on and off, so that a switching output voltage is generated at a switching node.
3. The COT buck converter-based current sharing circuit of claim 2, wherein the first switch tube is a PMOS tube, and the second switch tube is an NMOS tube, wherein:
the source electrode of the first switch tube and the input voltage VINThe drain electrode is connected with the switch node, and the grid electrode is connected with the controller and the grid electrode driving circuit;
and the source electrode of the second switching tube is connected with the reference potential, the drain electrode of the second switching tube is connected with the switching node, and the grid electrode of the second switching tube is connected with the controller and the grid electrode driving circuit.
4. The COT buck converter based current sharing circuit according to claim 1, wherein the current sampling signal is a current signal or a voltage signal.
5. The COT buck converter-based current sharing circuit according to claim 2, wherein the current sampling unit comprises a plurality of sampling pipes, a first PMOS pipe, a second PMOS pipe, a third PMOS pipe, a fourth PMOS pipe, a fifth PMOS pipe, a first NMOS pipe, a second NMOS pipe, a first current source, a second current source, a third resistor, and a filtering unit, wherein:
the sampling tube is connected in series with an input voltage VINBetween the first node and the source electrode of the sampling tube and the input voltage VINOr the drain electrode of the previous sampling tube is connected with the drain electrode of the first node or the source electrode of the next sampling tube, the grid electrodes of all the sampling tubes are connected with the reference potential, and the voltage of the first node is equal to the voltage of the switch node;
the source electrode of the first PMOS tube is connected with a first node, the drain electrode of the first PMOS tube is connected with a first current source and then is connected with a reference potential, and the grid electrode of the first PMOS tube is in short circuit with the drain electrode;
the source electrode of the second PMOS tube is connected with the switch node, the drain electrode of the second PMOS tube is connected with the reference potential after being connected with a second current source, and the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube;
the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the third PMOS tube is connected with the first node, the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube is in short circuit with the drain electrode, and the source electrode of the third PMOS tube is connected with the reference potential;
the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tubeThe drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is in short circuit with the drain electrode, and the source electrode of the fourth PMOS tube is connected with the input voltage VINConnecting;
the source electrode of the fifth PMOS tube and the input voltage VINThe grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, and the drain electrode of the third PMOS tube is connected with the reference potential after being connected with the third resistor;
the filtering unit is used for filtering the voltage at the two ends of the third resistor to obtain a direct current voltage signal, namely a current sampling signal VSENSE。
6. The COT buck converter-based current sharing circuit of claim 5, wherein the filtering unit comprises a first switch, a fourth resistor and a first capacitor, wherein:
the first end of the first switch is connected with the first end of the third resistor, the second end of the first switch is connected with the first end of the fourth resistor, the second end of the fourth resistor is connected with the first pole plate of the first capacitor, the second pole plate of the first capacitor is connected with the second end of the third resistor, and the second end of the fourth resistor outputs a current sampling signal VSENSE；
The first switch is closed when being opened relative to the first switch tube and is opened when the first switch tube is closed.
7. The COT buck converter-based current sharing circuit according to claim 5, wherein the current balancing control unit comprises a third NMOS transistor, a fourth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth resistor, a sixth resistor, a first error amplifier and a second error amplifier, wherein:
the source electrode of the sixth PMOS tube and the input voltage VINThe grid electrode is in short circuit with the drain electrode, the drain electrode is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the third node, and the fifth resistor is connected between the third node and the reference potential;
the source electrode of the seventh PMOS tube and the input voltage VINThe grid is connected with the grid of the sixth PMOS tube, the drain is connected with the drain of the third NMOS tube, andthe grid electrode of the three NMOS tubes is in short circuit with the drain electrode, and the source electrode is connected with the reference potential;
the source electrode of the eighth PMOS tube and the input voltage VINThe grid electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, the source electrode of the fourth NMOS tube is connected with the reference potential, and the sixth resistor is connected between the drain electrode of the eighth PMOS tube and the drain electrode of the fourth NMOS tube;
a first input terminal of the first error amplifier and a current sampling signal VSENSEThe second input end of the first NMOS tube is connected with the third node, and the output end of the first NMOS tube is connected with the grid electrode of the fifth NMOS tube;
a first input terminal of the second error amplifier and a reference voltage VREFThe second input end and the output end are both connected with a second node;
the drain electrode of the fourth NMOS tube outputs a reference voltage signal VREF_LOOP。
8. The COT buck converter based current sharing circuit of claim 7, wherein the voltage of the second node is equal to a reference voltage VREFReference voltage signal VREF_LOOPEqual to the difference between the voltage at the second node and the voltage drop across the sixth resistor.
9. The COT buck converter based current sharing circuit of claim 8, wherein the reference voltage signal VREF_LOOPComprises the following steps:
Figure FDA0003402298240000031
wherein K is the current sampling coefficient, IOUTTo output a current.
10. A current equalizing system based on COT buck converter is characterized in that the current equalizing system comprises a plurality of power management chips, each power management chip comprises the current equalizing circuit of any one of claims 1-9, so that the inductive currents of the plurality of power management chips are equal.
CN202111502538.9A 2021-12-09 2021-12-09 Current equalizing circuit and current equalizing system based on COT buck converter Pending CN114172372A (en)

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