CN114172125A - Power supply and distribution protection device for solid electronic switch - Google Patents
Power supply and distribution protection device for solid electronic switch Download PDFInfo
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- CN114172125A CN114172125A CN202111400363.0A CN202111400363A CN114172125A CN 114172125 A CN114172125 A CN 114172125A CN 202111400363 A CN202111400363 A CN 202111400363A CN 114172125 A CN114172125 A CN 114172125A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/22—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for distribution gear, e.g. bus-bar systems; for switching devices
- H02H7/222—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for distribution gear, e.g. bus-bar systems; for switching devices for switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J13/00—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
- H02J13/00002—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by monitoring
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J13/00—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
- H02J13/00032—Systems characterised by the controlled or operated power network elements or equipment, the power network elements or equipment not otherwise provided for
- H02J13/00036—Systems characterised by the controlled or operated power network elements or equipment, the power network elements or equipment not otherwise provided for the elements or equipment being or involving switches, relays or circuit breakers
- H02J13/0004—Systems characterised by the controlled or operated power network elements or equipment, the power network elements or equipment not otherwise provided for the elements or equipment being or involving switches, relays or circuit breakers involved in a protection system
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/20—Systems supporting electrical power generation, transmission or distribution using protection elements, arrangements or systems
Abstract
The invention relates to a power supply and distribution protection device of a solid-state electronic switch, which comprises a first chip (1), a second chip (2) and a power loop (3), wherein a hard wire configuration port (101), a bus configuration port (102) and an algorithm control circuit (103) are arranged in the first chip (1), and the hard wire configuration port (101) and the bus configuration port (102) are respectively used for receiving an external hard wire configuration signal and a bus configuration signal and transmitting the external hard wire configuration signal and the bus configuration signal to the algorithm control circuit (103) so as to configure the working mode and parameters of the device. The invention can not only avoid the defects of complicated circuit, device types and the like which are not beneficial to miniaturization caused by separating devices, but also avoid the defect of limited application range caused by simple and single function of the traditional electronic switch based on a special controller.
Description
Technical Field
The invention relates to a power supply and distribution protection device of a solid-state electronic switch.
Background
The solid-state electronic switch adopts a power tube as a core control switch, and is widely applied to various fields due to the advantages of no contact, no electric arc, no noise, quick response, small electromagnetic interference, long service life, high reliability and the like. In the prior art, from the protection characteristic point of view, a solid-state electronic switch with a protection function and a solid-state electronic switch without a protection function are included. The solid-state electronic switch with protection function is mainly a solid-state relay and mainly comprises a relay based on I2the solid-state power controller products with t function and short circuit immediate tripping function and the solid-state current limiting switch products based on constant current limiting function.
The realization of the solid-state electronic switch function and the drive control mode thereof is mainly divided into two types, the first type is a drive control circuit built by adopting a separation circuit, and the second type is a drive control circuit realized by a special control chip. The first implementation mode has many types and numbers of components, so that high-density integration and miniaturization are difficult to realize; the second type of dedicated controller has a relatively single function, and generally can only implement part of functions of the solid-state electronic switch, such as a relay type dedicated controller, a solid-state power controller type dedicated controller, a solid-state current-limiting switch type dedicated controller, and the like, which cannot implement on-line programming of functions, so that the application range is greatly limited.
Disclosure of Invention
The invention aims to provide a power supply and distribution protection device of a solid-state electronic switch.
In order to achieve the above object, the present invention provides a power supply and distribution protection device for a solid-state electronic switch, including a first chip, a second chip, and a power loop, where the first chip is provided with a hard-wire configuration port, a bus configuration port, and an algorithm control circuit, and the hard-wire configuration port and the bus configuration port are respectively used for receiving an external hard-wire configuration signal and a bus configuration signal and transmitting the signals to the algorithm control circuit to configure a working mode and parameters of the device.
According to an aspect of the present invention, the first chip further includes:
a power supply circuit for supplying power to the device;
a PLL (phase locked loop) circuit for receiving an input clock signal and providing a clock reference for the first chip;
the hard wire interface is provided with an ST _ PRO pin and an ST _ OF pin;
the hard wire configuration port is provided with a RIT interface, an ALG _ EN pin and a SET _ STS pin.
According to one aspect of the invention, the second chip has:
an OSC circuit (oscillation circuit) for generating a high frequency signal and a clock square wave signal;
the parameter configuration circuit is used for receiving and outputting configurable parameters;
the enabling configuration circuit is used for receiving an enabling or disabling command and carrying out function activation or function deactivation;
a state telemetry circuit for telemetry of the states of the digital and analog signals;
the voltage conversion circuit is used for carrying out secondary conversion on the input voltage to form a plurality of paths of voltages;
an ADC (analog-to-digital conversion) circuit for collecting the sampling voltage of the power loop and converting the sampling voltage into a digital signal;
the state coding circuit is used for performing state coding on the digital signal and outputting the digital signal;
the MOS tube driving circuit is used for driving and controlling the power loop;
the digital signal comprises a switch state, a protection state, a configuration bit and a working mode, and the analog signal is a current value acquired by the power loop.
According to an aspect of the present invention, the second chip further includes:
and the signal isolation circuit is used for receiving the signals output by the parameter configuration circuit, the enabling configuration circuit and the state coding circuit and carrying out high-frequency processing on the signals.
According to one aspect of the invention, the signal isolation circuit comprises a modem circuit and an on-chip transformer, the on-chip transformer being integrated on the second chip;
the signal isolation circuit adopts a magnetic isolation mode to modulate and demodulate current flowing between a drain electrode and a source electrode of a controlled object MOSFET (metal oxide semiconductor field effect transistor) and a path of externally acquired voltage analog quantity signal so as to realize magnetic isolation output.
According to one aspect of the invention, the power loop comprises:
the power MOSFET is used for controlling the on and off of the power loop;
and the sampling resistor is used for acquiring the current signal of the power loop.
According to one aspect of the invention, a master TWI interface and a slave TWI interface (two-wire interface) are respectively arranged in the first chip and the second chip.
According to one aspect of the invention, the device further comprises a hard-wired instruction input mode configuration pin and an on/off instruction input pin;
the bus configuration port adopts an SPI (serial peripheral interface) standard serial interface mode and is provided with a clock input pin, two bidirectional data input and output pins and a chip selection signal control pin;
the clock input pin and the bidirectional data input and output pin are shared pins, output is performed in an open-drain mode, and parallel control of 256 products can be supported.
According to one aspect of the invention, in burst mode, hard-wired burst commands are active simultaneously with software commands, with software commands prioritized in case of conflict;
in the level command mode, one of a hard-wired level command and a software command is active.
According to one aspect of the present invention, the apparatus has a protection function, a state monitoring function, and a mode control function;
the protection function comprises an overload protection function and a short-circuit protection function;
the overload protection function comprises current limiting protection and overcurrent protection;
the current-limiting protection adopts a closed-loop regulation mode, and when an external MOSFET (metal oxide semiconductor field effect transistor) of the integrated controller is tested and an external short circuit occurs outside, the closed-loop control inside the integrated controller is realized;
the over-current protection is I2t inverse time limit protection, namely turning off an external MOSFET after the protection time is up, and realizing mode selection and related parameter configuration through a bus configuration port or a hard line configuration port;
the short-circuit protection function is that when the external overload condition reaches a short-circuit protection point set by short-circuit protection, the short-circuit protection circuit turns off the external MOSFET in the appointed short-circuit protection time, parameter configuration is realized through a bus configuration port or a hard wire configuration port, a state ST _ PRO pin indicates after the protection action is executed, and meanwhile, the state can be inquired through the bus configuration port;
the state monitoring function comprises a hard line INT indication and a bus state output, after protection action occurs, the state indication is output through an interruption output pin INT, state information is written into a register corresponding to the functional circuit, and the state can be inquired through an SPI bus interface;
the mode control function comprises a time delay turn-off control mode, a repeated overload control mode and a turn-back control mode, and whether the mode control function is started or not is selected through an SPI bus configuration port;
when the time delay turn-off control mode is gated, timing is started from the instruction turning-on, and when the turning-on time of the MOSFET reaches the set timing time, the MOSFET is turned off;
when the repeated overload control mode is gated, the MOSFET automatically turns on again when the duration time reaches the re-triggering time set value after the overload protection is disconnected;
when the foldback control mode is gated, the MOSFET is not turned off after the overload protection time is up, the MOSFET working mode is converted into a closed-loop regulation mode, and the current is continuously maintained according to the set foldback current-limiting point;
the calculation formula of the foldback current limiting point is as follows:
wherein, VDSThe voltage between the drain electrode and the source electrode of the MOSFET is shown, and Rsense is the resistance value of the sampling resistor;
I2and (3) carrying out protection control on the t inverse time limit protection algorithm according to the following formula:
wherein, K. M, Ie、IpAll the parameters are configurable parameters and can be configured through an RIT or a bus unit;
t is algorithm protection time, K is protection characteristic type, the value is constant, M is setting coefficient, IeTo rated current value, IpAnd I is the current obtained by sampling, and is the multiple of the protection current and the rated current.
According to the concept of the invention, the core part of the power supply and distribution protection device of the multifunctional chip type solid-state electronic switch is composed of two core chips and a power loop, and the core chips are used for re-integrating functions, so that compared with a mode of separating devices, the power supply and distribution protection device of the multifunctional chip type solid-state electronic switch avoids the defects that the circuit is complex, the devices are various and are not beneficial to miniaturization, and the defect that the application range is limited due to the fact that the traditional solid-state electronic switch designed by a special controller is simple/single in function and cannot be configured is avoided. The device can be applied to the functions of switch control, over-current protection, fault isolation and recovery and the like of the distribution line.
According to one scheme of the invention, the core chip has the functions of analog quantity acquisition, isolated output and digital signal isolated input and output, parameter configuration can be realized through a bus configuration interface and a hard wire configuration interface, and current limiting control and I (input/output) are realized2t overcurrent control, immediate trip protection, repeated overload, protection action self-locking, slow switch-on and slow switch-off and the like. The control unit comprises an internal power supply circuit, a hard-line instruction input interface circuit, an analog quantity telemetering isolation output circuit, a digital quantity IO isolation control circuit and an internal power supply circuitThe power distribution protection device comprises a bus interface circuit, a parameter configuration and enabling control circuit, a functional circuit, a driving circuit and an output interface circuit, so that the functions of the power distribution protection device of the solid-state electronic switch are enriched, and meanwhile, the miniaturization can be realized. Moreover, the bus unit can be configured into solid-state power controller products and solid-state relay products, so that the application coverage of the solid-state electronic switch is greatly improved.
According to one scheme of the invention, the invention reserves a hard line configuration port and a bus configuration port, thereby realizing the configuration of key parameters through the hard line configuration port or the bus configuration port and realizing the multifunction of the product. Therefore, when no controller is arranged outside, basic configuration can be realized through the hard wire configuration port, and application of basic functions is completed. Wherein, the I pair can be realized by configuring RIT interface and using hard wire configuration interface2the starting point, the rated current value and the setting factor of the t inverse time limit protection function are configured, the immediate adjustment of the protection threshold value and the protection time can be configured through a bus configuration interface, the enabling or disabling of the overcurrent protection function can be realized through a hard wire configuration port and a configuration pin ALG _ EN, and the input mode of a pin PULSE _ EN configuration port is used for selecting a level instruction or a PULSE instruction. Therefore, the multifunctional configuration of the solid-state electronic switch can be realized by reserving the hard line configuration port and the bus configuration port. Meanwhile, the hard line configuration port can meet the requirements of a user on cost and simplicity in use, and the bus configuration port can meet the design requirements of the user on special functions, intellectualization and multiple functions, so that the influence of production cost, development period and the like caused by modification of hardware design is reduced.
According to one scheme of the invention, the level initial state control of the output can be realized, namely, the SET _ STS pin is used for hard-wire configuration into two initial state modes of Latch ON and Latch OFF.
According to one aspect of the invention, I2the t inverse time limit current protection parameter can be continuously adjusted through the bus unit.
Drawings
Fig. 1 schematically shows a schematic block circuit diagram of a solid-state electronic switching power supply and distribution protection device according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
The present invention is described in detail below with reference to the drawings and the specific embodiments, which are not repeated herein, but the embodiments of the present invention are not limited to the following embodiments.
Referring to fig. 1, the multifunctional chip-type solid-state electronic switch power supply and distribution protection device (for the second implementation) of the present invention includes a first chip 1 (i.e., IC1), a second chip 2(IC2), and a power loop 3. The first chip 1 is provided with a hard-wire configuration port 101, a bus configuration port 102 and an algorithm control circuit 103, wherein the hard-wire configuration port 101 and the bus configuration port 102 are respectively used for receiving an external hard-wire configuration signal and a bus configuration signal, and transmitting the processed signals to the algorithm control circuit 103 to configure the working mode, key parameters and the like of the device. The power circuit 3 is a power channel of a chip-type solid-state electronic switch power supply and distribution protection device, and comprises a power MOSFET301 and a sampling resistor 302, wherein the power MOSFET301 is used for controlling the on and off functions of the power circuit 3, and the sampling resistor 302 is used for realizing the functions of current telemetering, overcurrent state detection and the like of the power circuit 3 by collecting current signals of the power circuit 3.
Therefore, the protection device has the functions of on-off control, current signal monitoring, instruction input, telemetering state output and isolation of the power loop 3 of the MOSFET power loop, and realizes current-limiting control and I by combining external parameter configuration and an enable bit2And (4) gating or combining functions of t overcurrent control, immediate trip protection, protection action self-locking, slow-opening switching-on and slow-off and the like to realize multifunctional application.
The first chip 1 and the second chip 2 are also respectively provided with a master TWI interface 106 and a slave TWI interface 210 (master SPI interface and a slave SPI interface), and information interaction between the first chip 1 and the second chip 2 is completed through a standard SPI protocol, and the functions of state signals, current signals, configuration parameters and the like are included.
The first chip 1 is further provided with: a power supply circuit 104, a PLL circuit 105, and a hard-wired interface 107. The power supply circuit 104 is configured to supply power to the device, receive an input voltage provided from an external source, transmit a part of the input voltage directly to other circuits inside the first chip 1 to implement power supply, and output another part of the input voltage to the OSC circuit in the second chip 2, where the OCS circuit performs high-frequency signal conversion, performs isolation control of the on-chip transformer, and outputs the converted high-frequency signal to the voltage conversion (adjustment) circuit inside the second chip 2 to perform voltage adjustment, and then forms a multi-path isolated DCDC voltage to provide voltage for the other circuits inside the second chip 2. The PLL circuit 105 is configured to receive an input clock signal and provide a clock reference for the first chip 1, and specifically, receive a 1MHz input clock signal generated by the second chip 2 or an external clock circuit, and generate a 20MHz high-frequency square wave signal after frequency multiplication to provide a clock reference for the other circuits inside the first chip 1. The hard-wired interface 107 has an ST _ PRO pin and an ST _ OF pin. The hard wire configuration port 101 has a RIT interface, an ALG _ EN pin, and a SET _ STS pin. Therefore, the algorithm control circuit 6 in the first chip 1 acquires effective information transmitted by the hard wire interface, the hard wire configuration port, the bus configuration port and the TWI port, generates an output signal after internal algorithm operation, and outputs the output signal to the second chip 2 through the TWI port to realize drive control of the second chip 2.
The second chip 2 is provided with: the OSC circuit 201, the parameter configuration circuit 202, the enabling configuration circuit 203, the state telemetry circuit 204, the voltage conversion circuit 205, the ADC circuit 206, the state coding circuit 207 and the MOS tube driving circuit 208. The OSC circuit 201 is used to generate a high frequency signal and a clock square wave signal, and is itself an oscillation circuit, the generated high frequency signal is used to implement an isolated DC-DC voltage conversion control signal inside the second chip 2, and the output one path of clock square wave with high stability is used to provide a clock source for the first chip 1. The parameter configuration circuit 202 is configured to receive and output configurable parameters, and output the configurable parameters to the signal isolation circuit 209 after internal processing by receiving the configurable parameters transmitted from the TWI interface 210, so as to finally implement isolation configuration of the key parameters. The enabling configuration circuit 203 is configured to receive an enabling or disabling command and perform function activation or disabling, and is used as enabling or disabling control of the function circuit, specifically, the enabling or disabling command transmitted from the TWI interface 210 is received and internally processed and then output to the signal isolation circuit 209, so as to finally implement function activation or disabling. The state telemetry circuit 204 is used for telemetry of states of a digital signal and an analog signal, wherein the digital signal includes a switch state, a protection state, a configuration bit, a working mode, and the like, and the analog signal is a current value acquired by the power loop 3. The voltage conversion circuit 205(Rectifier) is used for performing secondary conversion on the input voltage to form a multi-path voltage, so that the isolated voltage input from the power supply is subjected to secondary conversion to form a multi-path voltage of ± 12V, +5V, +3.3V, +1.8V, and the multi-path voltage is used for normally supplying power to other circuits in the second chip 2. The ADC circuit 206 is configured to collect a sampling voltage of the power loop 3 and convert the sampling voltage into a digital signal, specifically, collect a mV-level voltage signal on the sampling resistor 302, and convert the mV-level voltage signal into a digital signal for isolated transmission after analog-to-digital conversion. The state coding circuit 207 is configured to perform state coding on the digital signal and output the digital signal, specifically, perform state coding on the digital signal acquired and converted by the ADC, and transmit the digital signal to the signal isolation circuit 209 to implement isolated transmission of the analog signal. The MOS transistor driving circuit 208 is used for realizing driving control of the power loop MOSFET.
The signal isolation circuit 209 is used for receiving the signals output by the parameter configuration circuit 202, the enable configuration circuit 203 and the state coding circuit 207 and performing high-frequency processing on the signals. The signal isolation circuit 209 includes a modulation and demodulation circuit 2091 and an on-chip transformer 2092, and the on-chip transformer 2092 is integrated on the second chip 2. The signal isolation circuit 209 modulates and demodulates the current flowing between the drain and the source of the controlled MOSFET and an externally acquired analog voltage signal in a magnetic isolation manner to achieve magnetic isolation output, and performs high-frequency processing on the signal to achieve isolation and conversion of the signal and energy. The on-chip transformer 2092 is directly re-integrated on the chip using a coreless transformer technology, thereby minimizing the size of the device and improving stability and reliability.
In the present invention, the device further reserves a hard-line instruction input mode configuration pin PULSE _ EN (located ON the hard-line configuration port) and an ON/OFF instruction input pin ON/OFF _ H (located ON the hard-line interface) ON the first chip 1, which are three pins for hard-line instruction control, and the specific configuration mode is as shown in table 1 below:
TABLE 1 Command control mode
The bus configuration port 102 adopts an SPI standard serial interface mode, and has a clock input pin SCLK, two bidirectional data input and output pins MISO, MOSI, and a chip select signal control pin CS. The clock input pin SCLK and the bidirectional data input and output pins MISO and MOSI are shared pins, output is performed in an open-drain mode, and parallel control of 256 products can be supported.
In the burst mode, hard-wired burst commands are valid simultaneously with software commands, with software commands being prioritized in case of conflict. In the level command mode, one of the hard-line level command and the software command is active (i.e., only one of them is selected).
The device has a protection function, a state monitoring function and a mode control function, and specifically comprises the following steps:
the protection functions include an overload protection function and a short-circuit protection function. The overload protection function includes current limiting protection and overcurrent protection. The current-limiting protection adopts a closed-loop regulation mode, and when the integrated controller is externally connected with an MOSFET (metal oxide semiconductor field effect transistor) for testing, when an external short circuit occurs, the closed-loop control inside the integrated controller is realized. Over-current protection is I2And t, an inverse time limit protection characteristic, namely, turning off an external MOSFET after the protection time is up, and realizing mode selection and related parameter configuration through a bus configuration port 102 or a hard line configuration port 101. The short-circuit protection function is that when the external overload condition reaches the short-circuit protection point set by the short-circuit protection, the short-circuit protection circuit turns off the external MOSFET in the appointed short-circuit protection time, and the external MOSFET is actually switched off through the bus configuration port 102 or the hard line configuration port 101In the present parameter configuration, the state ST _ PRO pin indicates after the protection action is performed, and the state can be queried through the bus configuration port 102.
The state monitoring function comprises a hard line INT indication and a bus state output, after protection action occurs, the state indication is output through an interrupt output pin INT, state information is written into a register corresponding to the functional circuit, and the state can be inquired through an SPI bus interface.
The mode control function includes a delay off control mode, a repetitive overload control mode, and a foldback control mode, all of which are selected to be turned on or not through the SPI bus configuration port 102. When the time delay turn-off control mode is gated, timing is started from the command turning-on, and when the MOSFET turning-on time reaches the set timing time, the MOSFET is turned off. When the repeated overload control mode is gated, the MOSFET automatically turns on again when the duration of the overload protection is up to the re-triggering time setting value after the overload protection is turned off. When the foldback control mode is gated, the MOSFET is not turned off after the overload protection time is up, the MOSFET working mode is converted into a closed-loop regulation mode, and the current is continuously kept according to the set foldback current-limiting point.
Wherein, the foldback current limiting point ILIMThe calculation formula of (a) is as follows:
wherein, VDSIs the voltage between the drain and source of the MOSFET, Rsense is the resistance of the sampling resistor 302.
I2And (3) carrying out protection control on the t inverse time limit protection algorithm according to the following formula:
wherein, K. M, Ie、IpAll the parameters can be configured through an RIT or a bus unit, t is algorithm protection time, K is protection characteristic type (or called proportionality coefficient), the value is constant, M is setting coefficient, IeTo ratedCurrent value, IpAnd I is the current obtained by sampling, and is the multiple of the protection current and the rated current.
The above description is only one embodiment of the present invention, and is not intended to limit the present invention, and it is apparent to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The power supply and distribution protection device for the solid-state electronic switch comprises a first chip (1), a second chip (2) and a power loop (3), and is characterized in that a hard wire configuration port (101), a bus configuration port (102) and an algorithm control circuit (103) are arranged in the first chip (1), wherein the hard wire configuration port (101) and the bus configuration port (102) are respectively used for receiving an external hard wire configuration signal and a bus configuration signal and transmitting the external hard wire configuration signal and the bus configuration signal to the algorithm control circuit (103) so as to configure the working mode and parameters of the device.
2. The device according to claim 1, characterized in that the first chip (1) further comprises:
a power supply circuit (104) for supplying power to the apparatus;
-a PLL circuit (105) for receiving an input clock signal and providing a clock reference for the first chip (1);
a hard-wired interface (107) having an ST _ PRO pin and an ST _ OF pin;
the hardwire configuration port (101) has a RIT interface, an ALG _ EN pin, and a SET _ STS pin.
3. The device according to claim 1, characterized in that the second chip (2) has provided therein:
an OSC circuit (201) for generating a high frequency signal and a clock square wave signal;
a parameter configuration circuit (202) for receiving and outputting configurable parameters;
an enabling configuration circuit (203) for receiving an enabling or disabling command and performing functional activation or deactivation;
a state telemetry circuit (204) for telemetry of the states of the digital and analog signals;
a voltage conversion circuit (205) for converting an input voltage twice to form a plurality of paths of voltages;
an ADC circuit (206) for collecting the sampling voltage of the power loop (3) and converting the sampling voltage into a digital signal;
a state coding circuit (207) for state coding and outputting the digital signal;
the MOS tube driving circuit (208) is used for driving and controlling the power loop (3);
the digital signal comprises a switch state, a protection state, a configuration bit and a working mode, and the analog signal is a current value acquired by the power loop (3).
4. The device according to claim 3, characterized in that the second chip (2) further comprises:
and the signal isolation circuit (209) is used for receiving the signals output by the parameter configuration circuit (202), the enabling configuration circuit (203) and the state coding circuit (207) and carrying out high-frequency processing on the signals.
5. The apparatus of claim 4, wherein the signal isolation circuit (209) comprises a modem circuit (2091) and an on-chip transformer (2092), the on-chip transformer (2092) being integrated on the second chip (2);
the signal isolation circuit (209) modulates and demodulates the current flowing between the drain electrode and the source electrode of the controlled object MOSFET and a path of externally acquired voltage analog quantity signal by adopting a magnetic isolation mode so as to realize magnetic isolation output.
6. The arrangement according to claim 1, characterized in that the power loop (3) comprises:
a power MOSFET (301) for controlling the switching on and off of the power loop (3);
a sampling resistor (302) for acquiring a current signal of the power loop (3).
7. The apparatus according to claim 1, wherein a master and a slave TWI interface (106,210) are further provided in the first chip (1) and the second chip (2), respectively.
8. The apparatus of claim 1, further comprising a hardwired command input mode configuration pin and an on/off command input pin;
the bus configuration port (102) adopts an SPI standard serial interface mode and is provided with a clock input pin, two bidirectional data input and output pins and a chip selection signal control pin;
the clock input pin and the bidirectional data input and output pin are shared pins, output is performed in an open-drain mode, and parallel control of 256 products can be supported.
9. The apparatus of claim 1, wherein in burst mode, hard-wired burst commands are active simultaneously with software commands, with software commands prioritized in case of conflict;
in the level command mode, one of a hard-wired level command and a software command is active.
10. The apparatus according to claim 1, wherein the apparatus has a protection function, a state monitoring function, and a mode control function;
the protection function comprises an overload protection function and a short-circuit protection function;
the overload protection function comprises current limiting protection and overcurrent protection;
the current-limiting protection adopts a closed-loop regulation mode, and when an external MOSFET (metal oxide semiconductor field effect transistor) of the integrated controller is tested and an external short circuit occurs outside, the closed-loop control inside the integrated controller is realized;
the over-current protection is I2t inverse time limit protection, external MOSFET is turned off after the protection time is up, and mode selection and correlation are realized through a bus configuration port (102) or a hard line configuration port (101)Parameter configuration;
the short-circuit protection function is that when the external overload condition reaches a short-circuit protection point set by short-circuit protection, the short-circuit protection circuit turns off an external MOSFET in the appointed short-circuit protection time, parameter configuration is realized through a bus configuration port (102) or a hard line configuration port (101), a state ST _ PRO pin indicates after the protection action is executed, and meanwhile, the state can be inquired through the bus configuration port (102);
the state monitoring function comprises a hard line INT indication and a bus state output, after protection action occurs, the state indication is output through an interruption output pin INT, state information is written into a register corresponding to the functional circuit, and the state can be inquired through an SPI bus interface;
the mode control function comprises a time delay turn-off control mode, a repeated overload control mode and a turn-back control mode, and whether the mode is started or not is selected through an SPI bus configuration port (102);
when the time delay turn-off control mode is gated, timing is started from the instruction turning-on, and when the turning-on time of the MOSFET reaches the set timing time, the MOSFET is turned off;
when the repeated overload control mode is gated, the MOSFET automatically turns on again when the duration time reaches the re-triggering time set value after the overload protection is disconnected;
when the foldback control mode is gated, the MOSFET is not turned off after the overload protection time is up, the MOSFET working mode is converted into a closed-loop regulation mode, and the current is continuously maintained according to the set foldback current-limiting point;
the calculation formula of the foldback current limiting point is as follows:
wherein, VDSIs the voltage between the drain and the source of the MOSFET, Rsense is the resistance of the sampling resistor (302);
I2and (3) carrying out protection control on the t inverse time limit protection algorithm according to the following formula:
wherein, K. M, Ie、IpAll the parameters are configurable parameters and can be configured through an RIT or a bus unit;
t is algorithm protection time, K is protection characteristic type, M is setting coefficient, IeTo rated current value, IpAnd I is the current obtained by sampling, and is the multiple of the protection current and the rated current.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111400363.0A CN114172125A (en) | 2021-11-24 | 2021-11-24 | Power supply and distribution protection device for solid electronic switch |
| PCT/CN2022/127421 WO2023093425A1 (en) | 2021-11-24 | 2022-10-25 | Power supply and distribution protection apparatus for solid-state electronic switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111400363.0A CN114172125A (en) | 2021-11-24 | 2021-11-24 | Power supply and distribution protection device for solid electronic switch |
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| Publication Number | Publication Date |
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| CN114172125A true CN114172125A (en) | 2022-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111400363.0A Pending CN114172125A (en) | 2021-11-24 | 2021-11-24 | Power supply and distribution protection device for solid electronic switch |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114172125A (en) |
| WO (1) | WO2023093425A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023093425A1 (en) * | 2021-11-24 | 2023-06-01 | 北京卫星制造厂有限公司 | Power supply and distribution protection apparatus for solid-state electronic switch |
| WO2023093426A1 (en) * | 2021-11-24 | 2023-06-01 | 北京卫星制造厂有限公司 | Solid-state power controller |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116909201B (en) * | 2023-09-13 | 2023-11-24 | 南京德克威尔自动化有限公司 | Bus type IO acquisition and control expansion method, system and computer storage medium |
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Also Published As
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| WO2023093425A1 (en) | 2023-06-01 |
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