CN114171371A - Preparation method of wafer sample for manufacturing chip on board and chip on board manufacturing method - Google Patents
Preparation method of wafer sample for manufacturing chip on board and chip on board manufacturing method Download PDFInfo
- Publication number
- CN114171371A CN114171371A CN202111465475.4A CN202111465475A CN114171371A CN 114171371 A CN114171371 A CN 114171371A CN 202111465475 A CN202111465475 A CN 202111465475A CN 114171371 A CN114171371 A CN 114171371A
- Authority
- CN
- China
- Prior art keywords
- wafer
- sample
- target wafer
- board
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2644—Adaptations of individual semiconductor devices to facilitate the testing thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a preparation method of a wafer sample for manufacturing a chip on board and a method for manufacturing the chip on board, wherein the preparation method of the wafer sample for manufacturing the chip on board comprises the following steps: determining a target wafer in the polycrystalline wafer laminated sample, wherein the target wafer is a non-bottommost wafer and is directly connected to the substrate through a gold wire, and the gold wire is provided with a first gold ball at a contact part with the substrate; removing the substrate until the solder mask layer at the bottom of the lowest wafer in the plurality of wafers is exposed; measuring a first distance between a first gold ball on a gold wire connecting the target wafer to the substrate and the edge of the target wafer in the horizontal direction; determining a grinding area for removing one or more wafers below the target wafer according to the first spacing; and grinding and removing one or more wafers below the target wafer based on the determined grinding area to obtain a wafer sample for manufacturing the chips on the board. The wafer sample for manufacturing the chip on board prepared by the invention is beneficial to wire bonding operation.
Description
Technical Field
The invention mainly relates to the field of semiconductor testing, in particular to a preparation method of a wafer sample for manufacturing a chip on board and a method for manufacturing the chip on board.
Background
When failure analysis is carried out on the polycrystalline wafer stacked sample, if a certain wafer (Die) is positioned to fail, the back surface of the wafer needs to be processed until the back surface of the target wafer is exposed, and then a Chip On Board (COB) is manufactured to carry out testing or failure position detection operation. The wire bonding operation on the target wafer is a critical step, which affects whether the detection or test operation can be performed smoothly and effectively.
Disclosure of Invention
The invention aims to provide a preparation method of a wafer sample for manufacturing a chip on board and a method for manufacturing the chip on board.
In order to solve the above technical problem, the present invention provides a method for preparing a wafer sample for chip on board fabrication, comprising the following steps: determining a target wafer in a multi-wafer stacked sample, wherein the multi-wafer stacked sample comprises a substrate and a plurality of wafers, the target wafer is a non-bottommost wafer and is directly connected to the substrate through a gold wire, and the gold wire is provided with a first gold ball at a contact part with the substrate; removing the substrate until the solder mask layer at the bottom of the lowest wafer in the plurality of wafers is exposed; measuring a first distance between a first gold ball on a gold wire connecting the target wafer to the substrate and the edge of the target wafer in the horizontal direction; determining a grinding area for removing one or more wafers below the target wafer according to the first distance in the horizontal direction; and grinding and removing one or more wafers below the target wafer based on the determined grinding area to obtain the wafer sample for manufacturing the chips on the board.
In an embodiment of the present invention, the removing, by polishing, one or more wafers below the target wafer based on the determined polishing area to obtain the wafer sample for manufacturing chips on board includes: and grinding and removing one or more wafers below the target wafer until the wafer connecting film at the bottom of the target wafer is exposed.
In an embodiment of the invention, removing the substrate until the solder mask layer exposing the bottom of the lowest die of the plurality of dies includes: and removing the substrate by a chemical etching mode.
In an embodiment of the present invention, measuring a first spacing in a horizontal direction between a first gold ball on a gold wire connecting the target wafer to the substrate and an edge of the target wafer comprises: and determining the horizontal direction distance between a first gold ball on a gold wire of the target wafer connected to the substrate and the edge of the target wafer through a distance scanning device.
In an embodiment of the present invention, determining a polishing area for removing one or more wafers below the target wafer according to the horizontal direction spacing includes: the distance from the edge of the grinding area close to the first gold ball to the edge of the target wafer is smaller than the first interval.
In an embodiment of the invention, after one or more wafers below the target wafer are removed by polishing based on the determined polishing area, the bottom of the target wafer is secondarily polished to perform a failure position detection operation.
In an embodiment of the present invention, determining a target wafer in a multi-wafer stack sample comprises: performing electrical failure analysis on the multi-wafer stacked sample to determine a failed wafer; and determining the failed wafer as the target wafer.
In an embodiment of the invention, the multi-wafer stacked sample includes a three-dimensional memory.
In an embodiment of the present invention, the chemical etching includes etching with dilute nitric acid.
The invention also provides a method for manufacturing a chip on board, which comprises the following steps: in a polycrystalline wafer laminated sample, a wafer sample for manufacturing a chip on board is obtained by the method of any one of the preceding claims, wherein the wafer sample comprises a target wafer, and a gold wire comprising a first gold ball is connected to the target wafer; and carrying out routing operation on the first gold ball of the gold wire, and connecting or extending the gold wire to manufacture a chip on board.
Compared with the prior art, the invention has the following advantages: according to the technical scheme, compared with the direct grinding and removal of one or more wafers below the target wafer, the gold ball at the tail end of the gold wire connecting the target wafer to the substrate in the multi-wafer stacked sample can be completely reserved, so that the gold wire is connected or prolonged when chips are formed on the substrate in the follow-up wafer sample manufacturing process, and the wafer testing efficiency is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the principle of the application. In the drawings:
fig. 1 is a flowchart of a method for preparing a wafer sample for fabricating chips on board according to an embodiment of the present application.
Fig. 2 to 9 are process schematic diagrams of a preparation method of a wafer sample for fabricating a chip on board according to the present application, wherein fig. 6 to 8 correspond to different embodiments.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.
Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.
Embodiments of the present application describe a method of preparing a wafer sample for fabricating chips on board and a method of fabricating chips on board.
Fig. 1 is a flowchart of a method for preparing a wafer sample for fabricating chips on board according to an embodiment of the present application.
As shown in fig. 1, a method for preparing a wafer sample for making chip-on-board includes, step 101, determining a target wafer in a multi-wafer stacked sample, the multi-wafer stacked sample including a substrate and a plurality of wafers, the target wafer being a non-lowermost wafer and being directly connected to the substrate by gold wires having first gold balls at contact portions with the substrate; 102, removing the substrate until the solder mask layer at the bottom of the wafer at the lowest position in the plurality of wafers is exposed; step 103, measuring a first distance between a first gold ball on a gold wire connecting the target wafer to the substrate and the edge of the target wafer in the horizontal direction; 104, determining a grinding area for removing one or more wafers below the target wafer according to the first interval in the horizontal direction; and 105, grinding and removing one or more wafers below the target wafer based on the determined grinding area to obtain the wafer sample for manufacturing the chips on the board.
Specifically, in step 101, a target wafer is determined in a multi-wafer stacked sample, the multi-wafer stacked sample including a substrate and a plurality of wafers, the target wafer being a non-lowermost wafer and being directly connected to the substrate by gold wires having first gold balls at contact portions with the substrate.
As illustrated in fig. 2, a multi-wafer stacked sample 200 includes a substrate 201 and a plurality of wafers, wafers 202, 203, 204, and 205 being shown in fig. 2. In some embodiments, solder ball structures 208 are also included under the substrate.
In fig. 2, wafers 202, 203, 204, and 205 are connected directly or indirectly to substrate 201 by gold wires 210, 211, 212, and 213.
In some embodiments, determining a target wafer in a polycrystallme wafer stack sample comprises: step 201, performing electrical failure analysis on the multi-wafer stacked sample to determine a failed wafer; step 202, determining the failed wafer as the target wafer. In some embodiments, the multi-wafer stacked sample includes a three-dimensional memory.
As illustrated in fig. 3, a failed wafer 204 is determined, for example, by electrical failure analysis, and the failed wafer 204 is a target wafer, as indicated by the dashed box in fig. 3. The target wafer 204 is a non-lowermost wafer and is directly connected to the substrate 201 by gold wires 212. The contact portion between the gold wire 212 and the substrate 201 (also referred to as the end of gold wire) has a first gold ball 220.
In some embodiments, the poly-wafer laminated sample 200 is provided with an electromagnetic shielding (EMC) cover (not shown).
After determining a target wafer which is not a lowermost wafer and is directly connected to the substrate by gold wires having first gold balls at contact portions with the substrate in step 101, removing the substrate until a solder resist (solder mask) at the bottom of the lowermost wafer among the plurality of wafers is exposed, which may also be referred to as a green oil layer, insulating the lowermost wafer from the substrate in step 102.
In some embodiments, removing the substrate to expose the solder mask layer on the bottom of the lowermost wafer of the plurality of wafers comprises: and removing the substrate by a chemical etching mode. The chemical etching means includes, for example, etching with dilute nitric acid. In some embodiments, the method further comprises removing the solder ball structure under the substrate by grinding.
The polycrystalline wafer stack sample 200 after substrate removal is illustrated in fig. 4.
Next, in step 103, a first spacing in a horizontal direction between a first gold ball on a gold wire connecting the target wafer to the substrate and an edge of the target wafer is measured.
As shown in fig. 5, a first spacing, such as the first spacing L indicated in fig. 5, of the first gold balls 220 on the gold wires 212 connecting the target wafer 204 to the substrate (which is now removed) from the edge of the target wafer 204 in the horizontal direction is measured. The first pitch may be a distance between an edge of the first gold ball near one side of the target wafer and an edge of the target wafer.
In some embodiments, measuring a first spacing in a horizontal direction between a first gold ball on a gold wire connecting the target wafer to the substrate and an edge of the target wafer comprises: and determining the horizontal direction distance between a first gold ball on a gold wire of the target wafer connected to the substrate and the edge of the target wafer through a distance scanning device. Distance scanning devices determine distance, for example, by emitting X-ray signals and receiving return signals.
In step 104, a grinding area for removing one or more wafers below the target wafer is determined according to the first spacing in the horizontal direction.
As illustrated in fig. 6, a polishing area, such as area 230, is illustrated when one or more wafers below the target wafer are removed.
In some embodiments, determining a polishing area for removal of one or more wafers below the target wafer based on the horizontal direction spacing comprises: the distance from the edge of the grinding area close to the first gold ball to the edge of the target wafer is smaller than the first interval.
Referring to fig. 6, the distance S that the edge of the polishing region near the first gold ball exceeds the edge of the target wafer is less than the first pitch L.
Fig. 7 is a diagrammatic representation of another embodiment of an abrasive region. In fig. 7, the distance S of the polishing region 231 from the edge of the first gold ball to the edge of the target wafer 204 is, for example, 0 (or close to 0), which also satisfies that the distance S from the edge of the polishing region to the edge of the first gold ball to the edge of the target wafer is smaller than the first pitch L.
Fig. 8 is a diagrammatic representation of another embodiment of an abrasive region. In fig. 8, the polishing region 232 is close to the edge of the first gold ball and does not exceed the edge of the target wafer 204, and at this time, if the distance S' from the edge of the polishing region close to the first gold ball to the edge of the target wafer is converted to the aforementioned distance S, it can also be understood that the distance S from the edge of the polishing region close to the first gold ball to the edge of the target wafer exceeds the edge of the target wafer is a negative value, so that the distance S from the edge of the polishing region close to the first gold ball to the edge of the target wafer exceeds the edge of the target wafer and is still smaller than the first distance L.
In step 105, one or more wafers below the target wafer are removed by grinding based on the determined grinding area, and the wafer sample for manufacturing the chip on board is obtained.
Grinding and removing one or more wafers below the target wafer based on the determined grinding area, and obtaining the wafer sample for manufacturing the chip on board comprises the following steps: and grinding and removing one or more wafers below the target wafer until the wafer connecting film at the bottom of the target wafer is exposed.
Fig. 9 is a schematic diagram of the wafer sample 260 for manufacturing chips on board after one or more wafers under the target wafer are removed by polishing based on the determined polishing area.
In fig. 9, a Die Attached Film (DAF) on the bottom of the target wafer is indicated by reference numeral 240. The grinding operation is carried out, for example, by means of a grinding instrument.
In some embodiments, the method for preparing a wafer sample for fabricating chips on board further comprises, after removing one or more wafers below the target wafer by grinding based on the determined grinding area, performing secondary grinding (also referred to as a trimming operation) on the bottom of the target wafer to perform a failure location detection operation (also referred to as a point-grabbing operation).
The application also provides a method for manufacturing a chip on board, which comprises the step 301 of obtaining a wafer sample for manufacturing the chip on board by the method in a polycrystalline wafer stacked package sample, wherein the wafer sample comprises a target wafer, and the target wafer is connected with a gold wire comprising a first gold ball; step 302, performing a wire bonding operation On the first gold ball of the gold wire, and connecting or extending the gold wire to manufacture a Chip On Board (COB).
According to the technical scheme, compared with the direct grinding and removal of one or more wafers below the target wafer, the gold ball at the tail end of the gold wire connecting the target wafer to the substrate in the multi-wafer stacked sample can be completely reserved, so that the gold wire can be connected or prolonged when the chip on the substrate is formed by subsequently manufacturing the wafer sample, and the gold ball at the tail end of the gold ball is completely reserved, so that the routing operation can be performed on the gold ball.
If one or more wafers below the target wafer are directly ground and removed, the gold balls are also easily ground and removed, so that the routing operation can be continued only at the head section of the gold wire, and the gold wire can be connected or prolonged. The diameter of the gold thread is greatly smaller than that of the gold ball, the operation can obviously increase the difficulty of routing operation, and if one routing operation is unsuccessful, the routed gold thread needs to be pulled out and then routed again, but the existing gold thread before the routing operation is easily pulled out in the routing process, so that the subsequent routing operation cannot be performed, the wafer sample processing fails, and the wafer testing efficiency is reduced.
Therefore, according to the preparation method of the wafer sample for manufacturing the chip on board and the method for manufacturing the chip on board, when the wafer sample for manufacturing the chip on board is prepared, the gold balls at the tail ends of the gold wires for connecting the target wafer to the substrate in the multi-wafer stacked sample are reserved, so that the subsequent routing operation is simple and easy, the routing operation difficulty is reduced, and the wafer testing efficiency is improved.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Although the present application has been described with reference to the present specific embodiments, it will be recognized by those skilled in the art that the foregoing embodiments are merely illustrative of the present application and that various changes and substitutions of equivalents may be made without departing from the spirit of the application, and therefore, it is intended that all changes and modifications to the above-described embodiments that come within the spirit of the application fall within the scope of the claims of the application.
Claims (10)
1. A method of preparing a wafer sample for making chips on board comprising the steps of:
determining a target wafer in a multi-wafer stacked sample, wherein the multi-wafer stacked sample comprises a substrate and a plurality of wafers, the target wafer is a non-bottommost wafer and is directly connected to the substrate through a gold wire, and the gold wire is provided with a first gold ball at a contact part with the substrate;
removing the substrate until the solder mask layer at the bottom of the lowest wafer in the plurality of wafers is exposed;
measuring a first distance between a first gold ball on a gold wire connecting the target wafer to the substrate and the edge of the target wafer in the horizontal direction;
determining a grinding area for removing one or more wafers below the target wafer according to the first distance in the horizontal direction;
and grinding and removing one or more wafers below the target wafer based on the determined grinding area to obtain the wafer sample for manufacturing the chips on the board.
2. The method for preparing a wafer sample for making chips on board according to claim 1, wherein the step of removing one or more wafers below the target wafer by grinding based on the determined grinding area comprises:
and grinding and removing one or more wafers below the target wafer until the wafer connecting film at the bottom of the target wafer is exposed.
3. The method for preparing a wafer sample for making chip on board as claimed in claim 1, wherein removing the substrate to expose the solder mask layer of the bottom wafer bottom portion of the plurality of wafers comprises: and removing the substrate by a chemical etching mode.
4. The method of claim 1, wherein measuring a first spacing in a horizontal direction between a first gold ball on a gold wire connecting the target wafer to the substrate and an edge of the target wafer comprises:
and determining the horizontal direction distance between a first gold ball on a gold wire of the target wafer connected to the substrate and the edge of the target wafer through a distance scanning device.
5. The method for preparing a wafer sample for chip on board fabrication as claimed in claim 1, wherein determining a grinding area for removing one or more wafers below the target wafer according to the horizontal direction spacing comprises:
the distance from the edge of the grinding area close to the first gold ball to the edge of the target wafer is smaller than the first interval.
6. The method for preparing a wafer sample for chip on board fabrication as claimed in claim 1, further comprising, after removing one or more wafers under the target wafer by grinding based on the determined grinding area, performing secondary grinding on the bottom of the target wafer for failure location detection operation.
7. The method for preparing a wafer sample for making chip on board according to claim 1, wherein the determining a target wafer in the multi-wafer stack sample comprises:
performing electrical failure analysis on the multi-wafer stacked sample to determine a failed wafer;
and determining the failed wafer as the target wafer.
8. The method of claim 1, wherein the multi-wafer stacked sample comprises a three-dimensional memory.
9. The method for preparing a wafer sample for making chip on board according to claim 3, wherein said chemical etching means comprises etching with dilute nitric acid.
10. A method of fabricating a chip-on-board comprising the steps of:
obtaining a wafer sample for manufacturing chips on a board by the method of any one of claims 1 to 9 in a multi-wafer stacked sample, wherein the wafer sample comprises a target wafer, and the target wafer is connected with gold wires comprising first gold balls;
and carrying out routing operation on the first gold ball of the gold wire, and connecting or extending the gold wire to manufacture a chip on board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111465475.4A CN114171371A (en) | 2021-12-03 | 2021-12-03 | Preparation method of wafer sample for manufacturing chip on board and chip on board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111465475.4A CN114171371A (en) | 2021-12-03 | 2021-12-03 | Preparation method of wafer sample for manufacturing chip on board and chip on board manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114171371A true CN114171371A (en) | 2022-03-11 |
Family
ID=80482642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111465475.4A Pending CN114171371A (en) | 2021-12-03 | 2021-12-03 | Preparation method of wafer sample for manufacturing chip on board and chip on board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114171371A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114800107A (en) * | 2022-06-27 | 2022-07-29 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Chip layer removal adjusting device and sample preparation method |
-
2021
- 2021-12-03 CN CN202111465475.4A patent/CN114171371A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114800107A (en) * | 2022-06-27 | 2022-07-29 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Chip layer removal adjusting device and sample preparation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7582953B2 (en) | Package structure with leadframe on offset chip-stacked structure | |
| US7488620B2 (en) | Method of fabricating leadframe based flash memory cards including singulation by straight line cuts | |
| JP4753170B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20090001574A1 (en) | Multi-chips Stacked package structure | |
| US20090278243A1 (en) | Stacked type chip package structure and method for fabricating the same | |
| CN114171371A (en) | Preparation method of wafer sample for manufacturing chip on board and chip on board manufacturing method | |
| US10163832B1 (en) | Integrated fan-out package, redistribution circuit structure, and method of fabricating the same | |
| US20130320463A1 (en) | Package structure having mems element and fabrication method thereof | |
| US9615451B2 (en) | Porous alumina templates for electronic packages | |
| JP2008219029A (en) | Semiconductor package, multi-chip package and its manufacturing process | |
| US8785254B2 (en) | Method of manufacturing high-capacity semiconductor package | |
| US6815806B1 (en) | Asymmetric partially-etched leads for finer pitch semiconductor chip package | |
| US7224829B2 (en) | Bonding pattern discrimination method, bonding pattern discrimination device and bonding pattern discrimination program | |
| KR20060025555A (en) | Stackable integrated circuit package and method therefor | |
| DE102017217595B4 (en) | Method of producing semiconductor devices with a general purpose non-linear semiconductor package production line | |
| EP2672511B1 (en) | 3d stacked multichip module and method of fabrication | |
| KR100608611B1 (en) | Wafer level chip scale package using via hole and manufacturing method for the same | |
| US20220375901A1 (en) | Semiconductor device and method of manufacturing a semiconductor device | |
| US6998720B2 (en) | Semiconductor package device and method for fabricating the same | |
| US20170162479A1 (en) | Semiconductor device with frame having arms and related methods | |
| JP2010087403A (en) | Semiconductor device | |
| US20080164601A1 (en) | Chip package structure | |
| KR101332858B1 (en) | Device for array observation of multi-stack die | |
| US9013043B2 (en) | Semiconductor element applicable to optical products | |
| JP2003179193A (en) | Lead frame and manufacturing method thereof, resin- sealed semiconductor device and manufacturing and inspection methods thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |