CN114155815A

CN114155815A - Pixel circuit, pixel driving method and display device

Info

Publication number: CN114155815A
Application number: CN202210071308.XA
Authority: CN
Inventors: 刘伟星; 王铁石; 徐智强; 张春芳; 滕万鹏; 郭凯; 周飞虎
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-01-21
Filing date: 2022-01-21
Publication date: 2022-03-08
Anticipated expiration: 2042-01-21
Also published as: CN114155815B

Abstract

The invention provides a pixel circuit, a pixel driving method and a display device. The pixel circuit comprises a driving circuit, a first light-emitting control circuit, a second light-emitting control circuit, a first initialization circuit and a light-emitting element; the first light-emitting control circuit controls the connection or disconnection between the first voltage end and the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the connection or disconnection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the first light-emitting control signal; the first initialization circuit is controlled to provide a first initial voltage to the first pole of the light-emitting element under the control of the second light-emitting control signal; the driving circuit is used for generating driving current under the control of the potential of the control end of the driving circuit; the second pole of the light-emitting element is electrically connected with the second voltage end. The invention can reduce the display peak current.

Description

Pixel circuit, pixel driving method and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a pixel circuit, a pixel driving method, and a display device.

Background

At present, more and more display products are added with the function of frequency conversion design. When the display product displays the static pictures, the screen refresh rate can be reduced, and the power consumption is saved. However, when the conventional low-frequency pixel driving circuit works, a phenomenon of large peak current caused by instant jump of the potential of the anode of the organic light emitting diode occurs.

Disclosure of Invention

The invention mainly aims to provide a pixel circuit, a pixel driving method and a display device, which solve the problem of large display peak current in the prior art.

In order to achieve the above object, an embodiment of the present invention provides a pixel circuit, including a driving circuit, a first light-emission control circuit, a second light-emission control circuit, a first initialization circuit, and a light-emitting element;

the first light-emitting control circuit is respectively electrically connected with a first light-emitting control line, a first voltage end and a first end of the driving circuit and is used for controlling the connection or disconnection between the first voltage end and the first end of the driving circuit under the control of a first light-emitting control signal provided by the first light-emitting control line;

the second light-emitting control circuit is respectively connected with the first light-emitting control line, the second end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the connection or disconnection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the first light-emitting control signal;

the first initialization circuit is respectively electrically connected with a second light-emitting control line, a first initial voltage end and a first pole of the light-emitting element, and is used for controlling the first initial voltage end to provide a first initial voltage to the first pole of the light-emitting element under the control of a second light-emitting control signal provided by the second light-emitting control line;

the driving circuit is used for generating a driving current flowing through a first end of the driving circuit and a second end of the driving circuit under the control of the potential of a control end of the driving circuit;

and the second pole of the light-emitting element is electrically connected with the second voltage end.

Optionally, a first light-emitting control signal provided by the first light-emitting control line is different from a second light-emitting control signal provided by the second light-emitting control line; or, the first light-emitting control signal provided by the first light-emitting control line is the same as the second light-emitting control signal provided by the second light-emitting control line.

Optionally, the pixel circuit further includes an on-off control circuit;

the on-off control circuit is respectively electrically connected with the first light-emitting control line, the second pole of the light-emitting element and the second voltage end, and is used for controlling the connection or disconnection between the second pole of the light-emitting element and the second voltage end under the control of the first light-emitting control signal.

Optionally, the first light emission control circuit includes a first transistor, the second light emission control circuit includes a second transistor, the driving circuit includes a driving transistor, and the first initialization circuit includes a third transistor;

a control electrode of the first transistor is electrically connected with the first light-emitting control electrode, a first electrode of the first transistor is electrically connected with the first voltage end, and a second electrode of the first transistor is electrically connected with the first electrode of the driving transistor;

a control electrode of the second transistor is electrically connected to the first light-emitting control line, a first electrode of the second transistor is electrically connected to a second electrode of the driving transistor, and the second electrode of the second transistor is electrically connected to the first electrode of the light-emitting element;

a control electrode of the third transistor is electrically connected to the second light emission control line, a first electrode of the third transistor is electrically connected to the first initial voltage terminal, and a second electrode of the third transistor is electrically connected to the first electrode of the light emitting element.

Optionally, the on-off control circuit includes a fourth transistor;

a control electrode of the fourth transistor is electrically connected to the first light emitting control electrode, a first electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element, and a second electrode of the fourth transistor is electrically connected to a second voltage terminal.

Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a first tank circuit, a data writing circuit, a compensation control circuit, and a second initialization circuit;

the first energy storage circuit is electrically connected with the control end of the driving circuit and is used for storing electric energy;

the data writing circuit is respectively electrically connected with a first scanning line, a data line and a first end of the driving circuit and is used for writing a data voltage provided by the data line into the first end of the driving circuit under the control of a first scanning signal provided by the first scanning line;

the compensation control circuit is respectively electrically connected with the second scanning line, the control end of the driving circuit and the second end of the driving circuit, and is used for controlling the connection or disconnection between the control end of the driving circuit and the second end of the driving circuit under the control of a second scanning signal provided by the second scanning line;

the second initialization circuit is respectively electrically connected with a reset control line, a second initial voltage end and the control end of the driving circuit, and is used for writing a second initial voltage provided by the second initial voltage end into the control end of the driving circuit under the control of a reset control signal provided by the reset control line.

Optionally, the first tank circuit includes a first capacitor, the data writing circuit includes a fifth transistor, the compensation control circuit includes a sixth transistor, and the second initialization circuit includes a seventh transistor;

the first end of the first capacitor is electrically connected with the control end of the driving circuit, and the second end of the first capacitor is electrically connected with the first voltage end;

a control electrode of the fifth transistor is electrically connected with the first scan line, a first electrode of the fifth transistor is electrically connected with the data line, and a second electrode of the fifth transistor is electrically connected with the first end of the driving circuit;

a control electrode of the sixth transistor is electrically connected with the second scanning line, a first electrode of the sixth transistor is electrically connected with a control end of the driving circuit, and a second electrode of the sixth transistor is electrically connected with a second end of the driving circuit;

a control electrode of the seventh transistor is electrically connected to the reset control line, a first electrode of the seventh transistor is electrically connected to the control terminal of the driving circuit, and a second electrode of the seventh transistor is electrically connected to the second initial voltage terminal.

An embodiment of the present invention further provides a pixel driving method, which is applied to the pixel circuit, where the pixel driving method includes:

the first light-emitting control circuit controls the connection or disconnection between the first voltage end and the first end of the driving circuit under the control of the first light-emitting control signal;

the second light-emitting control circuit controls the connection or disconnection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the first light-emitting control signal;

the first initialization circuit controls a first initial voltage end to provide a first initial voltage to a first pole of the light-emitting element under the control of the second light-emitting control signal;

the driving circuit generates a driving current flowing through a first end of the driving circuit and a second end of the driving circuit under the control of the potential of a control end of the driving circuit.

Optionally, the first light-emitting control signal is different from the second light-emitting control signal; the display period comprises a light-emitting stage, a peak suppression stage and a reset stage which are arranged in sequence; the pixel driving method includes:

in the light-emitting stage, the first light-emitting control circuit controls the first voltage end to be communicated with the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the communication between the second end of the driving circuit and the first pole of the light-emitting element under the control of the first light-emitting control signal;

in the peak suppressing stage and the resetting stage, the first light-emitting control circuit controls the first voltage end and the first end of the driving circuit to be disconnected under the control of a first light-emitting control signal; the second light-emitting control circuit controls the second end of the driving circuit to be disconnected with the first pole of the light-emitting element under the control of the first light-emitting control signal;

in the reset phase, the first initialization circuit controls the first initial voltage end to provide the first initial voltage to the first pole of the light-emitting element under the control of the second light-emitting control signal.

Optionally, the pixel circuit further includes an on-off control circuit; the pixel driving method further includes:

in the light emitting stage, the on-off control circuit controls the second pole of the light emitting element to be communicated with the second voltage end under the control of the first light emitting control signal; the driving circuit drives the light-emitting element to emit light;

and in the peak suppression stage and the reset stage, the on-off control circuit controls the second pole of the light-emitting element to be disconnected with the second voltage end under the control of the first light-emitting control signal.

Optionally, the pixel circuit further includes an on-off control circuit; the first light emission control signal is the same as the second light emission control signal; the display period comprises a light-emitting stage and a reset stage which are arranged in sequence; the pixel driving method includes:

in the light-emitting stage, the first light-emitting control circuit controls the first voltage end to be communicated with the first end of the driving circuit under the control of the first light-emitting control signal; the second light-emitting control circuit controls the communication between the second end of the driving circuit and the first pole of the light-emitting element under the control of the first light-emitting control signal; the on-off control circuit controls the second pole of the light-emitting element to be communicated with the second voltage end under the control of the first light-emitting control signal; the driving circuit drives the light-emitting element to emit light;

in a reset phase, the first initialization circuit writes a first initial voltage provided by the first initial voltage end into a first pole of the light-emitting element under the control of the second light-emitting control signal; the on-off control circuit controls the second pole of the light-emitting element to be disconnected with the second voltage end under the control of the first light-emitting control signal.

The embodiment of the invention also provides a display device which comprises a plurality of rows and a plurality of columns of the pixel circuit.

Optionally, the display device according to at least one embodiment of the present invention further includes a plurality of rows of first light-emitting control lines, a plurality of rows of second light-emitting control lines, and a light-emitting control signal generating module; the light-emitting control signal generation module comprises a multi-row light-emitting control signal generation circuit;

the nth row light-emitting control signal generating circuit is respectively electrically connected with the nth row first light-emitting control line and the nth row second light-emitting control line and is used for providing the nth row first light-emitting control signal for the nth row first light-emitting control line and providing the nth row second light-emitting control signal for the nth row second light-emitting control line;

n is a positive integer.

Optionally, the nth row light-emitting control signal generating circuit includes a node control circuit, a first output circuit and a second output circuit;

the node control circuit is respectively electrically connected with a first node and a second node and is used for controlling the potential of the first node and the potential of the second node;

the control node control circuit is respectively electrically connected with the second node, the control node, the first clock signal end and the fourth voltage end, and is used for controlling the potential of the control node according to the first clock signal and the fourth voltage signal provided by the fourth voltage end under the control of the potential of the second node and the first clock signal provided by the first clock signal end;

the first output circuit is respectively electrically connected with the first node, the second node, the nth row second light-emitting control signal terminal, the third voltage terminal and the fourth voltage terminal, and is used for controlling generation and outputting an nth row second light-emitting control signal through the nth row second light-emitting control signal terminal under the control of the electric potential of the first node and the electric potential of the second node;

the second output circuit is respectively electrically connected with the nth row first light-emitting control signal end, the nth row second light-emitting control signal end, the first node, the third voltage end and the output clock signal end, and is used for controlling the communication between the nth row first light-emitting control signal end and the third voltage end under the control of the potential of the first node and controlling the communication between the nth row first light-emitting control signal end and the output clock signal end under the control of the nth row second light-emitting control signal.

Optionally, the first output circuit includes a first output transistor and a second output transistor, and the second output circuit includes a third output transistor and a fourth output transistor;

a control electrode of the first output transistor is electrically connected with the first node, a first electrode of the first output transistor is electrically connected with the third voltage end, and a second electrode of the first output transistor is electrically connected with the second light-emitting control signal end of the nth row;

a control electrode of the second output transistor is electrically connected with the second node, a first electrode of the second output transistor is electrically connected with the fourth voltage end, and a second electrode of the second output transistor is electrically connected with the second light-emitting control signal end of the nth row;

a control electrode of the third output transistor is electrically connected with the first node, a first electrode of the third output transistor is electrically connected with the third voltage end, and a second electrode of the third output transistor is electrically connected with the nth row first light-emitting control signal end;

and the control electrode of the fourth output transistor is electrically connected with the second light-emitting control signal end of the nth row, the first electrode of the fourth output transistor is electrically connected with the output clock signal end, and the second electrode of the fourth output transistor is electrically connected with the first light-emitting control signal end of the nth row.

Optionally, the node control circuit includes a first node control sub-circuit and a second node control sub-circuit;

the first node control sub-circuit is respectively electrically connected with the control node, the first node, the second node, a third voltage end and a second clock signal end, and is used for controlling the connection or disconnection between the first node and the third voltage end under the control of the potential of the second node, controlling the potential of the first node under the control of a second clock signal provided by the second clock signal end and the potential of the control node, and maintaining the potential of the first node;

the second node control sub-circuit is electrically connected to the second clock signal terminal, the second node, the control node, the third voltage terminal, the first clock signal terminal and the input terminal, and is configured to control a potential of the second node according to the second clock signal, control the second node to be connected to or disconnected from the third voltage terminal under the control of the potential of the control node and the second clock signal, and control the input terminal to be connected to or disconnected from the second node under the control of the first clock signal.

Optionally, the control node control circuit includes a first control transistor and a second control transistor;

a control electrode of the first control transistor is electrically connected with the second node, a first electrode of the first control transistor is electrically connected with the first clock signal end, and a second electrode of the first control transistor is electrically connected with the control node;

a control electrode of the second control transistor is electrically connected with the first clock signal end, a first electrode of the second control transistor is electrically connected with the fourth voltage end, and a second electrode of the second control transistor is electrically connected with the control node;

the first node control sub-circuit comprises a third control transistor, a first storage capacitor, a fourth control transistor, a fifth control transistor and a second storage capacitor;

a control electrode of the third control transistor is electrically connected with the second node, a first electrode of the third control transistor is electrically connected with the third voltage terminal, and a second electrode of the third control transistor is electrically connected with the first node;

a first end of the first storage capacitor is electrically connected with the first node, and a second end of the first storage capacitor is electrically connected with the third voltage end;

a control electrode of the fourth control transistor is electrically connected with the second clock signal end, a first electrode of the fourth control transistor is electrically connected with a second electrode of the fifth control transistor, and the second electrode of the fourth control transistor is electrically connected with the first node;

a control electrode of the fifth control transistor is electrically connected with the control node, and a first electrode of the fifth control transistor is electrically connected with the second clock signal end; a first end of the second storage capacitor is electrically connected with the first pole of the fourth control transistor, and a second end of the second storage capacitor is electrically connected with the control node;

the second node control sub-circuit comprises a sixth control transistor, a seventh control transistor, an eighth control transistor and a third storage capacitor;

a control electrode of the sixth control transistor is electrically connected with the first clock signal end, a first electrode of the sixth control transistor is electrically connected with the input end, and a control electrode of the sixth control transistor is electrically connected with the second node;

a control electrode of the seventh control transistor is electrically connected to the control node, a first electrode of the seventh control transistor is electrically connected to the third voltage terminal, and a second electrode of the seventh control transistor is electrically connected to the first electrode of the eighth control transistor;

a control electrode of the eighth control transistor is electrically connected with the second clock signal end, and a second electrode of the eighth control transistor is electrically connected with the second node;

the first end of the third storage capacitor is electrically connected with the second node, and the second end of the third storage capacitor is electrically connected with the second clock signal end.

The pixel circuit, the pixel driving method and the display device can reduce the display peak current.

Drawings

Fig. 1 is a structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 3 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 4 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 5 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 6 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 5 according to at least one embodiment of the present invention;

FIG. 7 is a waveform illustrating a simulation of current flowing through an OLED during operation of at least one embodiment of the pixel circuit shown in FIG. 5;

FIG. 8 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 9 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 8 according to at least one embodiment of the present invention;

FIG. 10 is a simulated waveform diagram of current flowing through the OLED during operation of at least one embodiment of the pixel circuit shown in FIG. 8;

FIG. 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 12 is a timing diagram illustrating operation of at least one embodiment of the pixel circuit shown in FIG. 11 according to the present invention;

FIG. 13 is a waveform illustrating a simulation of current flowing through an OLED during operation of at least one embodiment of the pixel circuit shown in FIG. 11;

FIG. 14 is a block diagram of at least one embodiment of an nth row emission control signal generation circuit;

FIG. 15 is a block diagram of at least one embodiment of an nth row emission control signal generation circuit;

FIG. 16 is a circuit diagram of at least one embodiment of an nth row emission control signal generation circuit;

fig. 17 is an operation timing diagram of at least one embodiment of the nth row emission control signal generation circuit shown in fig. 16.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.

As shown in fig. 1, the pixel circuit according to the embodiment of the present invention includes a drive circuit 11, a first light emission control circuit 12, a second light emission control circuit 13, a first initialization circuit 14, and a light emitting element EL;

the first light-emitting control circuit 12 is respectively electrically connected with a first light-emitting control line EM1, a first voltage end V1 and a first end of the driving circuit 11, and is used for controlling connection or disconnection between the first voltage end V1 and the first end of the driving circuit 11 under the control of a first light-emitting control signal provided by the first light-emitting control line EM 1;

the second light emission control circuit 13 is respectively connected to the first light emission control line EM1, and the second end of the driving circuit 11 is electrically connected to the first pole of the light emitting element EL, and is configured to control the connection or disconnection between the second end of the driving circuit 11 and the first pole of the light emitting element EL under the control of the first light emission control signal;

the first initialization circuit 14 is electrically connected to the second emission control line EM2, a first initialization voltage terminal and the first pole of the light emitting element EL, respectively, and is configured to control the first initialization voltage terminal to provide a first initialization voltage Vint1 to the first pole of the light emitting element EL under the control of the second emission control signal provided by the second emission control line EM 2;

the driving circuit 11 is configured to generate a driving current flowing through a first terminal of the driving circuit 11 and a second terminal of the driving circuit 11 under the control of a potential of a control terminal of the driving circuit 11; the control terminal of the driving circuit 11 is labeled C0;

the second pole of the light emitting element EL is electrically connected to the second voltage terminal V2.

In at least one embodiment of the present invention, the first voltage terminal V1 may be a first high voltage terminal, and the second voltage terminal may be a first low voltage terminal, but not limited thereto.

In the pixel circuit according to the embodiment of the present invention, the first emission control circuit 12 and the second emission control circuit 13 operate under the control of the first emission control signal provided by the first emission control line EM1, the first initialization circuit 14 operates under the control of the second emission control signal provided by the second emission control line EM2, and the pulse width of the second emission control signal may be set to be greater than that of the first emission control signal, so as to reduce a display spike current, enable a low frequency display, and prevent a transient large current.

When the first light-emitting control signal is different from the second light-emitting control signal, and the pulse width of the second light-emitting control signal is set to be greater than that of the first light-emitting control signal, when the pixel circuit in the embodiment of the invention works, the display period may include a light-emitting stage, a peak suppression stage and a reset stage which are successively set;

in the light-emitting phase, the first light-emitting control circuit 12 controls the first voltage end V1 to be communicated with the first end of the driving circuit 11 under the control of the first light-emitting control signal; the second light emission control circuit 13 controls the communication between the second terminal of the driving circuit 11 and the first pole of the light emitting element EL under the control of the first light emission control signal;

in the peak suppressing phase and the reset phase, the first light-emitting control circuit 12 controls the first voltage end V1 to be disconnected from the first end of the driving circuit 11 under the control of the first light-emitting control signal; the second light emission control circuit 13 controls the second terminal of the driving circuit 11 to be disconnected from the first pole of the light emitting element EL under the control of the first light emission control signal;

in the reset phase, the first initialization circuit 14 controls the first initialization voltage terminal to provide the first initialization voltage Vint1 to the first pole of the light emitting element EL under the control of the second light emitting control signal, so as to control the light emitting element EL not to emit light.

When the pixel circuit according to the embodiment of the present invention operates, at the end of the light emitting period, the transistor included in the first light emitting control circuit 12 and the transistor included in the second light emitting control circuit 13 are turned off, and at this time, the transistor included in the first initializing circuit 14 is not turned on at the same time, but turned on after a certain time interval, so as to reduce a spike current caused by an instant jump of the potential of the first electrode of the light emitting element EL at the instant when the transistor included in the first light emitting control circuit 12 and the transistor included in the second light emitting control circuit 13 are turned off.

In at least one embodiment of the present invention, the light emitting element EL may be an organic light emitting diode, the first pole of the light emitting element EL may be an anode, and the second pole of the light emitting element EL may be a cathode, but not limited thereto.

As shown in fig. 2, on the basis of the embodiment of the pixel circuit shown in fig. 1, the pixel circuit according to at least one embodiment of the present invention may further include an on-off control circuit 20;

the on-off control circuit 20 is electrically connected to the first light-emitting control line EM1, and the second pole of the light-emitting element EL and the second voltage terminal V2, respectively, and is configured to control connection or disconnection between the second pole of the light-emitting element EL and the second voltage terminal V2 under the control of the first light-emitting control signal.

In at least one embodiment of the pixel circuit shown in fig. 2, the on-off control circuit 20 is additionally arranged, so that at the end of the light-emitting period, at the moment when the transistor included in the first light-emitting control circuit 12 and the transistor included in the second light-emitting control circuit 13 are turned off, the on-off control circuit 20 controls the second pole of the light-emitting element EL and the second voltage terminal V2 to be turned off under the control of the first light-emitting control signal, and at this time, even if the transistor included in the first initialization circuit 14 is turned on, no spike current is generated.

In at least one embodiment of the pixel circuit shown in fig. 2, the first light-emitting control signal and the second light-emitting control signal may be the same or different.

In at least one embodiment of the pixel circuit shown in fig. 2, when the first light-emitting control signal is different from the second light-emitting control signal, and the pulse width of the second light-emitting control signal is set to be greater than the pulse width of the first light-emitting control signal, the display period may include a light-emitting stage, a peak-suppressing stage, and a reset stage that are sequentially set;

in the light-emitting phase, the first light-emitting control circuit 12 controls the first voltage end V1 to be communicated with the first end of the driving circuit 11 under the control of the first light-emitting control signal; the second light emission control circuit 13 controls the communication between the second terminal of the driving circuit 11 and the first pole of the light emitting element EL under the control of the first light emission control signal; the on-off control circuit controls the second pole of the light-emitting element to be communicated with the second voltage end under the control of the first light-emitting control signal; the driving circuit drives the light-emitting element to emit light;

in the peak suppressing phase and the reset phase, the first light-emitting control circuit 12 controls the first voltage end V1 to be disconnected from the first end of the driving circuit 11 under the control of the first light-emitting control signal; the second light emission control circuit 13 controls the second terminal of the driving circuit 11 to be disconnected from the first pole of the light emitting element EL under the control of the first light emission control signal; the on-off control circuit controls the second pole of the light-emitting element to be disconnected with the second voltage end under the control of the first light-emitting control signal;

in the reset phase, the first initialization circuit 14 controls the first initialization voltage terminal to provide the first initialization voltage Vint1 to the first pole of the light emitting element EL under the control of the second light emitting control signal.

In at least one embodiment of the pixel circuit shown in fig. 2, when the first light-emitting control signal is the same as the second light-emitting control signal, the display period may include a light-emitting phase and a reset phase that are sequentially set;

in the reset phase, the first light-emitting control circuit 12 controls the first voltage terminal V1 to be disconnected from the first terminal of the driving circuit 11 under the control of the first light-emitting control signal; the second light emission control circuit 13 controls the second terminal of the driving circuit 11 to be disconnected from the first pole of the light emitting element EL under the control of the first light emission control signal; the on-off control circuit controls the second pole of the light-emitting element to be disconnected with the second voltage end under the control of the first light-emitting control signal;

Optionally, the on-off control circuit includes a fourth transistor;

In at least one embodiment of the present invention, the pixel circuit further includes a first tank circuit, a data writing circuit, a compensation control circuit, and a second initialization circuit;

As shown in fig. 3, on the basis of the embodiment of the pixel circuit shown in fig. 1, the pixel circuit according to at least one embodiment of the present invention further includes a first tank circuit 31, a data writing circuit 32, a compensation control circuit 33, and a second initialization circuit 34;

the first energy storage circuit 31 is electrically connected with the control end of the driving circuit 11 and is used for storing electric energy;

the Data writing circuit 32 is electrically connected to the first scan line GateP, the Data line Data, and the first end of the driving circuit 11, and is configured to write the Data voltage Vdata provided by the Data line Data into the first end of the driving circuit 11 under the control of the first scan signal provided by the first scan line GateP;

the compensation control circuit 33 is respectively electrically connected to the second scan line GateN, and the control end of the driving circuit 11 is electrically connected to the second end of the driving circuit 11, and is configured to control the connection or disconnection between the control end of the driving circuit 11 and the second end of the driving circuit 11 under the control of a second scan signal provided by the second scan line GateN;

the second initialization circuit 34 is electrically connected to a Reset control line Reset, a second initial voltage end, and the control end of the driving circuit 11, and is configured to write a second initial voltage Vint2 provided by the second initial voltage end into the control end of the driving circuit 11 under the control of a Reset control signal provided by the Reset control line Reset.

In at least one embodiment of the invention, the first initial voltage Vint1 may be the same as the second initialization voltage Vinit2, but not limited thereto, and in actual operation, the first initial voltage Vint1 may also be different from the second initialization voltage Vinit 2.

In at least one embodiment of the pixel circuit shown in fig. 3, the data writing circuit 32 writes a data voltage, the compensation control circuit 33 performs threshold voltage compensation, and the second initialization circuit 34 controls initialization of a potential at the control terminal of the driving circuit 11.

The difference between the at least one embodiment of the pixel circuit shown in fig. 4 of the present invention and the at least one embodiment of the pixel circuit shown in fig. 3 of the present invention is: at least one embodiment of the pixel circuit shown in fig. 4 of the present invention further includes an on-off control circuit 20;

As shown in fig. 5, on the basis of at least one embodiment of the pixel circuit shown in fig. 3, the light emitting element is an organic light emitting diode O1;

the first light emission control circuit 12 includes a first transistor T1, the second light emission control circuit 13 includes a second transistor T2, the driving circuit 11 includes a driving transistor T0, and the first initialization circuit 14 includes a third transistor T3;

a gate of the first transistor T1 is electrically connected to the first light emission control line EM1, a source of the first transistor T1 is electrically connected to a first high voltage terminal Vdd, and a drain of the first transistor T1 is electrically connected to a source of the driving transistor T0;

a gate electrode of the second transistor T2 is electrically connected to the first light emission control line EM1, a source electrode of the second transistor T2 is electrically connected to a drain electrode of the driving transistor T0, and a drain electrode of the second transistor T2 is electrically connected to an anode electrode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to a first low voltage terminal Vss;

a gate electrode of the third transistor T3 is electrically connected to the second light emission control line EM2, a source electrode of the third transistor T3 is electrically connected to the initial voltage terminal, and a drain electrode of the third transistor T3 is electrically connected to an anode electrode of the organic light emitting diode O1; the initial voltage end is used for providing an initial voltage Vint;

the first tank circuit 31 includes a first capacitor C1, the data write circuit 32 includes a fifth transistor T5, the compensation control circuit 33 includes a sixth transistor T6, and the second initialization circuit 34 includes a seventh transistor T7;

a first terminal of the first capacitor C1 is electrically connected to the gate of the driving transistor T0, and a second terminal of the first capacitor C1 is electrically connected to the first high voltage terminal Vdd;

a gate of the fifth transistor T5 is electrically connected to the first scan line GateP, a source of the fifth transistor T5 is electrically connected to the Data line Data, and a drain of the fifth transistor T5 is electrically connected to the source of the driving transistor T0;

a gate electrode of the sixth transistor T6 is electrically connected to the second scan line GateN, a source electrode of the sixth transistor T6 is electrically connected to the gate electrode of the driving transistor T0, and a drain electrode of the sixth transistor T6 is electrically connected to the drain electrode of the driving transistor T0;

a gate of the seventh transistor T7 is electrically connected to the Reset control line Reset, a source of the seventh transistor T7 is electrically connected to the gate of the driving transistor T0, and a drain of the seventh transistor T7 is electrically connected to the initial voltage terminal.

In at least one embodiment of the pixel circuit shown in fig. 5, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are all n-type thin film transistors, and the driving transistor T0, the first transistor T1, the second transistor T2, the fifth transistor T5 and the driving transistor are all p-type thin film transistors, but not limited thereto.

In at least one embodiment of the pixel circuit shown in fig. 5, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, but not limited thereto.

As shown in fig. 6, when the pixel circuit shown in fig. 5 of the present invention is in operation, the display period includes an initialization phase t1, a compensation phase t2, a light-emitting phase t3, a peak-suppressing phase t4, and a reset phase t5, which are sequentially arranged;

in the initialization phase T1, GateP and Reset provide a high voltage signal, GateN provides a low voltage signal, EM1 and EM2 both provide a high voltage signal, T7 is turned on to write Vint to the gate of T0 to enable T0 to conduct at the beginning of the compensation phase T2;

in the compensation phase T2, GateP and Reset provide low voltage signals, GateN provides high voltage signals, Data lines Data provide Data voltages Vdata, EM1 and EM2 both provide high voltage signals, T5 is turned on to write Vdata into the source of T0, T6 is turned on to control communication between the gate of T0 and the drain of T0;

at the beginning of the compensation phase T2, T0 is turned on, Vdata charges C1 through T5, T0 and T6 to raise the potential of the gate of T0 until T0 is turned off, at this time, the potential of the gate of T0 is Vdata + Vth, where Vth is the threshold voltage of T0;

in the lighting period T3, GateP provides a high voltage signal, Reset provides a low voltage signal, GateN provides a low voltage signal, EM1 and EM2 provide a low voltage signal, T5 is turned off, T6 is turned off, T1 and T2 are turned on, T3 is turned off, and T0 drives O1 to light;

in the peak suppression period T4, GateP provides a high voltage signal, Reset provides a low voltage signal, GateN provides a low voltage signal, EM1 provides a high voltage signal, EM2 provides a low voltage signal, T1 and T2 are turned off, and T3 is turned off, so that the peak current can be reduced;

in the Reset period T5, GateP provides a high voltage signal, Reset provides a low voltage signal, GateN provides a low voltage signal, EM1 and EM2 provide a high voltage signal, and T3 is turned on to write Vint into the anode of O1 to control O1 not to emit light.

FIG. 7 is a simulated waveform diagram of the current flowing through O1 when at least one embodiment of the pixel circuit shown in FIG. 5 is in operation according to the present invention; in fig. 7, the vertical axis represents the current I flowing through O1, and the horizontal axis represents the time t.

At least one embodiment of the pixel circuit shown in fig. 8 differs from at least one embodiment of the pixel circuit shown in fig. 5 in that: the EM1 and the EM2 are the same light emission control line, that is, the gate of the third transistor T3 is electrically connected to the first light emission control line EM 1;

at least one embodiment of the pixel circuit shown in fig. 8 further includes an on-off control circuit 20;

the on-off control circuit 20 comprises a fourth transistor T4;

a gate of the fourth transistor T4 is electrically connected to the first light emission control line EM1, a source of the fourth transistor T4 is electrically connected to an anode of the organic light emitting diode O1, and a drain of the fourth transistor T4 is electrically connected to a first low voltage terminal Vss.

In at least one embodiment of the pixel circuit shown in fig. 8, T4 is a p-type tft, but not limited thereto.

As shown in fig. 9, when the pixel circuit shown in fig. 8 of the present invention is in operation, the display period includes an initialization phase t1, a compensation phase t2, a light-emitting phase t3, and a reset phase t 5;

in the initialization phase T1, GateP and Reset provide a high voltage signal, GateN provides a low voltage signal, EM1 provides a high voltage signal, T4 is turned off, T7 is turned on to write Vint to the gate of T0, so that at the beginning of the compensation phase T2, T0 can be turned on;

in the compensation phase T2, GateP and Reset provide low voltage signals, GateN provides high voltage signals, Data line Data provides Data voltage Vdata, EM1 provides high voltage signals, T4 is turned off, T5 is turned on to write Vdata into the source of T0, T6 is turned on to control the connection between the gate of T0 and the drain of T0;

in the lighting period T3, GateP provides a high voltage signal, Reset provides a low voltage signal, GateN provides a low voltage signal, EM1 provides a low voltage signal, T5 is turned off, T6 is turned off, T1 and T2 are turned on, T4 is turned on, T3 is turned off, and T0 drives O1 to light;

in the Reset phase T5, the GateP provides a high voltage signal, the Reset provides a low voltage signal, the GateN provides a low voltage signal, the EM1 provides a high voltage signal, the T3 is turned on, the T4 is turned off, and the cathode of the O1 is controlled to be disconnected from the low voltage terminal Vss, so that the T3 is turned on, and no spike current is generated.

FIG. 10 is a simulated waveform diagram of the current flowing through O1 when at least one embodiment of the pixel circuit shown in FIG. 8 is in operation according to the present invention; in fig. 10, the vertical axis represents the current I flowing through O1, and the horizontal axis represents the time t.

At least one embodiment of the pixel circuit shown in fig. 11 differs from at least one embodiment of the pixel circuit shown in fig. 8 in that: a gate of the third transistor T3 is electrically connected to the second emission control line EM 2.

As shown in fig. 12, when at least one embodiment of the pixel circuit shown in fig. 11 of the present invention is in operation, the display period includes an initialization phase t1, a compensation phase t2, a light-emitting phase t3, a peak suppressing phase t4, and a reset phase t5, which are sequentially arranged;

during the peak suppression period t4, GateP provides a high voltage signal, Reset provides a low voltage signal, GateN provides a low voltage signal, EM1 provides a high voltage signal, and EM2 provides a low voltage signal; t1 and T2 are turned off, T3 is turned on, T4 is turned off, and the connection between the cathode of O1 and the low-voltage terminal Vss is controlled, so that even if T3 is turned on, a spike current cannot be generated;

in the Reset period T5, the gateP provides a high voltage signal, the Reset provides a low voltage signal, the gateN provides a low voltage signal, the EM1 provides a high voltage signal, the T3 is turned on, the T4 is turned off, and the cathode of the O1 is controlled to be disconnected from the low voltage terminal Vss.

FIG. 13 is a simulated waveform diagram of the current flowing through O1 when at least one embodiment of the pixel circuit shown in FIG. 11 is in operation according to the present invention; in fig. 13, the vertical axis represents the current I flowing through O1, and the horizontal axis represents the time t.

The pixel driving method according to at least one embodiment of the present invention is applied to the pixel circuit, and the pixel driving method includes:

In the pixel driving method according to the embodiment of the present invention, the first light emission control circuit and the second light emission control circuit operate under the control of a first light emission control signal provided by a first light emission control line, the first initialization circuit operates under the control of a second light emission control signal provided by a second light emission control line, and a pulse width of the second light emission control signal may be set to be greater than a pulse width of the first light emission control signal to reduce a display spike current.

In at least one embodiment of the present invention, the first light emitting control signal is different from the second light emitting control signal; the display period comprises a light-emitting stage, a peak suppression stage and a reset stage which are arranged in sequence; the pixel driving method includes:

In specific implementation, the pixel circuit further comprises an on-off control circuit; the pixel driving method further includes:

Optionally, the pixel circuit further includes an on-off control circuit; the first light emission control signal is the same as the second light emission control signal; the display period comprises a light-emitting stage and a reset stage which are arranged in sequence; a pixel driving method according to at least one embodiment of the present invention includes:

The display device of the embodiment of the invention comprises a plurality of rows and a plurality of columns of the pixel circuit.

In a specific implementation, the display device according to at least one embodiment of the present invention may further include a plurality of first light-emitting control lines, a plurality of second light-emitting control lines, and a light-emitting control signal generating module; the light-emitting control signal generation module comprises a multi-row light-emitting control signal generation circuit;

n is a positive integer.

The display device according to at least one embodiment of the present invention can provide the corresponding first light-emitting control signal and the corresponding second light-emitting control signal through the light-emitting control signal generating module, so as to implement a narrow frame.

In at least one embodiment of the present invention, as shown in fig. 14, at least one embodiment of the nth row emission control signal generation circuit may include a node control circuit 141, a first output circuit 142, a second output circuit 143, and a control node control circuit 144;

the node control circuit 141 is electrically connected to a first node N1 and a second node N2, respectively, for controlling the potential of the first node N1 and the potential of the second node N2;

the control node control circuit 144 is electrically connected to the second node N2, the control node N3, the first clock signal terminal ECK and the fourth voltage terminal V4, respectively, and is configured to control the potential of the control node N3 according to the first clock signal and the fourth voltage signal provided by the fourth voltage terminal V4 under the control of the potential of the second node N2 and the first clock signal provided by the first clock signal terminal ECK;

the first output circuit 142 is electrically connected to the first node N1, the second node N2, the nth row second emission control signal terminal EM2(N), the third voltage terminal V3 and the fourth voltage terminal V4, respectively, and is configured to control generation and output of an nth row second emission control signal through the nth row second emission control signal terminal EM2(N) under control of the potential of the first node N1 and the potential of the second node N2;

the second output circuit 143 is electrically connected to the nth row first light-emitting control signal terminal EM1(N), the nth row second light-emitting control signal terminal EM2(N), the first node N1, the third voltage terminal V3 and the output clock signal terminal ECK2, respectively, and is configured to control communication between the nth row first light-emitting control signal terminal EM1(N) and the third voltage terminal V3 under control of the potential of the first node N1, and control communication between the nth row first light-emitting control signal terminal EM1(N) and the output clock signal terminal ECK2 under control of the nth row second light-emitting control signal.

In at least one embodiment of the present invention, the third voltage terminal V3 can be a second high voltage terminal, and the fourth voltage terminal V4 can be a second low voltage terminal, but not limited thereto.

In operation of at least one embodiment of the nth row emission control signal generation circuit shown in fig. 14, the second output circuit 143 controls the nth row first emission control signal terminal EM1(N) to output the nth row first emission control signal under the control of the potential at the first node N1 and the nth row second emission control signal provided by the nth row second emission control signal terminal EM2 (N).

In a specific implementation, the node control circuit may include a first node control sub-circuit that controls a potential of the first node and a second node control sub-circuit that controls a potential of the second node.

As shown in fig. 15, on the basis of at least one embodiment of the nth row light emission control signal generation circuit shown in fig. 14, the node control circuit includes a first node control sub-circuit 151 and a second node control sub-circuit 152;

the first node control sub-circuit 151 is electrically connected to the control node N3, the first node N1, the second node N2, a third voltage terminal V3 and a second clock signal terminal ECB, respectively, and is configured to control connection and disconnection between the first node N1 and the third voltage terminal V3 under control of a potential of the second node N2, control a potential of the first node N1 under control of a second clock signal provided from the second clock signal terminal ECB and a potential of the control node N3, and maintain a potential of the first node N1;

the second node control sub-circuit 152 is electrically connected to the second clock signal terminal ECB, the second node N2, the control node N3, the third voltage terminal V3, the first clock signal terminal ECK, and the input terminal espv, respectively, and is configured to control the potential of the second node N2 according to the second clock signal, to control the connection or disconnection between the second node N2 and the third voltage terminal V3 under the control of the potential of the control node N3 and the second clock signal, and to control the connection or disconnection between the input terminal espv and the second node N2 under the control of the first clock signal.

As shown in fig. 16, on the basis of at least one embodiment of the nth row emission control signal generation circuit shown in fig. 15,

the control node control circuit 144 includes a first control transistor Tc1 and a second control transistor Tc 2;

a gate of the first control transistor Tc1 is electrically connected to the second node N2, a source of the first control transistor Tc1 is electrically connected to the first clock signal terminal ECK, and a drain of the first control transistor Tc1 is electrically connected to the control node N3;

a gate of the second control transistor Tc2 is electrically connected to the first clock signal terminal ECK, a source of the second control transistor Tc2 is electrically connected to a second low voltage terminal VGL, and a drain of the second control transistor Tc2 is electrically connected to the control node N3;

the first node control sub-circuit 151 includes a third control transistor Tc3, a first storage capacitor Cst1, a fourth control transistor Tc4, a fifth control transistor Tc5, and a second storage capacitor Cst 2;

a gate of the third control transistor Tc3 is electrically connected to the second node N2, a source of the third control transistor Tc3 is electrically connected to the second high voltage terminal VGH, and a drain of the third control transistor Tc3 is electrically connected to the first node N1;

a first terminal of the first storage capacitor Cst1 is electrically connected to the first node N1, and a second terminal of the first storage capacitor Cst1 is electrically connected to the first high voltage terminal VGH;

a gate of the fourth control transistor Tc4 is electrically connected to the second clock signal terminal ECB, a source of the fourth control transistor Tc4 is electrically connected to a drain of the fifth control transistor Tc5, and a drain of the fourth control transistor Tc4 is electrically connected to the first node N1;

a gate of the fifth control transistor Tc5 is electrically connected to the control node N3, and a source of the fifth control transistor Tc5 is electrically connected to the second clock signal terminal ECB;

a first terminal of the second storage capacitor Cst2 is electrically connected to the source of the fourth control transistor Tc4, and a second terminal of the second storage capacitor Cst2 is electrically connected to the control node N3;

the second node control sub-circuit includes a sixth control transistor Tc6, a seventh control transistor Tc7, an eighth control transistor Tc8, and a third storage capacitor Cst 3;

a gate of the sixth control transistor Tc6 is electrically connected to the first clock signal terminal ECK, a source of the sixth control transistor Tc6 is electrically connected to the input terminal ESTV, and a gate of the sixth control transistor Tc6 is electrically connected to the second node N2;

a gate of the seventh control transistor Tc7 is electrically connected to the control node N3, a source of the seventh control transistor Tc7 is electrically connected to the first high voltage terminal VGH, and a drain of the seventh control transistor Tc7 is electrically connected to a source of the eighth control transistor Tc 8;

a gate of the eighth control transistor Tc8 is electrically connected to the second clock signal terminal ECB, and a drain of the eighth control transistor Tc8 is electrically connected to the second node N2;

a first terminal of the third storage capacitor Cst3 is electrically connected to the second node N2, and a second terminal of the third storage capacitor Cst3 is electrically connected to the second clock signal terminal ECB;

the first output circuit 142 includes a first output transistor To1 and a second output transistor To2, and the second output circuit 143 includes a third output transistor To3 and a fourth output transistor To 4;

a gate of the first output transistor To1 is electrically connected To the first node N1, a source of the first output transistor To1 is electrically connected To the second high voltage terminal VGH, and a drain of the first output transistor To1 is electrically connected To the nth row second light emission control signal terminal EM2 (N);

a gate of the second output transistor To2 is electrically connected To the second node N2, a source of the second output transistor To2 is electrically connected To the second low voltage terminal VGL, and a drain of the second output transistor To2 is electrically connected To the nth row second light emission control signal terminal EM2 (N);

a gate of the third output transistor To3 is electrically connected To the first node N1, a source of the third output transistor To3 is electrically connected To the second low voltage terminal VGL, and a drain of the third output transistor To3 is electrically connected To the nth row first light emission control signal terminal EM1 (N);

a gate of the fourth output transistor To4 is electrically connected To the nth row second light emission control signal terminal EM2(n), a source of the fourth output transistor To4 is electrically connected To the output clock signal terminal ECK2, and a drain of the fourth output transistor To4 is electrically connected To the nth row first light emission control signal terminal EM1 (n).

In at least one embodiment shown in fig. 16, all the transistors are p-type thin film transistors, but not limited thereto.

As shown in fig. 17, when at least one embodiment of the nth row light-emitting control signal generating circuit shown in fig. 16 is in operation, the display period includes a first stage S1, a second stage S2, a third stage S3, a fourth stage S4, a fifth stage S5, and a sixth stage S6, which are sequentially arranged;

in a first stage S1, the ESTV provides a low voltage signal, the ECK provides a high voltage signal, the ECB provides a low voltage signal, the ECK2 provides a low voltage signal, the Tc6 is off, the potential of the N2 is maintained at a low voltage, the Tc3 is on, the potential of the N1 is at a high voltage, To1 and To3 are both off, To2 is on, the EM2(N) outputs a low voltage signal, To4 is on, the EM1(N) and the ECK2 are connected, and the EM1(N) outputs a low voltage signal;

in the second stage S2, the ESTV provides a high voltage signal, the ECK provides a low voltage signal, the ECB provides a high voltage signal, Tc6 is turned on, N2 and ESTV are connected, the potential of N2 is high voltage, Tc3 is turned off, Tc2 is turned on, the potential of N3 is low voltage, Tc7 is turned on, Tc8 is turned off, the potential of N1 is maintained at high voltage, To1 and To2 are turned off, EM2(N) maintains To output a low voltage signal, To3 is turned off, To4 is turned on, and EM1(N) and ECKL2 are connected;

in the third stage S3, the ESTV provides a high voltage signal, the ECK provides a high voltage signal, the ECB provides a low voltage signal, the ECK2 provides a high voltage signal, the Tc6 is off, the Tc2 is off, the potential of N3 is maintained at a low voltage, the Tc5 and the Tc4 are on to pull the potential of N1 low; tc7 and Tc8 are opened, the potential of N2 is high voltage, To1 and To3 are both opened, To2 is turned off, EM2(N) outputs a high voltage signal, To4 is turned off, and EM1(N) outputs a high voltage signal;

at a fourth stage S4, the ESTV provides a high voltage signal, the ECK provides a low voltage signal, the ECB provides a high voltage signal, the ECK2 provides a high voltage signal, Tc6 is turned on, the potential of N2 is a high voltage, Tc1 is turned off, the potential of N3 is maintained at a low voltage, Tc7 is turned on, Tc8 is turned off, Tc2 is turned on, and the potential of N3 is a low voltage; tc3 is turned off, Tc5 is turned on, Tc4 is turned off, the potential of N1 is maintained at a low voltage, To1 and To3 are both turned on, To2 is turned off, EM2(N) outputs a high voltage signal, To4 is turned off, and EM1(N) outputs a high voltage signal;

in a fifth stage S5, ESTV provides a low voltage signal, ECK provides a high voltage signal, ECB provides a low voltage signal, ECK2 provides a high voltage signal, Tc6 is off, the potential of N3 is maintained at a low voltage, Tc7 and Tc8 are both on, the potential of N2 is a high voltage, Tc4 and Tc5 are both on, the potential of N1 is a low voltage, To1 and To3 are on, To2 is off, EM2(N) outputs a high voltage signal, To4 is off, EM1(N) provides a high voltage signal;

in the sixth stage S6, the ESTV provides a low voltage signal, the ECK provides a low voltage signal, the ECB provides a high voltage signal, the ECK2 provides a low voltage signal, Tc2 is on, the potential of N3 is low, Tc6 is on, the potential of N2 is low, Tc3 is on, the potential of N1 is high, To1 is on, To2 is off, the EM2(N) outputs a low voltage signal, To3 is off, To4 is on, and the EM1(N) outputs a low voltage signal.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A pixel circuit is characterized by comprising a driving circuit, a first light-emitting control circuit, a second light-emitting control circuit, a first initialization circuit and a light-emitting element;

2. The pixel circuit according to claim 1, wherein a first light emission control signal provided by the first light emission control line is different from a second light emission control signal provided by the second light emission control line; or, the first light-emitting control signal provided by the first light-emitting control line is the same as the second light-emitting control signal provided by the second light-emitting control line.

3. The pixel circuit according to claim 2, wherein the pixel circuit further comprises an on-off control circuit;

4. The pixel circuit according to claim 1, wherein the first light emission control circuit includes a first transistor, the second light emission control circuit includes a second transistor, the driving circuit includes a driving transistor, and the first initialization circuit includes a third transistor;

5. The pixel circuit according to claim 3, wherein the on-off control circuit comprises a fourth transistor;

6. The pixel circuit according to any one of claims 2 to 5, further comprising a first tank circuit, a data write circuit, a compensation control circuit, and a second initialization circuit;

7. The pixel circuit according to claim 6, wherein the first tank circuit comprises a first capacitor, the data write circuit comprises a fifth transistor, the compensation control circuit comprises a sixth transistor, and the second initialization circuit comprises a seventh transistor;

8. A pixel driving method applied to the pixel circuit according to any one of claims 1 to 7, wherein the pixel driving method comprises:

9. The pixel driving method according to claim 8, wherein the first light emission control signal is different from the second light emission control signal; the display period comprises a light-emitting stage, a peak suppression stage and a reset stage which are arranged in sequence; the pixel driving method includes:

10. The pixel driving method according to claim 9, wherein the pixel circuit further includes an on-off control circuit; the pixel driving method further includes:

11. The pixel driving method according to claim 8, wherein the pixel circuit further includes an on-off control circuit; the first light emission control signal is the same as the second light emission control signal; the display period comprises a light-emitting stage and a reset stage which are arranged in sequence; the pixel driving method includes:

12. A display device comprising a plurality of rows and columns of the pixel circuit according to any one of claims 1 to 7.

13. The display device according to claim 12, further comprising a plurality of rows of first light emission control lines, a plurality of rows of second light emission control lines, and a light emission control signal generation module; the light-emitting control signal generation module comprises a multi-row light-emitting control signal generation circuit;

n is a positive integer.

14. The display device according to claim 13, wherein the nth row light emission control signal generation circuit includes a node control circuit, a first output circuit, and a second output circuit;

15. The display device according to claim 14, wherein the first output circuit includes a first output transistor and a second output transistor, and wherein the second output circuit includes a third output transistor and a fourth output transistor;

16. The display device according to claim 14, wherein the node control circuit includes a first node control sub-circuit and a second node control sub-circuit;

17. The display device according to claim 16, wherein the control node control circuit includes a first control transistor and a second control transistor;