CN114023264A - Drive circuit, drive module, drive method and display device - Google Patents

Drive circuit, drive module, drive method and display device Download PDF

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Publication number
CN114023264A
CN114023264A CN202111430130.5A CN202111430130A CN114023264A CN 114023264 A CN114023264 A CN 114023264A CN 202111430130 A CN202111430130 A CN 202111430130A CN 114023264 A CN114023264 A CN 114023264A
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China
Prior art keywords
driving
circuit
row
control
node
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CN202111430130.5A
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CN114023264B (en
Inventor
高志坤
秦斌
王玮
彭宽军
郭凯
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention provides a driving circuit, a driving module, a driving method and a display device. A drive circuit including a first drive circuit and a second drive circuit; the first driving circuit comprises a first node control circuit, a second node control circuit, a first energy storage circuit, a second energy storage circuit and an output circuit; the second driving circuit controls the second driving output end to be communicated with the first voltage line or controls the second driving output end to be communicated with the second voltage line under the control of the first driving signal; the first node control circuit controls the potential of the first node; the second node control circuit controls the potential of the second node; the output circuit writes the second clock signal into the first driving output terminal under the control of the potential of the first node, and writes the third voltage signal into the first driving output terminal under the control of the potential of the second node. The invention can save power consumption and realize narrow frame.

Description

Drive circuit, drive module, drive method and display device
Technical Field
The invention relates to the technical field of display, in particular to a driving circuit, a driving module, a driving method and a display device.
Background
The LTPO (low temperature polycrystalline Oxide) technology combines the high mobility of the LTPS (low temperature polycrystalline silicon) technology and the low leakage characteristic of the Oxide technology, realizes a dynamic refresh rate, and reduces the power consumption of the display panel. However, since the LTPO pixel circuit has both p-type transistors and n-type transistors, two different driving circuits are required to provide a low-voltage effective driving circuit and a high-voltage effective driving circuit, and the power consumption and the frame of the LTPO display product become large.
Disclosure of Invention
The invention mainly aims to provide a driving circuit, a driving module, a driving method and a display device, and solves the problems of high power consumption and large frame caused by the fact that an LTPO display product in the prior art needs two driving circuits for providing driving signals.
In order to achieve the above object, an embodiment of the present invention provides a driving circuit, including a first driving circuit and a second driving circuit; the first driving circuit comprises a first node control circuit, a second node control circuit, a first energy storage circuit, a second energy storage circuit and an output circuit;
the second driving circuit is electrically connected with the first driving output end, the first voltage line, the second voltage line and the second driving output end, and is used for controlling the communication between the second driving output end and the first voltage line or controlling the communication between the second driving output end and the second voltage line under the control of a first driving signal provided by the first driving output end;
the first node control circuit is respectively electrically connected with an input end, a first clock signal line, a second clock signal line, a third voltage line, a first node and a second node, is used for controlling the input signal provided by the input end to be written into the first node under the control of a first clock signal provided by the first clock signal line, and is used for controlling the first node to be electrically connected with the third voltage line under the control of the potential of the second node and a second clock signal provided by the second clock signal line;
the second node control circuit is respectively electrically connected with a first clock signal line, a fourth voltage line, a second node and a first node, is used for controlling the communication between the second node and the fourth voltage line under the control of the first clock signal, and is used for controlling the communication between the second node and the first clock signal line under the control of the potential of the first node;
the first energy storage circuit is electrically connected with the first node and used for storing electric energy;
the second energy storage circuit is electrically connected with the second node and used for storing electric energy;
the output circuit is electrically connected to the first node, the second node, the third voltage line, the second clock signal line, and the first driving output terminal, and is configured to write the second clock signal provided by the second clock signal line into the first driving output terminal under the control of the potential of the first node, and write the third voltage signal provided by the third voltage line into the first driving output terminal under the control of the potential of the second node.
Optionally, the second driving circuit includes a first driving transistor and a second driving transistor;
a control electrode of the first driving transistor is electrically connected with the first driving output end, a first electrode of the first driving transistor is electrically connected with a first voltage line, and a second electrode of the first driving transistor is electrically connected with the second driving output end;
a control electrode of the second driving transistor is electrically connected with the first driving output end, a first electrode of the second driving transistor is electrically connected with the second driving output end, and a second electrode of the second driving transistor is electrically connected with a second voltage line;
the first driving transistor is a p-type transistor, the second driving transistor is an n-type transistor, the first voltage line is a first high voltage line, and the second voltage line is a first low voltage line.
Optionally, the first node control circuit includes a first transistor, a second transistor, and a third transistor;
a control electrode of the first transistor is electrically connected with the first clock signal line, a first electrode of the first transistor is electrically connected with the input end, and a second electrode of the first transistor is electrically connected with the first node;
a control electrode of the second transistor is electrically connected to the second node, a first electrode of the second transistor is electrically connected to the third voltage line, and a second electrode of the second transistor is electrically connected to a first electrode of the third transistor;
a control electrode of the third transistor is electrically connected to the second clock signal line, and a second electrode of the third transistor is electrically connected to the first node;
the second node control circuit includes a fourth transistor and a fifth transistor;
a control electrode of the fourth transistor is electrically connected to the first clock signal line, a first electrode of the fourth transistor is electrically connected to the fourth voltage line, and a second electrode of the fourth transistor is electrically connected to the second node;
a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the first clock signal line, and a second electrode of the fifth transistor is electrically connected to the first clock signal line.
Optionally, the first tank circuit includes a first capacitor, and the second tank circuit includes a second capacitor;
a first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with the first driving output end;
a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the third voltage line;
the output circuit includes a first output transistor and a second output transistor;
a control electrode of the first output transistor is electrically connected with the first node, a first electrode of the first output transistor is electrically connected with the second clock signal line, and a second electrode of the first output transistor is electrically connected with the second driving output end;
a control electrode of the second output transistor is electrically connected to the second node, a first electrode of the second output transistor is electrically connected to the third voltage line, and a second electrode of the second output transistor is electrically connected to the second driving output terminal.
Optionally, the first node control circuit further includes a sixth transistor; a second pole of the first transistor is electrically connected to the first node through the sixth transistor;
a control electrode of the sixth transistor is electrically connected to a fourth voltage line, a first electrode of the sixth transistor is electrically connected to a second electrode of the first transistor, and the second electrode of the sixth transistor is electrically connected to the first node.
The embodiment of the invention also provides a driving module, which comprises the multi-stage driving circuit;
the input end of the first-stage driving circuit is electrically connected with a starting voltage line;
except for the first stage of driving circuit, the input end of the driving circuit of each stage is electrically connected with the first driving output end of the adjacent previous stage of driving circuit.
The embodiment of the invention also provides a driving method, which is applied to the driving circuit, wherein the driving cycle comprises an input stage, an output stage and a reset stage which are arranged in sequence; the driving method includes:
in the input stage, an input end provides an input signal, a first node control circuit writes the input signal into a first node under the control of a first clock signal, and an output circuit writes a second clock signal into a first driving output end under the control of the potential of the first node; the second node control circuit controls the second node to be communicated with the first clock signal line under the control of the potential of the first node, and the output circuit controls a third voltage signal to be written into the first driving output end under the control of the potential of the second node; the second driving circuit controls the second driving output end to be communicated with the second voltage line under the control of a first driving signal provided by the first driving output end;
in an output stage, a first energy storage circuit maintains the potential of the first node, a second node control circuit writes a first clock signal into a second node under the control of the potential of the first node, and the output circuit writes the second clock signal into the first driving output end under the control of the potential of the first node; the second driving circuit controls the second driving output end to be communicated with the first voltage line under the control of a first driving signal provided by the first driving output end;
in a reset phase, a second node control circuit controls communication between the second node and the fourth voltage line under the control of the first clock signal, the first node control circuit controls communication between the input terminal and the first node under the control of the first clock signal, and the output circuit writes the third voltage signal into the first driving output terminal under the control of the potential of the second node; the second driving circuit controls the second driving output end to be communicated with the second voltage line under the control of the first driving signal provided by the first driving output end.
The embodiment of the invention also provides a display device which comprises the driving module.
Optionally, the display device according to at least one embodiment of the present invention further includes a plurality of rows and columns of pixel circuits; the row a and column b pixel circuit comprises a row a and column b data writing sub-circuit, a row a and column b driving sub-circuit, a row a and column b compensation sub-circuit, a row a and column b resetting sub-circuit and a row a and column b energy storage sub-circuit; a and b are positive integers;
the a-row and b-column data writing sub-circuit is respectively electrically connected with the a-row first driving line, the b-column data line and the first end of the a-row and b-column driving sub-circuit, and is used for writing the data voltage provided by the b-column data line into the first end of the a-row and b-column driving sub-circuit under the control of a-row first driving signal provided by the a-row first driving line;
the a-row and b-column compensation sub-circuit is respectively electrically connected with the a-row second driving line, the control end of the a-row and b-column driving sub-circuit and the second end of the a-row and b-column driving sub-circuit, and is used for controlling the communication between the control end of the a-row and b-column driving sub-circuit and the second end of the a-row and b-column driving sub-circuit under the control of a-row second driving signal provided by the a-row second driving line;
the a-row and b-column reset sub-circuit is respectively electrically connected with an a-row second reset control line, a first reset voltage line and a control end of the a-row and b-column drive sub-circuit, and is used for supplying a first reset voltage supplied by the first reset voltage line to the control end of the a-row and b-column drive sub-circuit under the control of an a-row second reset control signal supplied by the a-row second reset control line;
the control end of the row a and column b energy storage sub-circuit is electrically connected with the control end of the row a and column b driving sub-circuit and is used for storing electric energy;
a first driving output end in an m-th level driving circuit included in the driving module is used for providing the a-th row first driving signal for the a-th row first driving line, and a second driving output end in an m-th level driving circuit included in the driving module is used for providing the a-th row second driving signal for the a-th row second driving line;
and a second driving output end in the m-1 stage driving circuit included in the driving module is used for providing a second reset control signal of the a-th row for the second reset control line of the a-th row.
Optionally, the a-row and b-column pixel circuit further includes an a-row and b-column initialization sub-circuit, an a-row and b-column first light-emitting control sub-circuit, an a-row and b-column second light-emitting control sub-circuit, and an a-row and b-column light-emitting element;
the a-row and b-column initialization sub-circuit is respectively electrically connected with an a-row first reset control line, a second reset voltage line and a first pole of the a-row and b-column light-emitting element and is used for writing a second reset voltage provided by the second reset voltage line into a first pole of the a-row and b-column light-emitting element under the control of an a-row first reset control signal provided by the a-row first reset control line; a second pole of the light emitting element in the a-th row and the b-th column is electrically connected with a first low voltage line;
the row a and column b first light-emitting control sub-circuit is respectively electrically connected with a row a light-emitting control line, a first high voltage line and a first end of the row a and column b driving sub-circuit, and is used for controlling the communication between the first high voltage line and the first end of the row a and column b driving sub-circuit under the control of a row a light-emitting control signal provided by the row a light-emitting control line;
the second light-emitting control sub-circuit in the a-th row and the b-th column is electrically connected with the light-emitting control line in the a-th row, the second end of the driving sub-circuit in the a-th row and the b-th column and the first pole of the light-emitting element in the a-th row and the b-th column respectively, and is used for controlling the communication between the second end of the driving sub-circuit in the a-th row and the b-th column and the first pole of the light-emitting element in the a-row and the b-th column under the control of the light-emitting control signal in the a-row;
the first driving output end in the m-1 stage driving circuit included in the driving module is used for providing a row a first reset control signal for the row a first reset control line.
The embodiment of the invention also provides a display device which comprises the driving module.
The driving circuit, the driving module, the driving method and the display device can provide a first driving signal with effective low voltage and a second driving signal with effective high voltage at the same time, can be applied to LTPO display products, reduce the number of transistors and capacitors, save power consumption and realize narrow frames.
Drawings
Fig. 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a driving circuit according to at least one embodiment of the invention;
FIG. 3 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;
FIG. 4 is a timing diagram illustrating operation of the driving circuit shown in FIG. 3 according to at least one embodiment of the present invention;
FIG. 5 is a block diagram of a driving module according to at least one embodiment of the present disclosure;
FIG. 6 is a block diagram of at least one embodiment of a pixel circuit in a display device according to the present invention;
FIG. 7 is a circuit diagram of at least one embodiment of a pixel circuit in a display device according to the present invention;
FIG. 8 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 7 according to at least one embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.
The driving circuit according to the embodiment of the present invention includes a first driving circuit and a second driving circuit 20; as shown in fig. 1, the first driving circuit includes a first node control circuit 11, a second node control circuit 12, a first tank circuit 13, a second tank circuit 14, and an output circuit 15;
the second driving circuit 20 is electrically connected to the first driving output Gpout, the first voltage line V1, the second voltage line V2 and the second driving output Gnout, and is configured to control communication between the second driving output Gnout and the first voltage line V1 or communication between the second driving output Gnout and the second voltage line V2 under control of a first driving signal provided by the first driving output Gpout;
the first node control circuit 11 is electrically connected to an input terminal I1, a first clock signal line CK, a second clock signal line CB, a third voltage line V3, a first node N1 and a second node N2, respectively, for controlling writing of an input signal supplied from an input terminal I1 into the first node N1 under control of a first clock signal supplied from the first clock signal line CK, and for controlling electrical connection of the first node N1 to the third voltage line V3 under control of a potential of the second node N2 and a second clock signal supplied from the second clock signal line CB;
the second node control circuit 12 is electrically connected to a first clock signal line CK, a fourth voltage line V4, a second node N2, and a first node N1, respectively, for controlling communication between the second node N2 and the fourth voltage line V4 under control of the first clock signal, and for controlling communication between the second node N2 and the first clock signal line CK under control of the potential of the first node N1;
the first energy storage circuit 13 is electrically connected to the first node N1 for storing electric energy;
the second tank circuit 14 is electrically connected to the second node N2 for storing electric energy;
the output circuit 15 is electrically connected to the first node N1, the second node N2, the third voltage line V3, the second clock signal line CB, and the first driving output Gpout, and is configured to write the second clock signal provided by the second clock signal line CB into the first driving output Gpout under the control of the potential of the first node N1, and write the third voltage signal provided by the third voltage line V3 into the first driving output Gpout under the control of the potential of the second node N2.
The driving circuit provided by the embodiment of the invention can simultaneously provide a first driving signal with effective low voltage and a second driving signal with effective high voltage, can be applied to LTPO display products, reduces the number of transistors and capacitors, can save power consumption and realize a narrow frame.
In at least one embodiment of the present invention, the first voltage line may be a first high voltage line, and the second voltage line may be a first low voltage line; the third voltage line may be a second high voltage line, and the fourth voltage line may be a second low voltage line, but not limited thereto.
When the embodiment of the driving circuit shown in fig. 1 of the present invention works, the driving cycle may include an input stage, an output stage, and a reset stage that are sequentially set;
in the input stage, the input terminal I1 provides an input signal, the first node control circuit 11 writes the input signal into the first node N1 under the control of a first clock signal, and the output circuit 15 writes a second clock signal into the first driving output terminal Gpout under the control of the potential of the first node N1; the second node control circuit 12 controls the connection between the second node N2 and the first clock signal line CK under the control of the potential of the first node N1, and the output circuit 15 controls the writing of the third voltage signal into the first driving output terminal Gpout under the control of the potential of the second node N2; the second driving circuit 20 controls the second driving output terminal Gnout to be connected to the second voltage line V2 under the control of the first driving signal provided by the first driving output terminal Gpout;
in the output phase, the first tank circuit 13 maintains the potential of the first node N1, the second node control circuit 12 writes the first clock signal into the second node N2 under the control of the potential of the first node N1, and the output circuit 15 writes the second clock signal into the first driving output terminal Gpout under the control of the potential of the first node N1; the second driving circuit 20 controls the second driving output terminal Gnout to be connected to the first voltage line V1 under the control of the first driving signal provided by the first driving output terminal Gpout;
in the reset phase, the second node control circuit 12 controls the connection between the second node N2 and the fourth voltage line V4 under the control of the first clock signal, the first node control circuit 11 controls the connection between the input terminal I1 and the first node N1 under the control of the first clock signal, and the output circuit 15 writes the third voltage signal into the first driving output terminal Gpout under the control of the potential of the second node N2; the second driving circuit 20 controls the second driving output terminal Gnout to communicate with the second voltage line V2 under the control of the first driving signal provided by the first driving output terminal Gpout.
In operation of the driving circuit according to the embodiment of the present invention, the first driving circuit may generate and output a first driving signal with a low voltage and effective through the first driving output terminal Gpout, and the second driving circuit 20 may be used as an inverter, but is not limited thereto.
Optionally, the second driving circuit includes a first driving transistor and a second driving transistor;
a control electrode of the first driving transistor is electrically connected with the first driving output end, a first electrode of the first driving transistor is electrically connected with a first voltage line, and a second electrode of the first driving transistor is electrically connected with the second driving output end;
a control electrode of the second driving transistor is electrically connected with the first driving output end, a first electrode of the second driving transistor is electrically connected with the second driving output end, and a second electrode of the second driving transistor is electrically connected with a second voltage line;
the first driving transistor is a p-type transistor, the second driving transistor is an n-type transistor, the first voltage line is a first high voltage line, and the second voltage line is a first low voltage line.
As shown in fig. 2, on the basis of the embodiment of the driving circuit shown in fig. 1, the second driving circuit 20 may include a first driving transistor Td1 and a second driving transistor Td 2;
a gate of the first driving transistor Td1 is electrically connected to the first driving output terminal Gpout, a source of the first driving transistor Td1 is electrically connected to a first high voltage line VDD, and a drain of the first driving transistor Td1 is electrically connected to a second driving output terminal Gnout;
a gate electrode of the second driving transistor Td2 is electrically connected to the first driving output terminal Gpout, a source electrode of the second driving transistor Td2 is electrically connected to the second driving output terminal Gnout, and a drain electrode of the second driving transistor Td2 is electrically connected to a first low voltage line VSS;
the first driving transistor Td1 is a p-type transistor, and the second driving transistor Td2 is an n-type transistor.
The embodiment of the driving circuit of the invention as shown in figure 2 is in operation,
when the first driving output Gpout outputs a low voltage signal, Td1 is turned on, Td2 is turned off, Gnout is communicated with VDD, and Gnout outputs a first high voltage signal;
when the first driving output terminal Gpout outputs a high voltage signal, Td1 is turned off, Td2 is turned on, Gnout is connected with VSS, and Gnout outputs a first low voltage signal.
In at least one embodiment of the present invention, the structure of the second driving circuit 20 is not limited to the structure shown in fig. 2, and may be any other circuit structure capable of implementing an inverting function.
In at least one embodiment of the present invention, the first node control circuit includes a first transistor, a second transistor, and a third transistor;
a control electrode of the first transistor is electrically connected with the first clock signal line, a first electrode of the first transistor is electrically connected with the input end, and a second electrode of the first transistor is electrically connected with the first node;
a control electrode of the second transistor is electrically connected to the second node, a first electrode of the second transistor is electrically connected to the third voltage line, and a second electrode of the second transistor is electrically connected to a first electrode of the third transistor;
a control electrode of the third transistor is electrically connected to the second clock signal line, and a second electrode of the third transistor is electrically connected to the first node.
In at least one embodiment of the present invention, the second node control circuit includes a fourth transistor and a fifth transistor;
a control electrode of the fourth transistor is electrically connected to the first clock signal line, a first electrode of the fourth transistor is electrically connected to the fourth voltage line, and a second electrode of the fourth transistor is electrically connected to the second node;
a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the first clock signal line, and a second electrode of the fifth transistor is electrically connected to the first clock signal line.
Optionally, the first tank circuit includes a first capacitor, and the second tank circuit includes a second capacitor;
a first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with the first driving output end;
a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the third voltage line.
Optionally, the output circuit includes a first output transistor and a second output transistor;
a control electrode of the first output transistor is electrically connected with the first node, a first electrode of the first output transistor is electrically connected with the second clock signal line, and a second electrode of the first output transistor is electrically connected with the second driving output end;
a control electrode of the second output transistor is electrically connected to the second node, a first electrode of the second output transistor is electrically connected to the third voltage line, and a second electrode of the second output transistor is electrically connected to the second driving output terminal.
Optionally, the first node control circuit further includes a sixth transistor; a second pole of the first transistor is electrically connected to the first node through the sixth transistor;
a control electrode of the sixth transistor is electrically connected to a fourth voltage line, a first electrode of the sixth transistor is electrically connected to a second electrode of the first transistor, and the second electrode of the sixth transistor is electrically connected to the first node.
In a specific implementation, the first node control circuit may further include a sixth transistor, and the second electrode of the first transistor is electrically connected to the first node through the sixth transistor, so as to prevent the potential of the first node from being affected by the potential of the second electrode of the first transistor, and stabilize the potential of the control electrode of the second output transistor (i.e., the potential of the first node).
As shown in fig. 3, based on at least one embodiment of the driving circuit shown in fig. 2,
the first node control circuit 11 includes a first transistor T1, a second transistor T2, a third transistor T3, and a sixth transistor T6;
the gate of the first transistor T1 is electrically connected to the first clock signal line CK, the source of the first transistor T1 is electrically connected to the input terminal I1, and the drain of the first transistor T1 is electrically connected to the source of the sixth transistor T6;
a gate of the second transistor T2 is electrically connected to the second node N2, a source of the second transistor T2 is electrically connected to a second high voltage line VH, and a drain of the second transistor T2 is electrically connected to a source of the third transistor T3;
a gate of the third transistor T3 is electrically connected to the second clock signal line CB, and a drain of the third transistor T3 is electrically connected to a source of the sixth transistor T6;
a gate of the sixth transistor T6 is electrically connected to a second low voltage line VL, and a drain of the sixth transistor T6 is electrically connected to the first node N1;
the second node control circuit 12 includes a fourth transistor T4 and a fifth transistor T5;
a gate of the fourth transistor T4 is electrically connected to the first clock signal line CK, a source of the fourth transistor T4 is electrically connected to the second low voltage line VL, and a drain of the fourth transistor T4 is electrically connected to the second node N2;
a gate of the fifth transistor T5 is electrically connected to the first node N1, a source of the fifth transistor T5 is electrically connected to the first clock signal line CK, and a drain of the fifth transistor T5 is electrically connected to the first clock signal line CK;
the first tank circuit comprises a first capacitor C1, and the second tank circuit comprises a second capacitor C2;
a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the first driving output terminal Gpout;
a first end of the second capacitor C2 is electrically connected to the second node N2, and a second end of the second capacitor C2 is electrically connected to the second high voltage line VH;
the output circuit 15 includes a first output transistor To1 and a second output transistor To 2;
a gate of the first output transistor To1 is electrically connected To the first node N1, a source of the first output transistor To1 is electrically connected To the second clock signal line CB, and a drain of the first output transistor To1 is electrically connected To the second driving output terminal Gnout;
a gate of the second output transistor To2 is electrically connected To the second node N2, a source of the second output transistor To1 is electrically connected To the second high voltage line VH, and a drain of the second output transistor To2 is electrically connected To the second driving output terminal Gnout.
In at least one embodiment of the driving circuit shown in fig. 3, T1, T2, T3, T4, T5, T6, To1, and To2 may all be p-type transistors, but are not limited thereto.
In at least one embodiment of the driving circuit shown in fig. 3, the input terminal I1 may be electrically connected to the first driving output terminal of the adjacent previous stage driving circuit.
In at least one embodiment of the driving circuit shown in fig. 3, the first driving signal output by the first driving output terminal Gpout can be used for controlling an LTPS (low temperature polysilicon) TFT (thin film transistor) in the pixel circuit, and the second driving signal output by the second driving output terminal Gnout can be used for controlling an Oxide TFT in the pixel circuit.
As shown in fig. 4, when the driving circuit shown in fig. 3 according to at least one embodiment of the present invention is in operation, the driving cycle may include an input stage S1, an output stage S2, and a reset stage S3;
in the input stage S1, I1 provides a low voltage signal, CK provides a low voltage signal, CB provides a high voltage signal, T1 is turned on, and T6 is turned on to input the low voltage signal provided by I1 to the first node N1 through T1 and T6; t4 and T5 are turned on so that the potential of N2 is low voltage, T2 is turned on, T3 is turned off, To1 and To2 are both turned on so that Gpout outputs a high voltage signal, Td1 is turned off, Td2 is turned on, Gnout outputs a low voltage signal;
in the output stage S2, I1 provides a high voltage signal, CK provides a high voltage signal, CB provides a low voltage signal, T1 is turned off, T4 is turned off, T5 is turned on, so that the second nodes N2 and CK are communicated, so that the potential of the second node N2 is a high voltage, T2 is turned off, C1 maintains the potential of the first node N1 as a low voltage, To1 is turned on, To2 is turned off, Gpout is communicated with CB, Gpout outputs a low voltage signal, Td1 is turned on, Td2 is turned off, Gnout is communicated with VDD, and Gnout outputs a high voltage signal;
in the reset phase S3, I1 provides a high voltage signal, CK provides a low voltage signal, CB provides a high voltage signal, T1 is turned on, so that the potential of the first node N1 becomes a high voltage, T4 is turned on, the potential of N2 is a low voltage, To1 is turned off, To2 is turned on, Gpout outputs a high voltage signal, To1 is turned off, To2 is turned on, and Gnout outputs a low voltage signal.
The driving module of the embodiment of the invention comprises a plurality of stages of driving circuits;
the input end of the first-stage driving circuit is electrically connected with a starting voltage line;
except for the first stage of driving circuit, the input end of the driving circuit of each stage is electrically connected with the first driving output end of the adjacent previous stage of driving circuit.
As shown in fig. 5, a first-stage driving circuit is denoted by reference numeral G1, a second-stage driving circuit is denoted by reference numeral G2, a second-stage driving circuit is denoted by reference numeral G3, an nth-stage driving circuit is denoted by reference numeral Gn, an n +1 th-stage driving circuit is denoted by reference numeral Gn +1, and n is an integer greater than 3;
the input terminal of the first-stage driving circuit G1 is electrically connected to the start voltage line STV;
the input end of the second stage driving circuit G2 is electrically connected with the first driving output terminal Gpout1 of the first stage driving circuit G1;
the input end of the third stage driving circuit G2 is electrically connected to the first driving output terminal Gpout2 of the second stage driving circuit G2;
the input end of the (n + 1) th stage driving circuit Gn +1 is electrically connected with the first driving output end Gpoutn of the nth stage driving circuit Gn;
in fig. 5, a second drive output terminal of the first stage drive circuit G1 is denoted by reference numeral Gnout1, a second drive output terminal of the second stage drive circuit G2 is denoted by reference numeral Gnout2, a second drive output terminal of the third stage drive circuit G3 is denoted by reference numeral Gnout3, a second drive output terminal of the nth stage drive circuit Gn is denoted by reference numeral Gnoutn, and a second drive output terminal of the n +1 th stage drive circuit Gn +1 is denoted by reference numeral Gnoutn + 1; reference numeral Gpout3 is a first driving output terminal of the third stage driving circuit G3, and reference numeral Gpout +1 is a first driving output terminal of the (n + 1) th stage driving circuit Sn + 1.
In fig. 5, only the first stage driving circuit G1 is shown to be electrically connected to the second high voltage line VH and the second low voltage line VL, but in at least one embodiment of the present invention, each of the driving circuits included in the driving module is electrically connected to the first clock signal line CK, the second clock signal line CB, the first high voltage line VDD, the first low voltage line VSS, the second high voltage line VH and the second low voltage line VL.
The driving method provided by the embodiment of the invention is applied to the driving circuit, and the driving cycle comprises an input stage, an output stage and a reset stage which are arranged in sequence; the driving method includes:
in the input stage, an input end provides an input signal, a first node control circuit writes the input signal into a first node under the control of a first clock signal, and an output circuit writes a second clock signal into a first driving output end under the control of the potential of the first node; the second node control circuit controls the second node to be communicated with the first clock signal line under the control of the potential of the first node, and the output circuit controls a third voltage signal to be written into the first driving output end under the control of the potential of the second node; the second driving circuit controls the second driving output end to be communicated with the second voltage line under the control of a first driving signal provided by the first driving output end;
in an output stage, a first energy storage circuit maintains the potential of the first node, a second node control circuit writes a first clock signal into a second node under the control of the potential of the first node, and the output circuit writes the second clock signal into the first driving output end under the control of the potential of the first node; the second driving circuit controls the second driving output end to be communicated with the first voltage line under the control of a first driving signal provided by the first driving output end;
in a reset phase, a second node control circuit controls communication between the second node and the fourth voltage line under the control of the first clock signal, the first node control circuit controls communication between the input terminal and the first node under the control of the first clock signal, and the output circuit writes the third voltage signal into the first driving output terminal under the control of the potential of the second node; the second driving circuit controls the second driving output end to be communicated with the second voltage line under the control of the first driving signal provided by the first driving output end.
In the driving method according to the embodiment of the present invention, in the input stage, the input signal provided by the input terminal is written into the first node, in the output stage, the first driving circuit controls the first driving output terminal to output the second clock signal, and the second driving circuit controls the second driving output terminal to output the first voltage signal, in the reset stage, the first driving circuit controls the first driving output terminal to output the third voltage signal, and the second driving circuit controls the second driving output terminal to output the second voltage signal.
The display device provided by the embodiment of the invention comprises the driving module.
The display device according to at least one embodiment of the present invention further includes a plurality of rows and columns of pixel circuits; the row a and column b pixel circuit comprises a row a and column b data writing sub-circuit, a row a and column b driving sub-circuit, a row a and column b compensation sub-circuit, a row a and column b resetting sub-circuit and a row a and column b energy storage sub-circuit; a and b are positive integers;
the a-row and b-column data writing sub-circuit is respectively electrically connected with the a-row first driving line, the b-column data line and the first end of the a-row and b-column driving sub-circuit, and is used for writing the data voltage provided by the b-column data line into the first end of the a-row and b-column driving sub-circuit under the control of a-row first driving signal provided by the a-row first driving line;
the a-row and b-column compensation sub-circuit is respectively electrically connected with the a-row second driving line, the control end of the a-row and b-column driving sub-circuit and the second end of the a-row and b-column driving sub-circuit, and is used for controlling the communication between the control end of the a-row and b-column driving sub-circuit and the second end of the a-row and b-column driving sub-circuit under the control of a-row second driving signal provided by the a-row second driving line;
the a-row and b-column reset sub-circuit is respectively electrically connected with an a-row second reset control line, a first reset voltage line and a control end of the a-row and b-column drive sub-circuit, and is used for supplying a first reset voltage supplied by the first reset voltage line to the control end of the a-row and b-column drive sub-circuit under the control of an a-row second reset control signal supplied by the a-row second reset control line;
the control end of the row a and column b energy storage sub-circuit is electrically connected with the control end of the row a and column b driving sub-circuit and is used for storing electric energy;
a first driving output end in an m-th level driving circuit included in the driving module is used for providing the a-th row first driving signal for the a-th row first driving line, and a second driving output end in an m-th level driving circuit included in the driving module is used for providing the a-th row second driving signal for the a-th row second driving line;
and a second driving output end in the m-1 stage driving circuit included in the driving module is used for providing a second reset control signal of the a-th row for the second reset control line of the a-th row.
In at least one embodiment of the present invention, the row-a-b-column pixel circuit includes a row-a-b-column data writing sub-circuit, a row-a-b-column driving sub-circuit, a row-a-b-column compensation sub-circuit, a row-a-b-column reset sub-circuit and a row-a-b-column energy storage sub-circuit, the row-a-n-column data writing sub-circuit is configured to write a data voltage provided by a column-b data line into a first end of the row-a-b-column driving sub-circuit, the row-a-b-column compensation sub-circuit is configured to control communication between a control end of the row-a-b-column driving sub-circuit and a second end of the row-b-column driving sub-circuit in a compensation phase so as to compensate for a threshold voltage of a light-emitting driving transistor included in the row-a-b-column driving circuit, the row-b-column resetting sub-circuit is configured to provide a first reset voltage provided by the first reset voltage line to a control end of the row-b-column driving sub-circuit in a reset phase, so that at the beginning of the compensation phase, the a-th row and b-th column driving sub-circuit can control the communication between the first end of the a-th row and b-th column driving sub-circuit and the second end of the a-th row and b-th column driving sub-circuit under the control of the potential of the control end.
In a specific implementation, the a-row and b-column pixel circuit may further include an a-row and b-column initialization sub-circuit, an a-row and b-column first light-emitting control sub-circuit, an a-row and b-column second light-emitting control sub-circuit, and an a-row and b-column light-emitting element;
the a-row and b-column initialization sub-circuit is respectively electrically connected with an a-row first reset control line, a second reset voltage line and a first pole of the a-row and b-column light-emitting element and is used for writing a second reset voltage provided by the second reset voltage line into a first pole of the a-row and b-column light-emitting element under the control of an a-row first reset control signal provided by the a-row first reset control line; a second pole of the light emitting element in the a-th row and the b-th column is electrically connected with a first low voltage line;
the row a and column b first light-emitting control sub-circuit is respectively electrically connected with a row a light-emitting control line, a first high voltage line and a first end of the row a and column b driving sub-circuit, and is used for controlling the communication between the first high voltage line and the first end of the row a and column b driving sub-circuit under the control of a row a light-emitting control signal provided by the row a light-emitting control line;
the second light-emitting control sub-circuit in the a-th row and the b-th column is electrically connected with the light-emitting control line in the a-th row, the second end of the driving sub-circuit in the a-th row and the b-th column and the first pole of the light-emitting element in the a-th row and the b-th column respectively, and is used for controlling the communication between the second end of the driving sub-circuit in the a-th row and the b-th column and the first pole of the light-emitting element in the a-row and the b-th column under the control of the light-emitting control signal in the a-row;
the first driving output end in the m-1 stage driving circuit included in the driving module is used for providing a row a first reset control signal for the row a first reset control line.
In at least one embodiment of the present invention, the a-row and b-column pixel circuit may further include an a-row and b-column initialization sub-circuit, an a-row and b-column first light-emitting control sub-circuit, an a-row and b-column second light-emitting control sub-circuit, and an a-row and b-column light-emitting element, where the a-row and b-column initialization sub-circuit may be configured to write a second reset voltage into a first pole of the a-row and b-column light-emitting element in a reset phase to control the a-row and b-column light-emitting element not to emit light; the first light-emitting control sub-circuit in the a-th row and the b-th column and the second light-emitting control sub-circuit in the a-th row and the b-th column are used for light-emitting control.
In at least one embodiment of the present invention, the light emitting device may be an organic light emitting diode, the first pole of the light emitting device may be an anode, and the second pole of the light emitting device may be a cathode, but not limited thereto.
As shown in fig. 6, the a-th row and b-th column pixel circuit includes an a-th row and b-th column data writing sub-circuit 61, an a-th row and b-th column driving sub-circuit 62, an a-th row and b-th column compensation sub-circuit 63, an a-th row and b-th column reset sub-circuit 64, an a-th row and b-th column energy storage sub-circuit 65, an a-th row and b-th column initialization sub-circuit 66, an a-th row and b-th column first light-emitting control sub-circuit 67, an a-th row and b-th column second light-emitting control sub-circuit 68 and an a-th row and b-th column organic light-emitting diode O1; a and b are positive integers;
the row-a and column-b Data writing sub-circuit 61 is electrically connected to the row-a first driving line Gate _ P, the column-b Data line Data and the first end of the row-a and column-b driving sub-circuit 62, respectively, and is configured to write the Data voltage provided by the column-b Data line Data into the first end of the row-a and column-b driving sub-circuit 62 under the control of the row-a first driving signal provided by the row-a first driving line Gate _ P;
the a-th row and b-th column compensation sub-circuit 63 is respectively electrically connected with the a-th row second driving line Gate _ N, the control terminal of the a-th row and b-th column driving sub-circuit 62 and the second terminal of the a-th row and b-th column driving sub-circuit 62, and is used for controlling the communication between the control terminal of the a-th row and b-th column driving sub-circuit 62 and the second terminal of the a-th row and b-th column driving sub-circuit 62 under the control of a-th row second driving signal provided by the a-th row second driving line Gate _ N;
the a-row and b-column Reset sub-circuit 64 is electrically connected to the a-row and second Reset control line Reset _ N, the first Reset voltage line Init _ N, and the control end of the a-row and b-column drive sub-circuit 62, respectively, and configured to provide the first Reset voltage provided by the first Reset voltage line Init _ N to the control end of the a-row and b-column drive sub-circuit 62 under the control of the a-row and second Reset control signal provided by the a-row and second Reset control line Reset _ N;
the row a and column b energy storage sub-circuit 65 is electrically connected with the control end of the row a and column b driving sub-circuit 62, and is configured to store electric energy;
the a-th row and b-th column initialization sub-circuit 66 is electrically connected to a-th row first Reset control line Reset _ P, a second Reset voltage line Init _ P and an anode of the a-th row and b-th column organic light emitting diode O1, respectively, and is configured to write a second Reset voltage supplied by the second Reset voltage line Init _ P into an anode of the a-th row and b-th column organic light emitting diode O1 under the control of a-th row first Reset control signal supplied by the a-th row first Reset control line Reset _ P; the cathode of the a-th row and b-th column organic light emitting diode O1 is electrically connected with a first low voltage line VSS;
the a-th row and b-th column first emission control sub-circuit 67 is electrically connected to the a-th row emission control line EM, the first high voltage line VDD and the first end of the a-th row and b-th column driving sub-circuit 62, respectively, and is configured to control communication between the first high voltage line VDD and the first end of the a-th row and b-th column driving sub-circuit 62 under the control of an a-th row emission control signal provided by the a-th row emission control line EM;
the a-row and b-column second emission control sub-circuit 68 is electrically connected to the a-row emission control line EM, the second terminal of the a-row and b-column driving sub-circuit 62 and the anode of the a-row and b-column organic light emitting diode O1, respectively, for controlling the communication between the second terminal of the a-row and b-column driving sub-circuit 62 and the anode of the a-row and b-column organic light emitting diode O1 under the control of the a-row emission control signal;
a first driving output end in an m-th level driving circuit included in the driving module is used for providing the a-th row first driving signal for the a-th row first driving line Gate _ P, and a second driving output end in an m-th level driving circuit included in the driving module is used for providing the a-th row second driving signal for the a-th row second driving line Gate _ N;
a second driving output end in an m-1 stage driving circuit included in the driving module is used for providing an a-th row second Reset control signal for the a-th row second Reset control line Reset _ N;
the first driving output end in the m-1 stage driving circuit included in the driving module is used for providing a row a first Reset control signal for the row a first Reset control line Reset _ P.
As shown in fig. 7, on the basis of at least one embodiment of the row a and column b pixel circuits shown in fig. 6, the row a and column b data writing sub-circuit 61 may include a data writing transistor M1, the row a and column b driving sub-circuit 62 includes a light emitting driving transistor M2, the row a and column b compensating sub-circuit 63 includes a compensating transistor M3, the row a and column b resetting sub-circuit 64 includes a resetting transistor M4, the row a and column b storage sub-circuit 65 includes a storage capacitor Cst, the row a and column b initializing sub-circuit 66 includes an initializing transistor M5, the row a and column b first light emitting controlling sub-circuit 67 includes a sixth transistor M6, and the row a and column b second light emitting controlling sub-circuit 68 includes a seventh transistor M7;
the Gate of M1 is electrically connected to the first driving line Gate _ P of row a, the source of M1 is electrically connected to the Data line Data of column b, and the drain of M1 is electrically connected to the fourth node N4;
the gate of M2 is electrically connected with a third node N3, and the source of M2 is electrically connected with the fourth node N4;
the grid electrode of M3 is electrically connected with the second driving line Gate _ N of the a-th row, the source electrode of M3 is electrically connected with the third node N3, and the drain electrode of M3 is electrically connected with the drain electrode of M2;
a gate of M4 is electrically connected to a second Reset control line Reset _ N of the a-th row, a source of M4 is electrically connected to the first Reset voltage line Init _ N, and a drain of M4 is electrically connected to the third node N3;
a gate of the M5 is electrically connected to a first Reset control line Reset _ P of the a-th row, a source of the M5 is electrically connected to the second Reset voltage line Init _ P, and a drain of the M5 is electrically connected to an anode of the a-th row and b-th column organic light emitting diode O1;
a gate of M6 is electrically connected to the a-th row emission control line EM, a source of M6 is electrically connected to the first high voltage line VDD, and a drain of M6 is electrically connected to the fourth node N4;
the gate of M7 is electrically connected to the a-th row emission control line EM, the source of M7 is electrically connected to the drain of M2, and the drain of M7 is electrically connected to the anode of O1.
In at least one embodiment of the row a and column b pixel circuits shown in fig. 7, M3 and M4 are both oxide thin film transistors, M3 and M4 are both n-type transistors, M1, M2, M5, M6 and M7 are all low temperature polysilicon thin film transistors, and M1, M2, M5, M6 and M7 are all p-type transistors.
In at least one embodiment of the pixel circuits in row a and column b shown in fig. 7, M3 and M4 are oxide thin film transistors to reduce leakage current and stabilize the potential of the third node N3, so that the O1 can be stably driven to emit light during the light emitting period M2.
As shown in fig. 8, when at least one embodiment of the pixel circuit in row a and column b shown in fig. 7 is in operation, the display period includes a reset phase t1, a compensation phase t2, and a light emitting phase t3, which are sequentially arranged;
in the Reset phase t1, Reset _ N provides a high voltage signal, Reset _ P provides a low voltage signal, Gate _ N provides a low voltage signal, Gate _ P provides a high voltage signal, EM provides a high voltage signal, M4 is turned on to write the first Reset voltage provided by Init _ N into the third node N3, so that M2 can be turned on at the beginning of the compensation phase t 2; m5 is turned on to write the second reset voltage provided by Init _ P into the anode of O1 to make O1 not emit light, clearing the residual charge of the anode of O1;
in the compensation phase t2, Reset _ N provides a low voltage signal, Reset _ P provides a high voltage signal, Gate _ N provides a high voltage signal, Gate _ P provides a low voltage signal, EM provides a high voltage signal, M1 is turned on to write the Data voltage Vdata provided by Data into the fourth node N4, and M3 is turned on to control the connection between the drains of the third nodes N3 and M2; at the beginning of the compensation phase t2, M2 is turned on to charge Cst via Vdata to raise the potential of the third node N3 until M2 is turned off, at which time the potential of the gate of M2 becomes Vdata + Vth, and Vth is the threshold voltage of M2;
in the lighting period t3, Reset _ N provides a low voltage signal, Reset _ P provides a high voltage signal, Gate _ N provides a low voltage signal, Gate _ P provides a high voltage signal, EM provides a low voltage signal, M6 and M7 are turned on, and M2 drives O1 to light.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A drive circuit is characterized by comprising a first drive circuit and a second drive circuit; the first driving circuit comprises a first node control circuit, a second node control circuit, a first energy storage circuit, a second energy storage circuit and an output circuit;
the second driving circuit is electrically connected with the first driving output end, the first voltage line, the second voltage line and the second driving output end, and is used for controlling the communication between the second driving output end and the first voltage line or controlling the communication between the second driving output end and the second voltage line under the control of a first driving signal provided by the first driving output end;
the first node control circuit is respectively electrically connected with an input end, a first clock signal line, a second clock signal line, a third voltage line, a first node and a second node, is used for controlling the input signal provided by the input end to be written into the first node under the control of a first clock signal provided by the first clock signal line, and is used for controlling the first node to be electrically connected with the third voltage line under the control of the potential of the second node and a second clock signal provided by the second clock signal line;
the second node control circuit is respectively electrically connected with a first clock signal line, a fourth voltage line, a second node and a first node, is used for controlling the communication between the second node and the fourth voltage line under the control of the first clock signal, and is used for controlling the communication between the second node and the first clock signal line under the control of the potential of the first node;
the first energy storage circuit is electrically connected with the first node and used for storing electric energy;
the second energy storage circuit is electrically connected with the second node and used for storing electric energy;
the output circuit is electrically connected to the first node, the second node, the third voltage line, the second clock signal line, and the first driving output terminal, and is configured to write the second clock signal provided by the second clock signal line into the first driving output terminal under the control of the potential of the first node, and write the third voltage signal provided by the third voltage line into the first driving output terminal under the control of the potential of the second node.
2. The drive circuit according to claim 1, wherein the second drive circuit includes a first drive transistor and a second drive transistor;
a control electrode of the first driving transistor is electrically connected with the first driving output end, a first electrode of the first driving transistor is electrically connected with a first voltage line, and a second electrode of the first driving transistor is electrically connected with the second driving output end;
a control electrode of the second driving transistor is electrically connected with the first driving output end, a first electrode of the second driving transistor is electrically connected with the second driving output end, and a second electrode of the second driving transistor is electrically connected with a second voltage line;
the first driving transistor is a p-type transistor, the second driving transistor is an n-type transistor, the first voltage line is a first high voltage line, and the second voltage line is a first low voltage line.
3. The drive circuit according to claim 1 or 2, wherein the first node control circuit includes a first transistor, a second transistor, and a third transistor;
a control electrode of the first transistor is electrically connected with the first clock signal line, a first electrode of the first transistor is electrically connected with the input end, and a second electrode of the first transistor is electrically connected with the first node;
a control electrode of the second transistor is electrically connected to the second node, a first electrode of the second transistor is electrically connected to the third voltage line, and a second electrode of the second transistor is electrically connected to a first electrode of the third transistor;
a control electrode of the third transistor is electrically connected to the second clock signal line, and a second electrode of the third transistor is electrically connected to the first node;
the second node control circuit includes a fourth transistor and a fifth transistor;
a control electrode of the fourth transistor is electrically connected to the first clock signal line, a first electrode of the fourth transistor is electrically connected to the fourth voltage line, and a second electrode of the fourth transistor is electrically connected to the second node;
a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the first clock signal line, and a second electrode of the fifth transistor is electrically connected to the first clock signal line.
4. The drive circuit of claim 1 or 2, wherein the first tank circuit comprises a first capacitor and the second tank circuit comprises a second capacitor;
a first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with the first driving output end;
a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the third voltage line;
the output circuit includes a first output transistor and a second output transistor;
a control electrode of the first output transistor is electrically connected with the first node, a first electrode of the first output transistor is electrically connected with the second clock signal line, and a second electrode of the first output transistor is electrically connected with the second driving output end;
a control electrode of the second output transistor is electrically connected to the second node, a first electrode of the second output transistor is electrically connected to the third voltage line, and a second electrode of the second output transistor is electrically connected to the second driving output terminal.
5. The drive circuit according to claim 3, wherein the first node control circuit further includes a sixth transistor; a second pole of the first transistor is electrically connected to the first node through the sixth transistor;
a control electrode of the sixth transistor is electrically connected to a fourth voltage line, a first electrode of the sixth transistor is electrically connected to a second electrode of the first transistor, and the second electrode of the sixth transistor is electrically connected to the first node.
6. A driver module comprising a plurality of stages of driver circuits according to any of claims 1 to 5;
the input end of the first-stage driving circuit is electrically connected with a starting voltage line;
except for the first stage of driving circuit, the input end of the driving circuit of each stage is electrically connected with the first driving output end of the adjacent previous stage of driving circuit.
7. A driving method is applied to the driving circuit as claimed in any one of claims 1 to 5, wherein the driving period comprises an input stage, an output stage and a reset stage which are arranged in sequence; the driving method includes:
in the input stage, an input end provides an input signal, a first node control circuit writes the input signal into a first node under the control of a first clock signal, and an output circuit writes a second clock signal into a first driving output end under the control of the potential of the first node; the second node control circuit controls the second node to be communicated with the first clock signal line under the control of the potential of the first node, and the output circuit controls a third voltage signal to be written into the first driving output end under the control of the potential of the second node; the second driving circuit controls the second driving output end to be communicated with the second voltage line under the control of a first driving signal provided by the first driving output end;
in an output stage, a first energy storage circuit maintains the potential of the first node, a second node control circuit writes a first clock signal into a second node under the control of the potential of the first node, and the output circuit writes the second clock signal into the first driving output end under the control of the potential of the first node; the second driving circuit controls the second driving output end to be communicated with the first voltage line under the control of a first driving signal provided by the first driving output end;
in a reset phase, a second node control circuit controls communication between the second node and the fourth voltage line under the control of the first clock signal, the first node control circuit controls communication between the input terminal and the first node under the control of the first clock signal, and the output circuit writes the third voltage signal into the first driving output terminal under the control of the potential of the second node; the second driving circuit controls the second driving output end to be communicated with the second voltage line under the control of the first driving signal provided by the first driving output end.
8. A display device comprising the driving module according to claim 6.
9. The display device of claim 8, further comprising a plurality of rows and columns of pixel circuits; the row a and column b pixel circuit comprises a row a and column b data writing sub-circuit, a row a and column b driving sub-circuit, a row a and column b compensation sub-circuit, a row a and column b resetting sub-circuit and a row a and column b energy storage sub-circuit; a and b are positive integers;
the a-row and b-column data writing sub-circuit is respectively electrically connected with the a-row first driving line, the b-column data line and the first end of the a-row and b-column driving sub-circuit, and is used for writing the data voltage provided by the b-column data line into the first end of the a-row and b-column driving sub-circuit under the control of a-row first driving signal provided by the a-row first driving line;
the a-row and b-column compensation sub-circuit is respectively electrically connected with the a-row second driving line, the control end of the a-row and b-column driving sub-circuit and the second end of the a-row and b-column driving sub-circuit, and is used for controlling the communication between the control end of the a-row and b-column driving sub-circuit and the second end of the a-row and b-column driving sub-circuit under the control of a-row second driving signal provided by the a-row second driving line;
the a-row and b-column reset sub-circuit is respectively electrically connected with an a-row second reset control line, a first reset voltage line and a control end of the a-row and b-column drive sub-circuit, and is used for supplying a first reset voltage supplied by the first reset voltage line to the control end of the a-row and b-column drive sub-circuit under the control of an a-row second reset control signal supplied by the a-row second reset control line;
the control end of the row a and column b energy storage sub-circuit is electrically connected with the control end of the row a and column b driving sub-circuit and is used for storing electric energy;
a first driving output end in an m-th level driving circuit included in the driving module is used for providing the a-th row first driving signal for the a-th row first driving line, and a second driving output end in an m-th level driving circuit included in the driving module is used for providing the a-th row second driving signal for the a-th row second driving line;
and a second driving output end in the m-1 stage driving circuit included in the driving module is used for providing a second reset control signal of the a-th row for the second reset control line of the a-th row.
10. The display device of claim 9, wherein the row a and column b pixel circuits further comprise a row a and column b initialization sub-circuit, a row a and column b first emission control sub-circuit, a row a and column b second emission control sub-circuit, and a row a and column b emission element;
the a-row and b-column initialization sub-circuit is respectively electrically connected with an a-row first reset control line, a second reset voltage line and a first pole of the a-row and b-column light-emitting element and is used for writing a second reset voltage provided by the second reset voltage line into a first pole of the a-row and b-column light-emitting element under the control of an a-row first reset control signal provided by the a-row first reset control line; a second pole of the light emitting element in the a-th row and the b-th column is electrically connected with a first low voltage line;
the row a and column b first light-emitting control sub-circuit is respectively electrically connected with a row a light-emitting control line, a first high voltage line and a first end of the row a and column b driving sub-circuit, and is used for controlling the communication between the first high voltage line and the first end of the row a and column b driving sub-circuit under the control of a row a light-emitting control signal provided by the row a light-emitting control line;
the second light-emitting control sub-circuit in the a-th row and the b-th column is electrically connected with the light-emitting control line in the a-th row, the second end of the driving sub-circuit in the a-th row and the b-th column and the first pole of the light-emitting element in the a-th row and the b-th column respectively, and is used for controlling the communication between the second end of the driving sub-circuit in the a-th row and the b-th column and the first pole of the light-emitting element in the a-row and the b-th column under the control of the light-emitting control signal in the a-row;
the first driving output end in the m-1 stage driving circuit included in the driving module is used for providing a row a first reset control signal for the row a first reset control line.
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