CN114153765A - A memory access interface module, computing device and data transmission method - Google Patents
A memory access interface module, computing device and data transmission method Download PDFInfo
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Abstract
The invention discloses a memory access interface module, a computing device and a data transmission method, wherein a message conversion module in the memory access interface module is used for repackaging a TileLink protocol message sent by a TileLink processing module according to a PCIe protocol and sending the generated PCIe protocol message to the PCIe processing module; and repackaging the PCIe protocol message sent by the PCIe processing module according to the TileLink protocol, and sending the generated TileLink protocol message to the TileLink processing module. Therefore, the memory access interface module in the scheme is a composite memory access interface module integrating a TileLink protocol and a PCIe protocol, can realize message conversion between the TileLink protocol and the PCIe protocol, can be applied to various computing devices in a memory access scene, and realizes interconnection and memory access functions among the computing devices.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a memory access interface module, a computing device and a data transmission method.
Background
With the continuous development of Processor technologies, Processor Interface standards for memory access are becoming more and more diversified, such as CXL (computer Express Link, interconnect protocol), CCIX (cache Coherent interconnect protocol), OpenCAPI (Open Coherent Accelerator Interface), and the like. The RISC-V instruction set architecture is a novel processor architecture, is developed rapidly at present, and is expected to become a main stream processor architecture in the future. The internal system bus of the RISC-V processor usually adopts an open-source TileLink protocol which is specially designed for RISC-V and has the characteristics of low delay and high throughput rate. The TileLink protocol specification supports a consistent memory mapping approach, allowing access to other memory and devices. TileLink adopts the MOESI consistency protocol standard (where M is Modified state, E is Exclusive state, S is Shared state, I is Invalid state, and O is ownded state). TileLink defines the mode of operation to support caching (TileLink Cached, TL-C). Cache among multiple processors and coherent interconnection among processors and various memories can be realized based on the mode.
However, currently, TileLink only defines a protocol layer, which is mainly used for inter-chip interconnection, and there is no inter-chip interconnection scheme based on TileLink protocol, so how to implement inter-chip interconnection for computing devices such as processors and the like based on TileLink protocol is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide an access interface module, computing equipment and a data transmission method, so that the computing equipment such as a processor and the like can realize inter-chip interconnection based on a TileLink protocol.
In order to achieve the above object, the present invention provides a memory access interface module, which comprises:
the system comprises a TileLink processing module, a message conversion module and a PCIe processing module;
the message conversion module is used for: repackaging the TiLELink protocol message sent by the TiLELink processing module according to a PCIe protocol, and sending the generated PCIe protocol message to the PCIe processing module; and repackaging the PCIe protocol message sent by the PCIe processing module according to a TileLink protocol, and sending the generated TileLink protocol message to the TileLink processing module.
Wherein, the message conversion module comprises:
the sending unit is used for repackaging the TiLELink protocol message sent by the TiLELink processing module according to a PCIe protocol and sending the generated PCIe protocol message to the PCIe processing module;
and the receiving unit is used for repackaging the PCIe protocol message sent by the PCIe processing module according to the TileLink protocol and sending the generated TileLink protocol message to the TileLink processing module.
Wherein, the TileLink processing module comprises: a TileLink protocol layer.
Wherein the PCIe processing module comprises: a PCIe physical layer, a PCIe link layer, and a PCIe transport layer.
To achieve the above object, the present invention further provides a computing device, which includes the memory access interface module as described above.
The computing equipment is used for realizing the functions of interconnection and memory access with other computing equipment through the memory access interface module.
The number of the memory access interface modules in the computing equipment is the same as that of the other computing equipment.
Wherein the computing device is a RISC-V processor.
Wherein the computing device is a PCIe accelerator card.
In order to achieve the above object, the present invention further provides a data transmission method based on a memory access interface module, where the memory access interface module includes: the data transmission method comprises the following steps of:
the message conversion module repackages the TiLELink protocol message sent by the TiLELink processing module according to a PCIe protocol, and sends the generated PCIe protocol message to the PCIe processing module;
and the message conversion module repackages PCIe protocol messages sent by the PCIe processing module according to a TileLink protocol, and sends the generated TileLink protocol messages to the TileLink processing module.
According to the above scheme, the message conversion module in the memory access interface module is used for repackaging the TileLink protocol messages sent by the TileLink processing module according to the PCIe protocol, and sending the generated PCIe protocol messages to the PCIe processing module; and repackaging the PCIe protocol message sent by the PCIe processing module according to the TileLink protocol, and sending the generated TileLink protocol message to the TileLink processing module. Therefore, the memory access interface module in the scheme is a composite memory access interface module integrating a TileLink protocol and a PCIe protocol, can realize message conversion between the TileLink protocol and the PCIe protocol, can be applied to various computing devices in a memory access scene, realizes interconnection and memory access functions among the computing devices, solves the problem that no inter-chip interconnection or interface providing a memory access function exists in the current RISC-V ecology, and provides an effective interconnection scheme for RISC-V future ecological construction.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a memory access interface module according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a structure of a message conversion module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an overall structure of a memory access interface module according to an embodiment of the present invention;
FIG. 4 is a block diagram of a RISC-V processor according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses an access interface module, computing equipment and a data transmission method, which are used for enabling the computing equipment such as a processor and the like to realize inter-chip interconnection based on a TileLink protocol.
Referring to fig. 1, an embodiment of the present invention provides a memory access interface module, which includes:
a TileLink processing module 11, a message conversion module 12, and a PCIe (peripheral component interconnect express, high speed serial computer expansion bus standard) processing module 13;
the message conversion module 12 is configured to: repackaging the TiLELink protocol message sent by the TiLELink processing module 11 according to a PCIe protocol, and sending the generated PCIe protocol message to a PCIe processing module 13; and repackaging the PCIe protocol message sent by the PCIe processing module 13 according to the TileLink protocol, and sending the generated TileLink protocol message to the TileLink processing module 11.
It should be noted that, in this embodiment, the TileLink processing module 11 is mainly configured to process data by using a TileLink protocol, for example: when the memory access interface module is applied to the RISC-V processor, the TileLink processing module 11 in the memory access interface module processes data sent by the RISC-V processor by using a TileLink protocol, generates a TileLink protocol message and sends the TileLink protocol message to the message conversion module 12, so that the message conversion module 12 converts the TileLink protocol message into a PCIe protocol message and sends the PCIe protocol message to other computing devices through the PCIe processing module 13. The TileLink processing module in this embodiment only needs to process data by using a TileLink protocol, and does not limit the specific structure thereof, for example: the TileLink processing module may only include a TileLink protocol layer, or the TileLink processing module may include a TileLink protocol layer, a TileLink link layer, and the like, which is not limited herein.
Referring to fig. 2, a schematic structural diagram of a message conversion module provided in the embodiment of the present invention is shown, where TileLink to PCIe in fig. 2 is a message conversion module, and channels a to channel e on the left side of the message conversion module are five channels of a TileLink protocol, and since the access interface module needs to implement interconnection and access operation between two computing devices, the message conversion module has two channels a to channel e in total, and the two channels a to channel e need to be implemented by a sending unit (Transport, Tx) and a receiving unit (receive, Rx) when sending and receiving data, respectively, where the sending unit is configured to repackage TileLink protocol messages sent by the TileLink processing module according to the PCIe protocol, and send the generated PCIe protocol messages to the PCIe processing module; the receiving unit is used for repackaging the PCIe protocol message sent by the PCIe processing module according to the TiLELink protocol and sending the generated TiLELink protocol message to the TiLELink processing module.
In this embodiment, the PCIe processing module 13 is configured to send the PCIe protocol packet generated by the packet conversion module through conversion to another computing device, and send the PCIe protocol packet sent by the other computing device to the TileLink processing module 11, so as to generate a TileLink protocol packet after protocol conversion and send the TileLink protocol packet to the packet conversion module 12. Therefore, in the present solution, as long as the PCIe processing module 13 can implement the function of sending and receiving the PCIe protocol packet, the specific structure is not limited, for example: the PCIe processing module may include: a PCIe physical layer, a PCIe link layer, and a PCIe transport layer, and of course, the PCIe processing module may also only include the PCIe link layer and the PCIe transport layer, and the like, which is not particularly limited herein. As shown in fig. 2, the PCIe processing module 13 connected to the right side of the message conversion module includes a PCIe Trans layer, a PCIe Link layer, and a PCIe Phy layer.
It can be understood that the memory access interface module in the present solution belongs to an improvement on an interface architecture, as long as the TileLink processing module 11, the message conversion module 12, and the PCIe processing module 13 can implement corresponding functions, see fig. 3, which is an overall structural schematic diagram of the memory access interface module provided for the embodiment of the present invention, and in fig. 3, only the memory access interface module includes: the five-layer structure of TileLink protocol layer 11, message conversion module 12, PCIe transport layer 131, PCIe link layer 132, and PCIe physical layer 133 is described as an example, that is, a composite memory access interface module designed by TileLink protocol, PCIe protocol and specification is used, which is within the protection scope of the present invention.
In summary, in the scheme, a novel memory access interface module of TileLink over PCIe can be realized through a physical layer, a link layer, a transport layer and a TileLink protocol layer based on PCIe, and the memory access interface module adapts to the message formats of the link layer and the physical layer of PCIe, so that the memory access interface module conforms to the message format and specification of the TileLink protocol, adjusts the packet form of the message, and realizes the transmission of the TileLink message in the physical layer, the link layer and the transport layer channel of PCIe. The memory access interface module can be applied to equipment such as a RISC-V processor, a PCIe acceleration card and the like, and provides an effective interconnection scheme for the future ecological construction of the RISC-V.
Based on the foregoing embodiments, in this embodiment, a computing device is further disclosed, where the computing device includes the memory access interface module described in any of the foregoing embodiments; the computing equipment is used for realizing the interconnection and the memory access function with other computing equipment through the memory access interface module.
In this embodiment, the computing device may be a RISC-V processor.
In the memory access interface module in the scheme, the physical layer, the link layer and the transmission layer of the interface are designed according to PCIe physical layer and link layer specifications, and the main purpose is to make compatibility with the most mainstream interface at present from the aspects of physical interface and electrical characteristics, and make compatible support for the existing memory access equipment through minimum modification. Moreover, the memory access interface module is mainly a processor facing to a RISC-V instruction set, therefore, a TileLink protocol is adopted by a protocol layer to support the access to the Cache/memory of the RISC-V processor, and the complete compatibility of the Cache Line state is realized.
Specifically, when the memory access interface module is applied to the internal implementation of the RISC-V processor, the specific application mode is as follows:
step 1: the TileLink over PCIe access interface is designed for RISC-V processors. The memory access interface design method can be determined according to the five-layer structure shown in fig. 3, and a corresponding PCIe physical layer (Serdes), a PCIe link layer, and a PCIe transport layer are designed, and a packet conversion module from the TileLink protocol to the PCIe protocol is designed, and the TileLink protocol layer is realized according to the TileLink protocol design.
Step 2: and implementing a TileLink Over PCIe memory access interface in the processor. And instantiating the designed memory access interface in the processor design according to the actual required number of the processor, and carrying out engineering realization along with the processor.
Through the two steps, the RISC-V processor with the TileLink Over PCIe access interface can be realized.
It should be noted that in this embodiment, memory access interface modules of different computing devices are interconnected in a point-to-point manner, so that if a computing device needs to be interconnected with multiple other computing devices, the computing device needs to set multiple memory access interfaces, that is to say: the number of the memory access interface modules in the computing device is the same as that of other computing devices needing to be connected. Referring to fig. 4, a schematic structural diagram of a RISC-V processor disclosed in the embodiments of the present invention is shown, where Control is a Control module, Execute is an execution module, TileLink over PCIe is an access interface module, D-Cache/I-Cache is two caches of the RISC-V processor, and each module and Cache in the RISC-V processor are interconnected through a bus.
Further, in this embodiment, only the memory access interface module is applied to the RISC-V processor for example, and when actually used, the memory access interface module may also be applied to other computing devices that need to access memory, for example: the computing device may be a PCIe acceleration card, a GPU (graphics processing unit), and the like.
In summary, in the computing device in this embodiment, the memory access interface designed based on the TileLink protocol and multiplexing the PCIe physical layer, the link layer, and the transport layer is provided, and the memory access interface may be oriented to the RISC-V novel processor architecture, and also has the characteristic of high compatibility of the PCIe interface, and may be widely applied to computing devices such as a RISC-V processor and a PCIe accelerator card, and in scenarios such as high-speed signal transmission. By the mode, the problem that no inter-chip interconnection or interface providing access and storage functions exists in the current RISC-V ecology can be solved, and an effective interconnection scheme is provided for the future ecological construction of RISC-V.
Based on the above embodiments, in this embodiment, a data transmission method based on a memory access interface module is disclosed, where the memory access interface module includes: the system comprises a TileLink processing module, a message conversion module and a PCIe processing module; the data transmission method comprises the following steps:
the message conversion module repackages the TiLELink protocol message sent by the TiLELink processing module according to a PCIe protocol, and sends the generated PCIe protocol message to the PCIe processing module;
and the message conversion module repackages the PCIe protocol message sent by the PCIe processing module according to the TileLink protocol and sends the generated TileLink protocol message to the TileLink processing module.
In this embodiment, the TileLink processing module may include: a TileLink protocol layer, the PCIe processing module may include: a PCIe physical layer, a PCIe link layer, and a PCIe transport layer.
In summary, in the present solution, a composite memory access interface module integrating a TileLink protocol and a PCIe protocol is disclosed, which can implement message conversion between the TileLink protocol and the PCIe protocol, and can be applied to various computing devices in a memory access scenario to implement interconnection and memory access functions between the computing devices. The scheme can solve the problem that no inter-chip interconnection or interface providing access and storage functions exists in the current RISC-V ecology, and provides an effective interconnection scheme for the future ecological construction of RISC-V.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
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