CN114153263A - LVDS transmitter - Google Patents

LVDS transmitter Download PDF

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Publication number
CN114153263A
CN114153263A CN202111444428.1A CN202111444428A CN114153263A CN 114153263 A CN114153263 A CN 114153263A CN 202111444428 A CN202111444428 A CN 202111444428A CN 114153263 A CN114153263 A CN 114153263A
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transistor
coupled
common mode
resistor
voltage
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CN202111444428.1A
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CN114153263B (en
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王桂玲
王荣
谭信辉
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Hangzhou Hikmicro Sensing Technology Co Ltd
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Hangzhou Hikvision Digital Technology Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

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  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The application provides an LVDS transmitter, relates to the technical field of electronics, and is used for solving the problem that power consumption is large in the LVDS transmitter. The LVDS transmitter includes: the output end of the first common-mode feedback circuit is coupled with the first input end of the driving circuit; the first common-mode feedback circuit includes: the circuit comprises a first operational amplifier, a first transistor, a first resistor, a second resistor and a second transistor, wherein the first transistor, the first resistor, the second resistor and the second transistor are sequentially coupled in series between a power supply end and a ground end; the first resistor and the second resistor are coupled to a first node, a first input terminal of the first operational amplifier is coupled to the first node, a second input terminal of the first operational amplifier is used for receiving a first reference voltage, an output terminal of the first operational amplifier is coupled with a gate of the first transistor and an output terminal of the first common mode feedback circuit, and a gate of the second transistor is used for receiving a bias voltage.

Description

LVDS transmitter
Technical Field
The application relates to the technical field of electronics, in particular to an LVDS transmitter.
Background
Currently, in order to stabilize a common-mode voltage at an output terminal of a low-voltage differential signal (LVDS) driving circuit, a common-mode feedback (CMFB) circuit is usually added to the LVDS driving circuit.
Fig. 1 is a schematic structural diagram of an LVDS transmitter provided in the prior art, where the LVDS transmitter includes: a driver circuit and a CMFB circuit coupled to each other. The drive circuit is used for outputting a differential voltage V1And V2The CMFB circuit is used for receiving the differential voltage V1And V2And according to the differential voltage V1And V2Determining a common-mode voltage VCFurther based on the common mode voltage VCOutput feedback voltage VF. Wherein, this drive circuit includes: 6 transistors and denoted M1To M6Transistor M1Coupled to a power supply terminal (VDD) and a first node P1Between, transistor M6Coupled to a second node P2And Ground (GND), transistor M1Is coupled to VDD, transistor M6Is coupled to GND, transistor M2And a transistor M4Is coupled in series to a first node P1And a second node P2Between, transistor M3And a transistor M5Is coupled in series to a first node P1And a second node P2First differential output terminal and transistor M3Is coupled to the source of the transistor M, and a second differential output terminal is coupled to the transistor M2Is coupled to the source of transistor M1Can be used to receive a bias voltage Ve, transistor M2Gate of (D) and transistor M5Respectively for receiving a first control signal C1Transistor M3Gate of (D) and transistor M4Respectively for receiving a second control signal C2Transistor M6The grid of (2) can be used for receiving a feedback voltage VF. The CMFB circuit includes: a first resistor R1A second resistor R2And an operational amplifier OP. A first resistor R1And a second resistor R2A first resistor R coupled in series between the first and second differential output terminals1And a second resistor R2Coupled to the node P3, the voltage at the node P3 is a common mode voltage VCThe negative pole of the operational amplifier OP is used for receiving the common-mode voltage VCThe positive pole of the operational amplifier OP is used for receiving a reference voltage VBG. In particular, the transistor M is operated in the driving circuit1And a transistor M6Are all current sources. T is1At the moment, the first control signal C1Can be used for controlling the transistor M2Hejing (Hejing)Body tube M5On, the second control signal C2Can be used for controlling the transistor M3And a transistor M4Turning off, at the moment, the first differential output end and the second differential output end output a first differential voltage V11And V12The second resistor R2And the first resistor R1According to the first differential voltage V11And V12Determining a first common mode voltage VC1The positive pole of the operational amplifier OP receives the first common mode voltage VC1And applying the first common mode voltage VC1And a reference voltage VBGAfter comparison, the feedback voltage V is outputFTransistor M6The grid electrode receives the feedback voltage VF；T2At the moment, the first control signal C1Can be used for controlling the transistor M2And a transistor M5Off, the second control signal C2Can be used for controlling the transistor M3And a transistor M4Is turned on due to the transistor M6The grid electrode receives the feedback voltage VFThe feedback voltage VFChange-over transistor M6Further changes the current in the driving circuit, and the first differential output terminal and the second differential output terminal output the second differential voltage V21And V22The first resistor R1And the second resistor R2According to the second differential voltage V21And V22Determining the second common mode voltage VC2. The LVDS transmitter changes the transistor M by the feedback voltage of the CMFB circuit6The grid voltage of the driving circuit is further changed, so that the purpose of stabilizing the common mode voltage is achieved.
However, in the LVDS transmitter, the current in the CMFB circuit is the same as the current in the driving circuit, which causes a large power consumption in the CMFB circuit if the current in the CMFB circuit is too large, and the common mode voltage cannot be effectively adjusted in a short time if the current in the CMFB circuit is too small; in addition, the first resistor and the second resistor have large resistance values, usually above kilo-ohm (K Ω) magnitude, so that when the first resistor and the second resistor are integrated on a chip, a large amount of chip area is occupied.
Disclosure of Invention
The application provides a low-voltage differential signal LVDS transmitter, which is used for solving the problem of large power consumption in the LVDS transmitter.
In order to achieve the purpose, the technical scheme is as follows:
in a first aspect, an LVDS transmitter is provided that includes a first common-mode feedback circuit and a driving circuit, an output of the first common-mode feedback circuit being coupled to a first input of the driving circuit; the first common-mode feedback circuit includes: the circuit comprises a first operational amplifier, a first transistor, a first resistor, a second resistor and a second transistor, wherein the first transistor, the first resistor, the second resistor and the second transistor are sequentially coupled in series between a power supply end and a ground end; wherein the first resistor and the second resistor are coupled to a first node, a first input terminal of the first operational amplifier is coupled to the first node, a second input terminal of the first operational amplifier is configured to receive a first reference voltage, an output terminal of the first operational amplifier is coupled to a gate of the first transistor and an output terminal of the first common mode feedback circuit, and a gate of the second transistor is configured to receive a bias voltage; the drive circuit includes: a third transistor, a differential circuit, and a fourth transistor coupled in series in this order between the power terminal and the ground terminal; the grid electrode of the third transistor is coupled with the first input end of the driving circuit, and the differential output end of the differential circuit is used as the differential output end of the driving circuit for outputting differential voltage; the current of the third transistor is larger than that of the first transistor, and a linear relation exists between the current of the third transistor and that of the first transistor.
In the above technical solution, the current of the third transistor is larger than the current of the first transistor and has a linear relationship with the current of the first transistor, that is, the current of the driving circuit is larger than the current of the first common mode feedback circuit and has a linear relationship with the current of the first common mode feedback circuit, the first common mode feedback circuit generates a first common mode voltage at a first node according to the bias voltage and outputs a first feedback voltage according to the first common mode voltage and the first reference voltage, the driving circuit is configured to generate a differential voltage according to the current (large current) of the driving circuit and receive the first feedback voltage, the differential voltage is configured to determine a second common mode voltage, the first feedback voltage is configured to adjust the differential voltage to stabilize the second common mode voltage, so as to quickly stabilize the second common mode voltage, and the current in the LVDS transmitter in which two resistors are connected in series (the current in the CMFB circuit is the same as the current in the driving circuit, current in the driving circuit must be increased in order to quickly stabilize the common mode voltage in the driving circuit), the current in the common mode feedback circuit is small, and therefore, the power consumption in the common mode feedback circuit is small, so that the power consumption in the common mode feedback circuit is reduced while the second common mode voltage is quickly stabilized; on the other hand, the first resistor and the second resistor have small resistance values, typically several hundred ohms (Ω), and occupy a small area of a chip when the first resistor and the second resistor are integrated on the chip.
In one possible implementation form of the first aspect, the third transistor is larger in size than the first transistor. In the above possible implementation manner, when the third transistor and the first transistor are connected in common, the third transistor and the first transistor constitute a current mirror, so that the current in the third transistor is greater than the current in the first transistor, and the current in the third transistor and the current in the first transistor are in a multiple relationship, thereby increasing the current in the third transistor.
In one possible implementation manner of the first aspect, the LVDS transmitter further includes: the input end of the second common mode feedback circuit is coupled with the output end of the first common mode feedback circuit, and the output end of the second common mode feedback circuit is coupled with the second input end of the driving circuit; the second common mode feedback circuit includes: a fifth transistor, a third resistor, a fourth resistor and a sixth transistor sequentially coupled in series between the power supply terminal and the ground terminal; the third resistor and the fourth resistor are coupled to a second node, the first input terminal of the second operational amplifier is coupled to the second node, the second input terminal of the second operational amplifier is configured to receive a second reference voltage, the output terminal of the second operational amplifier is coupled to the gate of the sixth transistor and the output terminal of the second common mode feedback circuit, and the gate of the fifth transistor is coupled to the input terminal of the second common mode feedback circuit. In the above possible implementation manner, the second common mode feedback circuit receives the first feedback voltage output by the first common mode feedback circuit, may generate a third common mode voltage at a second node according to the first feedback voltage, and output a second feedback voltage according to the third common mode voltage and a second reference voltage, where the second feedback voltage is used to adjust the differential voltage to stabilize the second common mode voltage, and the first common mode feedback circuit and the second common mode feedback circuit are used to jointly stabilize the second common mode voltage, thereby improving a speed of stabilizing the second common mode voltage; on the other hand, the third resistor and the fourth resistor have small resistance values, typically several hundred ohms (Ω), and when the third resistor and the fourth resistor are integrated on a chip, the occupied area of the chip is small.
In one possible implementation manner of the first aspect, the size of the fourth transistor is larger than the size of the sixth transistor. In the above possible implementation manner, when the fourth transistor and the sixth transistor are connected in common gate, the fourth transistor and the sixth transistor constitute a current mirror, so that a current in the fourth transistor is greater than a current in the sixth transistor, and the current in the fourth transistor and the current in the sixth transistor are in a multiple relationship, thereby increasing the current in the sixth transistor.
In one possible implementation manner of the first aspect, the differential circuit and the third transistor are coupled to a third node, the differential circuit and the fourth transistor are coupled to a fourth node, and the differential circuit further includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, the seventh transistor and the eighth transistor being coupled between the third node and the differential output terminal, respectively, the ninth transistor and the tenth transistor being coupled between the differential output terminal and the fourth node, respectively. In the foregoing possible implementation manner, when the driving circuit receives the serial signal, the driving circuit may be configured to convert the serial signal into a parallel LVDS signal and output the parallel LVDS signal, where the LVDS signal may improve a transmission rate of the signal during transmission.
In one possible implementation form of the first aspect, the bias voltage is a fixed voltage. In the above possible implementation manner, when the gate of the second transistor receives the bias voltage, the second transistor is made to be a constant current source, that is, the current in the first common mode feedback circuit is a constant value.
In one possible implementation form of the first aspect, the second transistor and the fourth transistor are constant current sources. In the above possible implementation manner, the second transistor and the fourth transistor are constant current sources, so that stability of the second transistor and the fourth transistor is ensured.
In a second aspect, a chip is provided, which includes an LVDS transmitter provided in the first aspect or any one of the possible implementations of the first aspect.
In a third aspect, an LVDS interface is provided, in which an LVDS transmitter is provided, and the LVDS transmitter is the LVDS transmitter provided in the first aspect or any one of the possible implementations of the first aspect.
In a fourth aspect, a terminal device is provided, where the terminal device includes an input/output interface, and the input/output interface includes an LVDS transmitter, and the LVDS transmitter is the LVDS transmitter provided in the first aspect or any possible implementation manner of the first aspect.
It can be understood that the chip, the LVDS interface, and the terminal device provided above all include all the contents of the LVDS transmitter provided above, and therefore, the beneficial effects achieved by the chip, the LVDS interface, and the terminal device may refer to the beneficial effects of the LVDS transmitter provided above, and are not described herein again.
Drawings
Fig. 1 is a schematic structural diagram of an LVDS transmitter provided in the prior art;
fig. 2 is a schematic structural diagram of a terminal device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an LVDS transmitter according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another LVDS transmitter according to an embodiment of the present application.
Detailed Description
In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b and c can be single or multiple.
The embodiments of the present application use the words "first" and "second" to distinguish between objects having similar names or functions, and those skilled in the art will appreciate that the words "first" and "second" do not limit the number or order of execution. The term "coupled" is used to indicate electrical connection, including direct connection through wires or connections, or indirect connection through other devices. Thus, "coupled" should be considered as an electronic communication connection in a broad sense.
The transistors in the embodiments of the present application may refer to Metal Oxide Semiconductor (MOS), the types of the transistors may include N-type metal oxide semiconductor (NMOS) transistors and P-type metal oxide semiconductor (PMOS) transistors, the transistors may also be other types of transistors, such as gallium nitride type transistors, and the transistors in the embodiments of the present application are described by taking NMOS as an example. In addition, two transistors coupled in series herein may mean that a source of a first transistor is connected to a drain of a second transistor, and both the drain of the first transistor and the source of the second transistor are connected to an external circuit.
The technical solution provided in the embodiment of the present application may be applied to various terminal devices including a low-voltage differential signaling (LVDS) transmitter, where the terminal devices may include, but are not limited to, a personal computer, a server computer, a mobile device (such as a mobile phone, a tablet computer, a media player, etc.), a wearable device, an in-vehicle device, a consumer terminal device, a mobile robot, an unmanned aerial vehicle, and the like. The specific structure of the terminal device will be described below.
Fig. 2 is a schematic structural diagram of a terminal device according to an embodiment of the present application, where the terminal device is described by taking a notebook computer as an example. As shown in fig. 2, the terminal device may include: memory 201, processor 202, sensor component 203, multimedia component 204, and input/output interface 205.
Wherein, the memory 201 can be used for storing data, software programs and software modules; the system mainly comprises a storage program area and a storage data area, wherein the storage program area can store an operating system and an application program required by at least one function, such as a sound playing function or an image playing function; the storage data area may store data created according to the use of the terminal device, such as audio data, image data, table data, or the like. In addition, the terminal device may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
The processor 202 is a control center of the terminal device, connects various parts of the entire device by using various interfaces and lines, and performs various functions of the terminal device and processes data by running or executing software programs and/or software modules stored in the memory 201 and calling data stored in the memory 201, thereby performing overall monitoring of the terminal device. Alternatively, the processor 202 may include one or more processing units, for example, the processor 202 may include a Central Processing Unit (CPU), an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a controller, a video codec, a Digital Signal Processor (DSP), a baseband processor and/or a neural Network Processor (NPU), and the like. The different processing units may be separate devices or may be integrated into one or more processors.
The sensor component 203 includes one or more sensors for providing various aspects of status assessment for the terminal device. The sensor component 203 may include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor, and acceleration/deceleration, orientation, on/off state of the terminal device, relative positioning of components, or temperature change of the terminal device may be detected by the sensor component 203. In addition, the sensor assembly 203 may further include a light sensor, and the sensor assembly 203 may further include a light sensor for detecting light of the surrounding environment.
The multimedia component 204 is a screen providing an output interface between the terminal device and the user, and the screen may be a touch panel, and when the screen is a touch panel, the screen may be implemented as a touch screen to receive an input signal from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In addition, the multimedia component 204 may further include at least one camera, for example, the multimedia component 204 may include a front camera and/or a rear camera. When the terminal device is in an operation mode, such as a shooting mode or a video mode, the front camera and/or the rear camera can receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The i/o interface 205 provides an interface between the processor 202 and a peripheral interface module, which may be, for example, a Universal Serial Bus (USB) device. In an embodiment of the present application, the input/output interface 205 may include an LVDS transmitter provided herein for converting a received serial signal into a parallel LVDS signal.
Although not shown, the terminal device may further include an audio component, a communication component, and the like, for example, the audio component includes a microphone, and the communication component includes a wireless fidelity (WiFi) module or a bluetooth module, and the like, which is not described herein again. Those skilled in the art will appreciate that the terminal device configuration shown in fig. 2 is not intended to be limiting and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
Fig. 3 is a schematic structural diagram of an LVDS transmitter according to an embodiment of the present application, where the LVDS transmitter includes a first common-mode feedback circuit 301 and a driving circuit 302, an output end of the first common-mode feedback circuit 301 is coupled to a first input end of the driving circuit 302; the first common mode feedback circuit 301 includes: a first operational amplifier OP1, and a first transistor M coupled in series between a power supply terminal (VDD) and a ground terminal (GND) in that order1A first resistor R1A second resistor R2And a second transistor M2(ii) a Wherein the first resistor R1And the second resistor R2Coupled to a first node P1A first input terminal of the first operational amplifier OP1 is coupled to the first node P1A second input terminal of the first operational amplifier OP1 for receiving a first reference voltage VB1An output terminal of the first operational amplifier OP1 and the first transistor M1Is coupled to the output of the first common mode feedback circuit 301, the second transistor M2For receiving a bias voltage Ve。
The operation of the first common mode feedback circuit 301 will be described below.
Specifically, in one duty cycle T, the second transistor M2Can be used for receiving a bias voltage VeSo that the second transistor M2When the second transistor M is turned on2Is a constant current source. The bias current passes through the first transistor M1A first resistor R1A second resistor R2And a second transistor M2Then, the first output end outputs a first common mode voltage VC1The operational amplifier OP1 receives the first common mode voltage VC1And applying the first common mode voltage VC1And the first reference voltage VB1Comparing and outputting the first feedback voltage VF1First transistor M1Can be used for receiving the first feedback voltage VF1. The first transistor M1The first resistor R1The first common mode voltage VC1And the operational amplifier OP1 form a first closed loop negative feedback loop.
Wherein, when designing the circuit, the bias voltage V can be seteSuch that the bias current is equal to a first threshold value, which may be 350 microamperes (μ a) in practical applications, for example.
In addition, in designing the circuit, the appropriate resistance can be selected so that the first resistance R is1And the second resistor R2A first common mode voltage V betweenC1Is equal to the first reference voltage VB1For example, the first reference voltage VB1May be 1.25V.
In another possible embodiment, as shown in fig. 4, the LVDS transmitter further includes: an input terminal of the second common mode feedback circuit 303 is coupled to an output terminal of the first common mode feedback circuit 301, and an output terminal of the second common mode feedback circuit 303 is coupled to a second input terminal of the driving circuit 302; the second common mode feedback circuit 303 includes: a second operational amplifier OP2, and a fifth transistor M sequentially coupled in series between the (VDD) and the (GND)5A third resistor R3A fourth resistor R4And a sixth transistor M6(ii) a Wherein the third resistor R3And the fourth resistor R4Coupled to a second node P2A first input terminal of the second operational amplifier OP2 is coupled to the second node P2A second input terminal of the second operational amplifier OP2 is used for receiving a second reference voltage VB2An output terminal of the second operational amplifier OP2 and the sixth transistor M6Is coupled to an output of the second common mode feedback circuit 303, the fifth transistor M5Is coupled to an input of the second common mode feedback circuit 303.
The specific operation of the second common mode feedback circuit 303 will be described below.
Specifically, in one operation period T, the fifth transistor M5Can be used for receiving a first feedback voltage VF1So that the fifth transistor M5And generates a bias current through the fifth transistor M5A sixth transistor M6A third resistor R3And a fourth resistor R4Then, the second node P is enabled2To generate an output third common mode voltage VC3The second operational amplifier OP2 receives the third common mode voltage VC3And applying the third common mode voltage VC3And the second reference voltage VB2Comparing and outputting the second feedback voltage VF2The sixth transistor M6Can be used for receiving the second feedback voltage VF2. The sixth transistor M6The fourth resistor R4, the second common mode voltage VC2And the second operational amplifier OP2 form a second closed loop negative feedback loop.
It should be noted that, when designing the circuit, an appropriate resistor may be selected so that the third resistor R is used3And the fourth resistor R4Third common mode voltage V in betweenC3Is equal to the second reference voltage VB2For example, the second reference voltage VB2May be 1.25V.
The driving circuit 302 in fig. 3 and 4 will be described.
The driving circuit 302 includes: a third transistor M sequentially coupled in series between the (VDD) and the (GND)3 Differential circuit 02 and fourth transistor M4(ii) a Wherein the third transistor M3Is coupled to a first input of the driver circuit 302, and a differential output of the differential circuit 02 is used as a differential output with the driver circuit 302 for outputting a differential voltage V1And V2(ii) a Wherein the differential circuit02 and the third transistor M3Coupled to a third node P3The differential circuit 02 and the fourth transistor M4Coupled to a fourth node P4The driving circuit 302 further includes: seventh transistor M7An eighth transistor M8The ninth transistor M9And a tenth transistor M10The seventh transistor M7And the eighth transistor M8Are respectively coupled to the third nodes P3And the differential output terminal, the ninth transistor M9And the tenth transistor M10Coupled to the differential output terminal and the fourth node P respectively4In the meantime.
The operation of the driving circuit 302 will be described below. The fifth transistor M is operated by the driving circuit 3023And a tenth transistor M4Are all current sources. In one operation period T, the operation process of the driving circuit 302 may include two phases.
In particular, T1Time of day, first control signal C1Control the seventh transistor M7And the ninth transistor M9On, the second control signal C2Control the eighth transistor M8And the tenth transistor M10Turn off, the first differential output terminal and the second differential output terminal output a differential voltage V11And V12. Wherein the differential voltage V11And V12Are the same, are out of phase by 180 deg., and at this time V11At a high level, V12Is low.
T2Time of day, first control signal C1Control the seventh transistor M7And the ninth transistor M9Off, second control signal C2Control the eighth transistor M8And the tenth transistor M10Conducting, the first differential output terminal and the second differential output terminal output a differential voltage V21And V22. The differential voltage V11And V12Are the same, are out of phase by 180 deg., and at this time V21At a high level, V22Is low.
The process of determining the second common mode voltage according to the differential voltage is the same as that of the prior art, and is not described herein again.
Further, the third transistor M3Is larger than the first transistor M1And with the first transistor M1There is a linear relationship between the currents.
Further, the third transistor M3Is larger than the first transistor M1Of the fourth transistor M, the fourth transistor M4Is larger than the tenth transistor M10I.e. the third transistor M3Is larger than the first transistor M1The size ratio of the fourth transistor M4Is larger than the tenth transistor M10The size ratio of (a).
Wherein the size ratio is the ratio of the width to the length of the transistor, e.g. the third transistor M3Is the third transistor M3And the third transistor M3The ratio of the lengths of (a) and (b). In practical application, the third transistor M3May be the first transistor M 110 times the size ratio. In this situation, the third transistor M3And the first transistor M1When the common gate is connected, the third transistor M3And the first transistor M1Forming a current mirror, i.e. the third transistor M3With the first transistor M1The current in (a) is in a multiple relation, the third transistor M3Is the first transistor M1The current in the capacitor is amplified according to a certain proportion.
In the circuit design stage of the LVDS transmitter shown in fig. 4, the appropriate resistors can be selected to drive the second common-mode voltage V in the circuit 302C2And a first node P in the first common mode feedback circuit 3011A first common mode voltage VC1And a second node P in the second common mode feedback circuit 3032A third common mode voltage VC3And (7) corresponding. I.e. the second common mode voltage V in the driving circuit 302C2With the first common mode voltage V in the first common mode feedback circuit 301C1And a secondSecond node P in common mode feedback circuit 3032A third common mode voltage VC3Are equal, it is possible to stabilize the first common mode voltage V in the first common mode feedback circuit 301C1And a second node P in the second common mode feedback circuit 3032A third common mode voltage VC3To stabilize the second common mode voltage V in the driving circuit 302C2。
In one possible embodiment, the LVDS transmitter includes a first common-mode feedback circuit 301 and a driving circuit 302, in this case, the structure of the LVDS transmitter is as shown in fig. 3, and the first common-mode feedback circuit 301 is at a first node P according to the bias current (small current)1To generate a first common mode voltage VC1The first operational amplifier OP1 is based on the first common-mode voltage VC1And a first reference voltage VB1Outputting a first feedback voltage VF1The first common mode feedback circuit 301 receives the first feedback voltage VF1And through the first feedback voltage VF1Adjusting the first common mode voltage VC1To stabilize the first common mode voltage VC1Due to the first common mode voltage VC1And the second common mode voltage VC2Are in the same trend, thereby stabilizing the second common mode voltage VC2In the process, the bias current is a small current, i.e. the current in the first common mode feedback circuit 301 is a small current (350 μ a in practical application), and compared with the LVDS transmitter in fig. 1 (in order to quickly stabilize the common mode voltage in the driving circuit, the current in the driving circuit must be increased), the current in the first common mode feedback circuit 301 is small, so the power consumption in the first common mode feedback circuit 301 is small, thereby quickly stabilizing the second common mode voltage VC2Meanwhile, the power consumption in the first common mode feedback circuit 301 is reduced; on the other hand, the first resistance R is comparable to the resistance in the LVDS transmitter in fig. 1 (typically above the order of K Ω)1And the second resistor R1Is small, typically a few hundred ohms (omega), thereby placing the first resistor R in contact with the ground1And the second resistor R1When the chip is integrated on a chip, the occupied area of the chip is small.
In another possible embodimentThe LVDS transmitter includes a driving circuit 302 and a second common mode feedback circuit 303, and in this case, the structure of the LVDS transmitter is a partial structure shown in fig. 4. Third transistor M in LVDS transmitter in this configuration3For receiving a bias voltage Va, a third transistor M3As a current source, a fifth transistor M5The gate is used for receiving the bias voltage Ve, and the advantageous effects of the LVDS transmitter under this structure are similar to those of the LVDS transmitter in fig. 3, and are not described herein again.
In yet another possible embodiment, the LVDS transmitter includes a driving circuit 302, a first common mode feedback circuit 301, and a second common mode feedback circuit 303, and the LVDS transmitter is configured as shown in fig. 4, and the LVDS transmitter simultaneously adjusts a second common mode voltage in the driving circuit through the first common mode feedback circuit 301 and the second common mode feedback circuit 303, so as to stabilize the second common mode voltage and simultaneously increase a speed at which the second common mode voltage is stabilized.
It should be noted that the first common mode voltage VC1And the third common mode voltage VC3The regulation process is similar, and the first common mode voltage V is usedC1For example, the first common mode voltage V is adjusted for a first closed loop negative feedback loopC1The procedure of (2) is explained.
When the first common mode voltage VC1When the voltage rises, the first feedback voltage V output by the first operational amplifier OP1F1Decrease the first feedback voltage VF1Satisfies formula (1):
first feedback voltage VF1First reference voltage VB1-a first common mode voltage VC1) Magnification times (1)
Due to the first transistor M1Is proportional to the difference between the gate voltage and the source voltage, the first feedback voltage VF1Is reduced to flow through the first transistor M1Is constant, the first transistor M is turned on1Source voltage V ofSAnd decreases. Due to the first common mode voltage VC1Satisfies formula (2):
a first common mode voltage VC1Source electrodeVoltage VS-IR1 (2)
Wherein the current I and the first resistance R1When the source voltage V is constantSWhen it is reduced, the first common mode voltage V is reducedC1And decreases.
According to the above-mentioned regulation process, when the first common mode voltage V is appliedC1When the voltage rises, the voltage is adjusted by a first closed loop negative feedback loop, so that the originally raised first common mode voltage V is enabled to be increasedC1Reduce to stabilize the first common mode voltage VC1The purpose of (1).
Due to the first transistor M1And the third transistor M3Are connected in common, so that the first transistor M1And the third transistor M3Forming a linear current mirror, i.e. the third transistor M3With the first transistor M1Is in a multiple relation and flows through the third transistor M3Current of
Figure BDA0003384327930000081
Satisfies formula (3):
Figure BDA0003384327930000082
wherein the content of the first and second substances,
Figure BDA0003384327930000083
is a first transistor M1Current of medium, Q1Is the third transistor M3Size ratio of (2), Q2Is a first transistor M1Size ratio of (2), Q1Satisfies the formula (4), Q2Satisfies formula (5):
Figure BDA0003384327930000084
Figure BDA0003384327930000085
Figure BDA0003384327930000086
is the third transistor M3The width of (a) is greater than (b),
Figure BDA0003384327930000087
is the third transistor M3The length of (a) of (b),
Figure BDA0003384327930000088
is a first transistor M1The width of (a) is greater than (b),
Figure BDA0003384327930000089
is a first transistor M1Length of (d). In practical application, the third transistor M3May be the first transistor M1Is 10 times the size ratio of (A), i.e. Q1And Q2The ratio of (A) to (B) is 10. When the first transistor M is turned on1When the current in (1) is 350 μ A, the third transistor M can be obtained from the formula (3)3Current of
Figure BDA00033843279300000810
And 3.5 milliamps (mA). Therefore, when the first transistor M is used1When the current is fixed, the third transistor M can be obtained from the equation (3)3The current in (c) is also fixed. In the same way, when the sixth transistor M is used6When the current in the fourth transistor M is fixed, the fourth transistor M4The current in (c) is also fixed.
When the second common mode voltage increases, the first common mode voltage also increases, the output voltage of the first operational amplifier OP1 decreases, and the fifth transistor M decreases5Due to the fifth transistor M5Is a fixed value, so the third transistor M3The second common mode voltage is reduced, i.e., stabilized.
In the LVDS transmitter according to an embodiment of the present application, a current of a driving circuit is larger than a current of a common mode feedback circuit, and a linear relationship exists between the current of the common mode feedback circuit and the common mode feedback circuit, the common mode feedback circuit generates a first common mode voltage according to the current (small current) of the common mode feedback circuit and outputs a feedback voltage according to the first common mode voltage, the driving circuit is configured to generate a differential voltage according to the current (large current) of the driving circuit and receive the feedback voltage, the differential voltage is used to determine a second common mode voltage, the feedback voltage is used to adjust the differential voltage to stabilize the second common mode voltage, so as to rapidly stabilize the second common mode voltage, compared with the LVDS transmitter in which two resistors are connected in series in fig. 1 (in order to rapidly stabilize the common mode voltage in the driving circuit, the current in the driving circuit must be increased), the current in the common mode feedback circuit is small, so that power consumption in the common mode feedback circuit is small, thereby reducing power consumption in the common mode feedback circuit while rapidly stabilizing the second common mode voltage.
Embodiments of the present application also provide a chip including an LVDS transmitter, which may include the LVDS transmitter provided in fig. 3 or fig. 4.
Embodiments of the present application also provide an LVDS interface, which may include the LVDS transmitter provided in fig. 3 or fig. 4.
An embodiment of the present application further provides a terminal device, where the terminal device includes an input/output interface, and the input/output interface may include the LVDS transmitter provided in fig. 3 or fig. 4.
It should be noted that, for the relevant description of the LVDS transmitter, reference may be made to the relevant description of the LVDS transmitter provided above, and details of the embodiments of the present application are not repeated herein.
Finally, it should be noted that: the above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A low-voltage differential signaling (LVDS) transmitter is characterized by comprising a first common-mode feedback circuit and a driving circuit, wherein an output end of the first common-mode feedback circuit is coupled with a first input end of the driving circuit;
the first common-mode feedback circuit includes: the circuit comprises a first operational amplifier, a first transistor, a first resistor, a second resistor and a second transistor, wherein the first transistor, the first resistor, the second resistor and the second transistor are sequentially coupled in series between a power supply end and a ground end; wherein the first resistor and the second resistor are coupled to a first node, a first input terminal of the first operational amplifier is coupled to the first node, a second input terminal of the first operational amplifier is configured to receive a first reference voltage, an output terminal of the first operational amplifier is coupled to a gate of the first transistor and an output terminal of the first common mode feedback circuit, and a gate of the second transistor is configured to receive a bias voltage;
the drive circuit includes: a third transistor, a differential circuit, and a fourth transistor coupled in series in this order between the power terminal and the ground terminal; wherein a gate of the third transistor is coupled to the first input terminal of the driving circuit, and a differential output terminal of the differential circuit is used as a differential output terminal of the driving circuit for outputting a differential voltage;
wherein the current of the third transistor is larger than that of the first transistor, and a linear relation exists between the current of the third transistor and that of the first transistor.
2. The LVDS transmitter of claim 1, wherein a size of the third transistor is larger than a size of the first transistor.
3. The LVDS transmitter according to claim 1, further comprising: a second common mode feedback circuit, an input terminal of the second common mode feedback circuit being coupled to an output terminal of the first common mode feedback circuit, an output terminal of the second common mode feedback circuit being coupled to a second input terminal of the driving circuit;
the second common mode feedback circuit includes: a fifth transistor, a third resistor, a fourth resistor and a sixth transistor sequentially coupled in series between the power supply terminal and the ground terminal; wherein the third resistor and the fourth resistor are coupled to a second node, the first input terminal of the second operational amplifier is coupled to the second node, the second input terminal of the second operational amplifier is configured to receive a second reference voltage, the output terminal of the second operational amplifier is coupled to the gate of the sixth transistor and the output terminal of the second common mode feedback circuit, and the gate of the fifth transistor is coupled to the input terminal of the second common mode feedback circuit.
4. The LVDS transmitter of claim 3 wherein the size of the fourth transistor is larger than the size of the sixth transistor.
5. The LVDS transmitter of any one of claims 1-4, wherein the differential circuit and the third transistor are coupled to a third node, the differential circuit and the fourth transistor are coupled to a fourth node, the differential circuit further comprising: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, the seventh transistor and the eighth transistor being coupled between the third node and the differential output terminal, respectively, the ninth transistor and the tenth transistor being coupled between the differential output terminal and the fourth node, respectively.
6. The LVDS transmitter of claim 1, wherein the bias voltage is a fixed voltage.
7. The LVDS transmitter of claim 1, wherein the second transistor and the fourth transistor are constant current sources.
8. A chip characterized in that it comprises an LVDS transmitter according to any one of claims 1 to 7.
9. An LVDS interface, characterized in that the LVDS interface comprises an LVDS transmitter according to any one of claims 1 to 7.
10. An end device characterized in that the end device comprises an LVDS transmitter according to any one of claims 1 to 7.
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CN111865295A (en) * 2019-04-24 2020-10-30 烽火通信科技股份有限公司 Low-voltage differential signal transmitter

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001050596A1 (en) * 2000-01-06 2001-07-12 Thomson Licensing S.A. Voltage level translation circuits
US20100079172A1 (en) * 2008-09-29 2010-04-01 Fujitsu Microelectronics Limited Differential output circuit
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