CN114153257B - Two-way programmable Josephson junction array driving method and device - Google Patents
Two-way programmable Josephson junction array driving method and device Download PDFInfo
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Abstract
The invention provides a two-way programmable Josephson junction array driving method and a device thereof, wherein the driving method comprises the following steps: setting the sampling frequency f s Will program JosephQuantizing the target output voltage waveform of the Sensen junction array into a voltage value sequence; calculating the sequence of voltage values S 0 、S 1 ……Sn‑ 1 Voltage bias combinations corresponding to the voltage values; calculating the driving voltage combination of each driving channel of the programmable Josephson junction array driver according to the voltage bias combination; quantizing the driving voltage combination of each driving channel into a binary coding combination; sequentially inputting the binary coding combination into the digital-to-analog converters in each driving channel; synchronously triggering output driving voltage of each driving channel through a reference clock; and driving the programmable Josephson junction array by the driving voltage output by the digital-to-analog converter. The invention has the beneficial effects that: and the reference clock is used as a synchronous trigger signal to realize the high synchronism of the two paths of Josephson junction array driving currents.
Description
Technical Field
The invention relates to the technical field of circuit driving, in particular to a two-way synchronous programmable Josephson junction array driving method and a device thereof.
Background
In a programmable josephson quantum voltage reference device, the josephson junction arrays must be able to generate the dc quantum voltage described by the josephson effect, while ensuring that the driving currents of the respective sub-junction arrays remain synchronized. The Josephson junction array is generally formed by connecting more than ten to more than twenty sub-junction arrays in series, the driving current of each sub-junction array needs to keep high synchronism, the value of the driving current of each sub-junction array is different, and no method capable of realizing the quantum voltage required by the standard voltage and the current signal generated by the two-way Josephson junction array simultaneously exists in the prior art. Therefore, in order to ensure that the multi-path driving signals have high synchronism and prevent bias state of other sub-junction arrays from being abnormal due to bias state hysteresis of the other sub-junction arrays, a synchronous triggering and control system architecture based on a high-stability time base is needed to ensure the requirement of driving synchronism.
Disclosure of Invention
In order to solve the above problems in the prior art, the present application provides a dual-path programmable josephson junction array driving method and apparatus capable of ensuring that the driving currents of all the sub-junction arrays in the dual-path josephson junction array keep high synchronism.
Based on the above object, the present application provides a dual path programmable josephson junction array driving method for driving a dual path programmable josephson junction array, the dual path programmable josephson junction array including a first programmable josephson junction array and a second programmable josephson junction array, the driving method comprising:
setting the sampling frequency f s Quantizing a target output voltage waveform of the programmable Josephson junction array into a sequence of voltage values S 0 、S 1 ……S n-1 ；
Calculating a sequence of voltage values S 0 、S 1 ……S n-1 Voltage bias combination of each sub-junction array in the Josephson junction array corresponding to each voltage value;
calculating the driving voltage combination of each driving channel of the programmable Josephson junction array driver according to the voltage bias combination of each sub-junction array;
quantizing the driving voltage combination of each driving channel into a binary coding combination;
sequentially inputting the binary coding combination into the digital-to-analog converters in each driving channel;
synchronously triggering the digital-to-analog converters in each driving channel to output driving voltages corresponding to binary codes through a reference clock;
and converting the driving voltage output by the digital-to-analog converter into a driving current to drive the programmable Josephson junction array to output a target voltage.
Further, the voltage value sequence S0, S 1 ......S n-1 The quantization method comprises the following steps:
wherein u (i/f) s ) Represents the voltage value at the ith sampling point, ROUND is a rounding function, u LSB The voltage value which can be synthesized by the sub-junction array corresponding to the minimum effective bit in the programmable Josephson junction array.
Further, u LSB The expression of (a) is:
wherein N is the number of the Josephson junctions in the corresponding sub-junction array with the least significant bit, N is the quantization step number, f is the microwave frequency, K J The Josephson constant is 483597.9GHz/V.
Further, a sequence of voltage values S 0 、S 1 ……S n-1 The voltage bias combination of each sub-junction array in the Josephson junction array corresponding to each voltage value is expressed as:
wherein B is i，j Representing a sequence S of voltage values 0 、S 1 ……S n-1 Voltage value S of the ith sampling point i Required bias of j-th Josephson sub-junction arraySet state, B i，j Is one of 1, 0 and-1, which respectively represents positive bias, zero bias and negative bias.
Further, the combination of the driving voltages of the driving channels of the programmable josephson junction array driver is shown as follows:
wherein V i，j Representing a sequence S of voltage values 0 、S 1 ……S n-1 Voltage value S of the ith sampling point i Of the jth Josephson sub-junction array, V i，j Is calculated as follows
Wherein I b(i) Is the bias current on the ith segment of the sub-junction array, i is more than or equal to 1 and less than or equal to n-1; the R sub-junction array corresponds to the resistance value of the driving channel; n is i For the sub-junction matrix biased state, N i The number of the Josephson junctions contained in the i-th segment of the sub-junction array.
Further, the binary coding mode is offset binary coding or two's complement coding.
And further setting the phase difference of the output voltages of the two-way programmable Josephson junction arrays, and inputting the binary code combination into the digital-to-analog converters in the driving channels of the first programmable Josephson junction array and the second programmable Josephson junction array respectively according to the phase difference.
Based on the above object, the present application further provides a two-way programmable josephson junction array driving device, comprising:
the programmable Josephson junction array module is used for outputting quantum voltage and comprises a first programmable Josephson junction array module and a second programmable Josephson junction array module;
the driving module is used for driving the programmable Josephson junction array module and comprises a first driving module and a second driving module, the first driving module is used for driving the first programmable Josephson junction array module, the second driving module is used for driving the second programmable Josephson junction array module, and the first driving module and the second driving module both comprise a control end;
the waveform memory is used for storing binary codes corresponding to voltage values of all points in the voltage waveform to be output by the driving module;
the controller generates a driving voltage waveform of the driving module according to a target output voltage waveform of the programmable Josephson junction array, stores binary codes corresponding to voltage values of all points in the driving voltage waveform in the waveform memory, sequentially reads all groups of binary codes in the waveform memory and inputs the binary codes into the corresponding driving module;
the reference clock is used for outputting clock pulses, and the clock pulses are used for triggering the first driving module and the second driving module to synchronously read the binary codes sent by the control end;
the waveform memory is in communication connection with the controller, the output end of the controller is connected with the input end of the driving module, the output end of the driving module is connected with the programmable Josephson junction array module, and the output end of the reference clock is simultaneously connected with the control ends of the first driving module and the second driving module.
The microwave power amplifier is characterized by further comprising a microwave generating module, wherein the microwave generating module comprises a microwave signal generator and a microwave power amplifier, the output end of the microwave signal generator is connected with the input end of the microwave power amplifier, and the output end of the microwave power amplifier is simultaneously connected with the input ends of the first programmable Josephson junction array module and the second programmable Josephson junction array module.
Furthermore, the first driving module and the second driving module both comprise a plurality of driving branches, each driving branch comprises a digital-to-analog converter and a V/I converter which are connected in series, the digital-to-analog converters are connected with the output end of the controller, and the output ends of the V/I converters are correspondingly connected with the input ends of the programmable Josephson junction array modules.
Compared with the prior art, the invention has the following beneficial effects: the two-way synchronous programmable Josephson junction array driving method of the invention uses the reference clock as the synchronous trigger signal to ensure that all digital-to-analog converters synchronously output the driving voltage, thereby realizing the high synchronism of the two-way Josephson junction array driving current; meanwhile, the two-way synchronous programmable Josephson junction array driving device samples waveforms to be output, digitalizes sampling data into binary codes and stores the binary codes in a waveform memory, and sequentially sends the corresponding binary codes to corresponding digital-to-analog converters in the first programmable Josephson junction array module and the second programmable Josephson junction array module according to the set phase difference, so that the control of the phase difference between two-way outputs is realized.
Drawings
Fig. 1 is a flowchart of a method for driving a programmable josephson junction array according to an embodiment of the present invention.
Fig. 2 is a flow chart of another programmable josephson junction array driving method according to an embodiment of the present invention.
Fig. 3 is a circuit block diagram of a programmable josephson junction array driving apparatus according to an embodiment of the present invention.
Fig. 4 is a circuit block diagram of a driving branch circuit of an embodiment of the present invention.
Description of reference numerals: 101. a first driving module; 102. a second driving module; 111. a first programmable josephson junction array module; 112. a second programmable josephson junction array module; 120. a controller; 121. a waveform memory; 130. a reference clock; 141. a digital-to-analog converter; 142. a V/I converter; 150. a microwave generation module; 151. a microwave signal generator; 152. a microwave power amplifier.
Detailed Description
In order to enable a reader to better understand the design purpose of the method, the following specific embodiments are provided in particular, so that the reader can visually understand the structure, structural composition, action principle and technical effect related to the method. It should be noted that the following embodiments are not intended to limit the technical solutions of the present methods, and those skilled in the art can analyze and understand the embodiments and make a series of modifications and equivalent substitutions on the technical solutions provided by the present methods in combination with the prior knowledge, and the new technical solutions obtained by the modifications and equivalent substitutions are also encompassed by the present methods.
As shown in fig. 1, a two-way programmable josephson junction array driving method for driving a two-way programmable josephson junction array including a first programmable josephson junction array and a second programmable josephson junction array, the driving method comprising:
step S101, setting a sampling frequency f s Quantizing the waveform of the target output voltage u (t) of the programmable Josephson junction array into a sequence of voltage values S 0 、S 1 ……S n-1 ；
Step S102, calculating a voltage value sequence S 0 、S 1 ……S n-1 Voltage bias combination of each sub-junction array in the Josephson junction array corresponding to each voltage value;
step S103, calculating driving voltage combinations of all driving channels of the programmable Josephson junction array driver according to the voltage bias combinations of all the sub-junction arrays;
step S104, quantizing the driving voltage combination of each driving channel into a binary coding combination;
step S105, inputting the binary code combination into the digital-to-analog converter 141 in each driving channel in sequence;
step S106, synchronously triggering the digital-to-analog converters 141 in each driving channel to output driving voltages corresponding to the binary codes through the reference clock 130;
step S107, converting the driving voltage output by the digital-to-analog converter 141 into a driving current to drive the programmable josephson junction array module to output a target voltage.
As one implementation, the voltage value sequence S in step S101 0 、S 1 ......S n-1 The quantification method is shown as follows:
wherein u (i/f) S ) Represents the voltage value at the ith sampling point, ROUND is an integer function, u LSB For sub-junctions corresponding to the least significant bit in a programmable Josephson junction arrayThe voltage values that the array can synthesize.
As an implementation, u LSB The expression of (a) is:
wherein N is the number of the Josephson junctions in the corresponding sub-junction array with the least significant bit, N is the quantization step number, f is the microwave frequency, K J The Josephson constant is 483597.9GHz/V.
As one implementation, the voltage value sequence S in step S102 0 、S 1 ……S n-1 The voltage bias combination of each sub-junction array in the Josephson junction array corresponding to each voltage value is represented as T1:
wherein B is i，j Representing a sequence S of voltage values 0 、S 1 ……S n-1 Voltage value S of the ith sampling point i Required bias state of the j-th Josephson sub-junction array, B i，j Is one of 1, 0 and-1, which respectively represents positive bias, zero bias and negative bias.
As one implementation manner, the combination of the driving voltages of the driving channels of the programmable josephson junction array driver in step S103 is represented as T2:
wherein V i，j Representing a sequence S of voltage values 0 、S 1 ……S n-1 Voltage value S of the ith sampling point i Of the jth Josephson sub-junction array, V i，j The calculation method of (a) is shown as follows:
wherein I b(i) I is more than or equal to 1 and less than or equal to n-1; the R sub-junction array corresponds to the resistance value of the driving channel; n is i For the sub-junction matrix biased state, N i The number of the Josephson junctions contained in the i-th segment of the sub-junction array is shown.
As an implementation manner, the binary coding manner in step S104 is offset binary coding or two' S complement coding, and this step digitizes the elements in table T2 into DAC codes, so as to obtain DAC codes as shown in table T3 below, and stores the DAC codes in the waveform memory 121.
As an implementation manner, as shown in fig. 2, the method further includes: step S108, setting phase difference of output voltage of the two-way programmable Josephson junction array, and inputting the binary code combination into the digital-to-analog converters 141 in the driving channels of the first programmable Josephson junction array and the second programmable Josephson junction array respectively according to the phase difference. The specific steps are as follows, phase difference of two-way output is set, and the calculation method of the phase control word delta P is as follows:
wherein,
for phase differences between the two-way programmable Josephson junction array output voltages, or>
m is the number of sampling points.
Step S109, reading the ith column data in the T3 table from the waveform memory 121, and sending the ith column data to the corresponding labeled dac 141 in the first group according to the row number j; the i + Δ P column data in the T3 table is read from the waveform memory 121 and sent to the corresponding labeled dac 141 in the second group according to the row number j.
Step S110, after the first trigger edge of the pulse of the reference clock 130 reaches the output refresh control terminals of all the digital-to-analog converters 141 of the first group and the second group, all the DACs synchronously output the driving voltage, and after passing through the V/I converter 142, the josephson junction is driven to bias to the state represented by T1, and at the same time, the corresponding quantum voltage is output.
Step S111, when waiting for the second trigger edge of the pulse of the reference clock 130 to reach the controller, calculating and refreshing i and skipping to step S109, and repeating the steps S109 to S111, wherein the value of i is as follows:
to illustrate the dual-channel synchronous programmable Josephson junction array driving method proposed by the present invention, the following example synthesizes the phase difference of
The specific process of the two paths of quantum voltage signals, wherein the frequency of the quantum voltage waveform to be synthesized is 1Hz, and the amplitude is 10V; the examples are only for the convenience of understanding the method of the present invention, but are not intended to limit the scope of the method of the present invention, the application field, and other various fields.
Firstly, a controller carries out digital processing on a waveform to be synthesized; setting the sampling rate f s =8Hz, the monocycle waveform u (t) to be output is quantized into a voltage value sequence, and the quantization formula is as follows:
in the formula u (i/f) s ) Represents the voltage value at the ith sampling point, ROUND is an integer function, u LSB The voltage value which can be synthesized by the sub-junction array corresponding to the minimum effective bit in the programmable Josephson junction array，u LSB The expression of (a) is:
wherein N is the number of Josephson junctions corresponding to the least significant bit in the sub-junction array, N is the quantization step number, f is the microwave frequency, K J The Josephson constant is 483597.9GHz/V. The final step voltage value sequence is 0.000000, 4.999818, 9.999862, 4.999818, 0.000000, -4.999818, -9.999862, -4.999818.
Calculating corresponding Josephson sub-junction array bias combinations in the voltage sequence, and constructing a bias combination sequence table as shown in the following:
calculating the summary number n of the needed Josephson junctions;
grouping Josephson sub-junction arrays contained in a chip according to the number of junctions, wherein the joint number comprises an ascending ternary T group, a ternary redundant R group, a quantization error compensation S group and a residual effective sub-junction array O group;
the total number n is decomposed into n Tj And n Oj The sum of the two terms, wherein the decomposition modes are p, n Tj Is a non-negative integer less than the sum of the numbers of the T sets of sub-junction arrays, n Oj Is a non-negative integer represented by a biased combination of O groups of the subjunction arrays;
splitting n in p separately Tj Converting into p bias combination forms represented by T group and R group subcode arrays;
respectively compensating quantization errors generated by the p bias combination forms through the quantization error compensation values of the S group to obtain a bias combination mode with the minimum residual error after compensation;
and arranging the obtained bias combination modes according to the sequence of the atomic junction array.
As an implementation manner, the josephson sub-junction array bias combination calculation can also be realized by the following method:
and judging whether a magnetic flux capturing phenomenon occurs or not, if not, calculating a bias state matrix corresponding to the quantum voltage sequence by adopting a balanced ternary algorithm, otherwise, closing the abnormal junction section during calculation, and calculating the bias state matrix by adopting an index algorithm.
Calculating the driving voltage value of each channel corresponding to each step voltage in each bias combination according to the Josephson sub-junction array bias combination corresponding to each step voltage, wherein the calculation formula of the driving voltage value is as follows:
in which I b(i) The bias current on the ith segment of the sub-junction array is more than or equal to 1 and less than or equal to n-1; r =110 Ω is a precision resistor in the voltage output channel; n is i (subcontact array bias state) = -1, 0, or 1,n i The number of the Josephson junctions contained in the i segment sub-junction array; the finally obtained programmable josephson sub-junction array driving voltage combination sequence table is as follows:
the elements in the table above are digitized into a DAC code table as shown below and the DAC codes are stored in the waveform memory 1211.
And calculating a phase control word delta P =125 according to the set phase difference of the two paths of output, and taking an initial value i =0.
The 1 st column data in the table above is read from the waveform memory 121 and sent to the corresponding labeled DAC 141 in the first group according to the row number j (A) 1 、A 2 …A n ) (ii) a The 1+ Δ P =126 column data in the table above is read from the waveform memory 121 and sent to the corresponding labeled dac 141 in the second group according to the row number j (C) 1 、C 2 …C n )。
After the first trigger edge of the reference clock 130 pulse reaches the output refresh control terminals of all the digital-to-analog converters 141 of the first group and the second group, all the DACs synchronously output the driving voltage, and after passing through the V/I converter 142, the josephson junctions are driven to bias to the state shown in the bias combination sequence table, and simultaneously, corresponding quantum voltage signals are output.
When a second trigger edge of the reference clock 130 pulse reaches the controller, calculating and refreshing i, outputting two paths of quantum voltage signals in a reciprocating cycle manner, wherein the phase difference of the two paths of output signals is
As shown in fig. 3, a two-way programmable josephson junction array driving apparatus includes:
the programmable Josephson junction array module is used for outputting quantum voltage and comprises a first programmable Josephson junction array module and a second programmable Josephson junction array module; the programmable josephson junction array module in this example uses two 10V josephson chips.
The driving module is used for driving the programmable Josephson junction array module and comprises a first driving module 101 and a second driving module 102, the first driving module 101 is used for driving the first programmable Josephson junction array module, the second driving module 102 is used for driving the second programmable Josephson junction array module, and the first driving module 101 and the second driving module 102 both comprise a control end;
the waveform memory 121 is configured to store binary codes corresponding to voltage values of each point in a voltage waveform to be output by the driving module; the waveform memory 121 is preferably AM29F032B.
The controller 120 generates driving voltage waveforms of the driving modules according to target output voltage waveforms of the programmable Josephson junction array, stores binary codes corresponding to voltage values of all points in the driving voltage waveforms in the waveform memory 121, sequentially reads all groups of binary codes in the waveform memory 121 and inputs the binary codes into the corresponding driving modules; the controller 120 is preferably ZYNQ7010.
The reference clock 130 is configured to output a clock pulse, where the clock pulse is used to trigger the first driving module 101 and the second driving module 102 to synchronously read the binary code sent by the control end; the reference clock 130 is preferably a rubidium atomic clock.
The waveform memory 121 is in communication connection with the controller 120, an output end of the controller 120 is connected to an input end of the driving module, an output end of the driving module is connected to the programmable josephson junction array, and an output end of the reference clock 130 is simultaneously connected to control ends of the first driving module 101 and the second driving module 102.
As an implementation manner, the apparatus further includes a microwave generation module 150, the microwave generation module 150 includes a microwave signal generator 151 and a microwave power amplifier 152, an output end of the microwave signal generator 151 is connected to an input end of the microwave power amplifier 152, and an output end of the microwave power amplifier 152 is simultaneously connected to input ends of the first programmable josephson junction array module 111 and the second programmable josephson junction array module 112.
As an implementation manner, as shown in fig. 4, each of the first driving module 101 and the second driving module 102 includes a plurality of driving branches, each of the driving branches includes a digital-to-analog converter 141 and a V/I converter 142 connected in series, the digital-to-analog converter 141 is connected to an output end of the controller 120, and an output end of the V/I converter 142 is correspondingly connected to an input end of the programmable josephson junction array module.
The V/I converter 142 includes a plurality of voltage followers 1421 and a voltage dividing resistor R 1 、R 2 ...R n (ii) a The output end of the voltage follower 1421 is connected to the divider resistors R 1 、R 2 ...R n One end of (1), a voltage dividing resistor R 1 、R 2 ...R n The other ends of the two electrodes are respectively connected with a plurality of input ends of a 10V Josephson chip.
In summary, in the two-way synchronous programmable josephson junction array driving method of the present invention, the reference clock 130 is used as a synchronous trigger signal, so that all the digital-to-analog converters 141 synchronously output driving voltages, thereby realizing high synchronism of the two-way josephson junction array driving currents; meanwhile, the two-way synchronous programmable josephson junction array driving device of the invention samples the waveform to be output, digitizes the sampled data into binary codes and stores the binary codes in the waveform memory 121, and sequentially sends the corresponding binary codes to the corresponding digital-to-analog converters 141 in the first programmable josephson junction array module 111 and the second programmable josephson junction array module 112 according to the set phase difference, thereby realizing the control of the phase difference between two-way outputs.
It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims. The drawings corresponding to the specific embodiments exist in a form assisting understanding, and a reader can conveniently understand the abstract upper concept of the technical idea related to the method by understanding the specific visualized lower concept. When the whole understanding of the method and the comparison with other technical schemes except the technical scheme provided by the method are carried out, the expression of the attached drawings is not taken as the sole reference, and a series of modifications, equivalent substitutions, mixture of characteristic elements, deletion and recombination of unnecessary technical characteristic elements, reasonable addition and recombination of the unnecessary technical characteristic elements which are common in the prior art and the like which are made according to the attached drawings or without the attached drawings after the concept of the method is understood to be included in the spirit of the method.
Claims (10)
1. A dual path programmable josephson junction array driving method for driving a dual path programmable josephson junction array comprising a first programmable josephson junction array and a second programmable josephson junction array, the driving method comprising:
setting the sampling frequency f s Quantizing the target output voltage waveform of the programmable Josephson junction array into a sequence of voltage values S 0 、S 1 ……Sn- 1 ；
Calculating the sequence of voltage values S 0 、S 1 ……Sn- 1 Voltage bias combination of each sub-junction array in the Josephson junction array corresponding to each voltage value;
calculating the driving voltage combination of each driving channel of the programmable Josephson junction array driver according to the voltage bias combination of each sub-junction array;
quantizing the driving voltage combination of each driving channel into a binary coding combination;
sequentially inputting the binary coding combination into the digital-to-analog converters in each driving channel;
synchronously triggering the digital-to-analog converters in each driving channel by a reference clock to output driving voltages corresponding to the binary codes;
converting the driving voltage output by the digital-to-analog converter into a driving current to drive the programmable Josephson junction array to output a target voltage.
2. The method of dual path programmable josephson junction array drive according to claim 1, wherein the sequence of voltage values S 0 、S 1 ……Sn- 1 The quantization method comprises the following steps:
wherein u (i/f) s ) Represents the voltage value at the ith sampling point, ROUND is an integer function, u LSB The voltage value which can be synthesized by the sub-junction array corresponding to the minimum effective bit in the programmable Josephson junction array.
3. A method of two-way programmable josephson junction array driving according to claim 2, wherein u is LSB The expression of (c) is:
wherein N is the number of the Josephson junctions in the corresponding sub-junction array with the least significant bit, N is the quantization step number, f is the microwave frequency, K J Is the Josephson constant 483597.9GHz/V.
4. A method of two-way programmable Josephson junction array driving according to claim 1, wherein the sequence of voltage values S 0 、S 1 ……Sn- 1 The voltage bias combination of each sub-junction array in the Josephson junction array corresponding to each voltage value is expressed as:
wherein B is i,j The sequence S of representative voltage values 0 、S 1 ……Sn- 1 Voltage value S of the ith sampling point i Desired bias state of j-th Josephson sub-junction array, B i,j Is one of 1, 0 and-1, representing positive, zero and negative bias, respectively.
5. The method of claim 1, wherein the driving voltages for the driving channels of the programmable josephson junction array driver are expressed in combination as:
wherein V i,j Representing a sequence S of voltage values 0 、S 1 ……Sn- 1 Voltage value S of the ith sampling point i The j-th Josephson sub-junction array of, the V i,j The calculation method is
In which I b(i) Is the bias current on the ith segment of the sub-junction array, i is more than or equal to 1 and less than or equal to n-1; r, the resistance value of the corresponding driving channel of the sub-junction array; n is i For the sub-junction matrix biased state, N i The number of the Josephson junctions in the i-th segment of the sub-junction array, f is the microwave frequency, K j-90 Is the josephson constant.
6. The method of claim 1, wherein the binary code is offset binary code or two's complement code.
7. The method of claim 1 further comprising setting phase differences of output voltages of the two-way programmable josephson junction arrays, combining the binary codes with the phase differences and inputting the combined binary codes to digital-to-analog converters in respective drive channels of the first and second programmable josephson junction arrays.
8. A two-way programmable josephson junction array drive apparatus comprising:
the programmable Josephson junction array module is used for outputting quantum voltage and comprises a first programmable Josephson junction array module and a second programmable Josephson junction array module;
the driving module is used for driving the programmable Josephson junction array module and comprises a first driving module and a second driving module, the first driving module is used for driving the first programmable Josephson junction array module, the second driving module is used for driving the second programmable Josephson junction array module, and the first driving module and the second driving module both comprise a control end;
the waveform memory is used for storing binary codes corresponding to voltage values of all points in the voltage waveform to be output by the driving module;
the controller generates driving voltage waveforms of driving modules according to target output voltage waveforms of the programmable Josephson junction array, stores binary codes corresponding to voltage values of all points in the driving voltage waveforms in the waveform memory, sequentially reads all groups of binary codes in the waveform memory and inputs the binary codes into the corresponding driving modules;
the reference clock is used for outputting clock pulses, and the clock pulses are used for triggering the first driving module and the second driving module to synchronously read the binary codes sent by the control end;
the waveform memory is in communication connection with the controller, the output end of the controller is connected with the input end of the driving module, the output end of the driving module is connected with the programmable Josephson junction array module, and the output end of the reference clock is simultaneously connected with the control ends of the first driving module and the second driving module.
9. The dual path programmable josephson junction array driving device of claim 8, further comprising a microwave generating module, the microwave generating module comprising a microwave signal generator and a microwave power amplifier, an output of the microwave signal generator being connected to an input of the microwave power amplifier, an output of the microwave power amplifier being connected to inputs of the first and second programmable josephson junction array modules simultaneously.
10. The device of claim 8, wherein the first and second driving modules each comprise a plurality of driving branches, the driving branches comprise a digital-to-analog converter and a V/I converter connected in series, the digital-to-analog converter is connected to the output of the controller, and the output of the V/I converter is correspondingly connected to the input of the programmable josephson junction array module.
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| US10367483B1 (en) * | 2018-12-20 | 2019-07-30 | Northrop Grumman Systems Corporation | Josephson current source system |
| CN110673523A (en) * | 2019-09-24 | 2020-01-10 | 中国计量科学研究院 | Josephson junction array driving method combining balanced ternary and index algorithm |
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| CN203313163U (en) * | 2013-05-28 | 2013-11-27 | 中国计量科学研究院 | Dynamic signal synthesis device based on programmable Josephson junction array |
| CN110095639B (en) * | 2019-04-04 | 2021-06-01 | 中国计量科学研究院 | Device and method for generating alternating current quantum voltage |
| US11557708B2 (en) * | 2019-05-21 | 2023-01-17 | Government Of The United States Of America, As Represented By The Secretary Of Commerce | Josephson voltage standard |
| CN112668270B (en) * | 2020-12-30 | 2021-11-23 | 中国计量科学研究院 | Josephson junction array quantum step determination method, apparatus, device and storage medium |
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| CN110673523A (en) * | 2019-09-24 | 2020-01-10 | 中国计量科学研究院 | Josephson junction array driving method combining balanced ternary and index algorithm |
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