CN114141920B - Light emitting diode and preparation method thereof - Google Patents
Light emitting diode and preparation method thereof Download PDFInfo
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- CN114141920B CN114141920B CN202111376242.7A CN202111376242A CN114141920B CN 114141920 B CN114141920 B CN 114141920B CN 202111376242 A CN202111376242 A CN 202111376242A CN 114141920 B CN114141920 B CN 114141920B
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- 238000002360 preparation method Methods 0.000 title abstract description 4
- 238000005192 partition Methods 0.000 claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 238000005520 cutting process Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims description 73
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 239000007788 liquid Substances 0.000 abstract description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 4
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- 239000010980 sapphire Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910015269 MoCu Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
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- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- BEQNOZDXPONEMR-UHFFFAOYSA-N cadmium;oxotin Chemical compound [Cd].[Sn]=O BEQNOZDXPONEMR-UHFFFAOYSA-N 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- SKRWFPLZQAAQSU-UHFFFAOYSA-N stibanylidynetin;hydrate Chemical compound O.[Sn].[Sb] SKRWFPLZQAAQSU-UHFFFAOYSA-N 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
Abstract
The application discloses a light-emitting diode and a preparation method thereof, wherein the light-emitting diode comprises a substrate, a structural layer and a light-emitting table top, wherein the upper surface of the substrate is provided with a light-emitting area and a cutting area surrounding the light-emitting area; the structural layer is paved on the light-emitting area and the cutting area; a light-emitting table top is arranged on the structural layer at the light-emitting area, and the light-emitting table top comprises a first epitaxial layer; the cutting area comprises a first partition area and a second partition area which are arranged at intervals in the circumferential direction of the light-emitting table surface, a boss is formed on the first partition area, and the boss is connected to the structural layer and is obtained by extending upwards a first insulating layer, a second insulating layer and a metal layer in the structural layer; the second partition is formed with a second epitaxial layer extending from the second partition onto the boss. According to the application, the second epitaxial layer is arranged on the second partition and the adjacent boss, so that gaps are prevented from occurring at the joint of the boss and the second partition, and etching liquid is prevented from penetrating into the structural layer and damaging the structural layer in the subsequent process.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a light emitting diode and a method for manufacturing the same.
Background
Light emitting diodes are widely used in many fields due to their high luminous efficiency. The light-emitting diode comprises a light-emitting table top and a cutting area surrounding the light-emitting table top, and because of the difference of thermal expansion coefficients between the light-emitting table top and the structural layer and between the light-emitting table top and the substrate, the light-emitting diode is easy to generate stress with different sizes, and even is easy to generate stress lines or the phenomenon that the light-emitting table top is damaged or falls off. In order to solve the above problems, a boss surrounding the light emitting mesa is formed in the cut region.
After the boss surrounding the light-emitting table surface is introduced, the potential distribution of the whole light-emitting diode is uneven, the phenomenon of electromigration of the light-emitting diode is easy to occur, and the reliability of the light-emitting diode is affected. Therefore, in order to improve the phenomenon that the light emitting diode is easy to generate electromigration, the cutting area is divided into a first partition area and a second partition area, and a boss is formed on the first partition area only, so that the phenomenon that the light emitting diode generates electromigration is avoided.
However, the cutting area is divided into the first partition area and the second partition area, and after the first partition area forms the boss, the height of the first partition area is inconsistent with the height of the second partition area, the distance between adjacent boss areas is smaller, and in the subsequent process, the joint of the boss areas and the second partition area is easy to generate breakage phenomena such as gaps, and further the etching solution permeates into the structural layer and damages the structural layer, so that the reliability of the light-emitting diode is affected.
Disclosure of Invention
The application aims to provide a light-emitting diode, which can prevent gaps from appearing at the joint of a boss and a second partition by arranging a second epitaxial layer on the second partition and the boss adjacent to the second partition, further prevent etching liquid from penetrating into a structural layer and damaging the structural layer in the subsequent process, and improve the reliability of the light-emitting diode.
Another object is to provide a method for manufacturing the light emitting diode.
In a first aspect, embodiments of the present application provide a light emitting diode, including:
a substrate, the upper surface of which is provided with a light-emitting area and a cutting area surrounding the light-emitting area;
the structure layer is paved on the light-emitting area and the cutting area; the structural layer at least comprises a first insulating layer, a second insulating layer and a metal layer from top to bottom; a light-emitting table top is arranged on the structural layer at the light-emitting area, and the light-emitting table top comprises a first epitaxial layer;
the cutting region comprises a first partition and a second partition which are arranged at intervals in the circumferential direction of the light-emitting table top; the first partition is provided with a boss which is connected to the structural layer and is formed by upwards extending a first insulating layer, a second insulating layer and a metal layer, the height of the boss is lower than that of the light-emitting table top, and the boss and the light-emitting table top are arranged at intervals; the second partition is formed with a second epitaxial layer extending from the second partition onto the boss.
In one possible embodiment, the second epitaxial layer coats at least the end of the boss adjacent the second partition.
In one possible embodiment, the second epitaxial layer is spaced apart from the light emitting mesa.
In a possible embodiment, the second epitaxial layer covers at least a side of the mesa adjacent to the light emitting mesa.
In one possible embodiment, the portion of the second epitaxial layer located on the boss is configured as a U-shape with the U-shaped opening facing the opposite side of the second partition.
In one possible embodiment, the width of the second epitaxial layer at the mesa is equal to the width of the second epitaxial layer at the second region.
In one possible embodiment, the second epitaxial layer covers the entire area or a partial area of the second sub-area in the circumferential direction of the light-emitting mesa.
In one possible embodiment, when the second epitaxial layer covers a partial region of the second partition in the circumferential direction of the light emitting mesa, the outer wall of the portion of the second epitaxial layer located in the second partition is curved or sloped, and the slope of the outer wall decreases from bottom to top.
In one possible embodiment, the upper surface of the second epitaxial layer is level with the upper surface of the light emitting mesa.
In one possible embodiment, the layer structure of the second epitaxial layer is the same as the layer structure of the first epitaxial layer.
In one possible embodiment, the sum L of the lengths of the first partitions in the circumferential direction of the light-emitting mesa 1 Sum of lengths L of the second partitions in the circumferential direction of the light emitting mesa 2 The ratio of (2) is between 5 and 20.
In one possible implementation, a reflective layer and a conductive layer are included between the first insulating layer and the second insulating layer, the reflective layer is connected with the first epitaxial layer through the first insulating layer, the conductive layer wraps the periphery of the reflective layer, and a contact electrode is electrically connected to the surface facing the first epitaxial layer; the second insulating layer is coated on the periphery of the conductive layer; the metal layer is provided with a conductive column electrically connected with the first epitaxial layer, and the side wall of the conductive column is coated with a second insulating layer and a first insulating layer.
In one possible embodiment, the first epitaxial layer includes a first semiconductor layer, an active layer, and a second semiconductor layer from top to bottom, the conductive pillars are electrically connected to the first semiconductor layer, and the contact electrodes are electrically connected to the second semiconductor layer.
In a second aspect, an embodiment of the present application provides a method for manufacturing a light emitting diode, including:
forming a semiconductor stack layer on a substrate;
etching the semiconductor stacked layer, and forming a first groove for arranging a boss and a second groove for arranging a conductive column; the first grooves are of annular structures which are distributed intermittently, and the depth of the first grooves is smaller than the height of the semiconductor stacked layers;
forming a structural layer on the semiconductor stacked layer, wherein the structural layer at least comprises a first insulating layer, a second insulating layer and a metal layer from bottom to top, and the first insulating layer, the second insulating layer and the metal layer extend to the first groove and form a boss; bonding the structural layer to the substrate;
removing the substrate; etching the semiconductor stacked layer and forming a light emitting mesa comprising a first epitaxial layer; the cutting area comprises a first partition area and a second partition area which are arranged at intervals in the circumferential direction of the light-emitting table top, and the first partition area comprises a boss;
and continuing to etch the semiconductor stacked layer at the cutting region, so that the second epitaxial layer remains in the second region, and the second epitaxial layer extends from the second region to the boss.
In one possible embodiment, the second epitaxial layer coats at least the end of the boss adjacent to the second partition; the second epitaxial layer is arranged at intervals with the light-emitting table surface.
Compared with the prior art, the application has at least the following beneficial effects:
according to the application, the second epitaxial layer is arranged on the second partition and the adjacent boss, the second epitaxial layer can protect the second partition and the end part of the boss, which is close to the second partition, so that the damage phenomenon such as a gap and the like at the joint of the boss and the second partition is effectively avoided, the phenomenon that etching liquid is easy to permeate into the structural layer and damage the structural layer due to the damage phenomenon in the subsequent process is avoided, and the reliability of the light-emitting diode is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a top view of a light emitting diode according to an embodiment of the present application;
FIG. 2 is a top view of a light emitting diode according to an embodiment of the present application;
FIG. 3 is a top view of a light emitting diode according to an embodiment of the present application;
FIG. 4 is a top view of a light emitting diode according to an embodiment of the present application;
FIG. 5 is a schematic A-A cross-sectional view of a light emitting diode according to an embodiment of the present application;
FIG. 6 is a schematic A-A cross-sectional view of a light emitting diode according to an embodiment of the present application;
FIG. 7 is a schematic view of a B-B cross-section of a light emitting diode according to an embodiment of the present application;
FIG. 8 is a schematic view of a B-B cross-section of a light emitting diode according to an embodiment of the present application
Fig. 9 to 19 are schematic structural views of a light emitting diode according to an embodiment of the present application at different stages of fabrication.
Illustration of:
a 100 substrate; 200 luminous table top; 210 a first epitaxial layer; 211 a first semiconductor layer; 212 an active layer; 213 a second semiconductor layer; 214 a first trench; 215 a second trench; 220 a second epitaxial layer; 221 first portion; 222 a second portion; 300 a first insulating layer; 301 a first opening; 302 a second opening; 310 a reflective layer; 320 conductive layers; 330 a second insulating layer; 340 a metal layer; 341 conductive posts; 350 a transparent conductive layer; a 400 substrate; 500 cutting areas; 510 a first partition; 511 bosses; 520 second partition; 600 contact electrodes; 700 a third insulating layer.
Detailed Description
The following specific examples are presented to illustrate the present application, and those skilled in the art will readily appreciate the additional advantages and capabilities of the present application as disclosed herein. The application may be practiced or carried out in other embodiments that depart from the spirit and scope of the present application, and details of the present application may be modified or changed from various points of view and applications.
In the description of the present application, it should be noted that the azimuth or positional relationship indicated by the terms "upper" and "lower" and the like are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship conventionally put in use of the product of the application, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application. Furthermore, the terms "first" and "second," etc. are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
According to one aspect of the present application, a light emitting diode is provided. Fig. 1 to 4 are plan views of light emitting diodes, fig. 5 and 6 are schematic views of A-A cross-section of the light emitting diodes, and fig. 7 and 8 are schematic views of B-B cross-section of the light emitting diodes. The curve a in fig. 1 to 4 is the cut line of the light emitting diode. The I region in fig. 5 to 8 is indicated as a light emitting diode cut along the dicing line a.
The light emitting diode includes a substrate 400, a structural layer, and a light emitting mesa 200. The upper surface of the substrate 400 is provided with a light emitting region and a cutting region 500 surrounding the light emitting region. The structural layer is laid on the light emitting region and the cutting region 500, and the structural layer includes at least a first insulating layer 300, a second insulating layer 330 and a metal layer 340 from top to bottom; a light emitting mesa 200 is disposed on the structural layer at the light emitting region, the light emitting mesa 200 including a first epitaxial layer 210. The cutting region 500 includes a first partition 510 and a second partition 520, the first partition 510 and the second partition 520 being spaced apart in the circumferential direction of the light emitting mesa 200; the first partition 510 is formed with a boss 511, the boss 511 is connected to the structural layer and is formed by extending the first insulating layer 300, the second insulating layer 330 and the metal layer 340 upward, the height of the boss 511 is lower than that of the light emitting mesa 200, and the boss 511 is spaced apart from the light emitting mesa 200. The second partition 520 is formed with the second epitaxial layer 220, and the second epitaxial layer 220 extends from the second partition 520 onto the boss 511. The circumferential direction of the light emitting mesa is the circumferential direction of the side wall of the light emitting mesa.
The second epitaxial layer 220 has the same layer structure as the first epitaxial layer 210, and is formed by etching a semiconductor stack layer. The semiconductor stacked layers each include a first semiconductor layer 211, an active layer 212 and a second semiconductor layer 213 from top to bottom, wherein the first semiconductor layer 211 is an N-type semiconductor layer, the second semiconductor layer 213 is a P-type semiconductor layer, and the active layer 212 is a multi-layer quantum well layer. The N-type semiconductor layer, the multi-layer quantum well layer and the P-type semiconductor layer are only basic constituent units of the semiconductor stacked layer, and the semiconductor stacked layer can also comprise other functional structure layers with an optimization effect on the performance of the light emitting diode.
The substrate 400 is a permanent substrate for transferring the light emitting mesa 200 grown on the substrate 100. The material of the substrate 400 is selected from GaAs, ge, si, cu, mo, WCu or MoCu.
By arranging the second epitaxial layer 220 on the second partition 520 and the adjacent boss 511, the second epitaxial layer 220 can at least cover the second partition 520 and the end of the boss 511 in the circumferential direction of the light-emitting table 200, so as to protect the second partition 520 and the end of the boss 511 close to the second partition 520, effectively avoid the damage phenomenon such as gaps at the joint of the boss 511 and the second partition 520, further avoid the phenomenon that etching liquid is easy to penetrate into the structural layer and damage the structural layer due to the damage phenomenon in the subsequent process, and improve the reliability of the light-emitting diode.
In one embodiment, referring to fig. 1 to 4, the second epitaxial layer 220 covers at least an end of the boss 511 near the second partition 520, and the second epitaxial layer 220 is spaced apart from the light emitting mesa 200. The second epitaxial layer 220 covers at least one side of the mesa 511 adjacent to the light emitting mesa 200.
In one embodiment, the second epitaxial layer 220 includes a first portion 221 and a second portion 222 connected, the first portion 221 being located on the boss 511, the second portion 222 being located in the second section 520.
Preferably, referring to fig. 1 and 5, the portion of the second epitaxial layer 220 located on the boss 511 covers the upper surface, the side wall, of the boss 511, and the second epitaxial layer 220 covers the entire area of the second partition 520 in the circumferential direction of the light emitting mesa, and the width of the second epitaxial layer 220 at the boss 511 is equal to the width of the second epitaxial layer 220 at the second partition 520. In other words, the first portion 221 covers the upper surface and the sidewall of the boss 511, and the second portion 222 covers the entire area of the second partition 520 in the circumferential direction of the light emitting mesa. The width of the first portion 221 is preferably equal to the width of the second portion 222, and the width of both the first portion 221 and the second portion 222 is greater than the width of the boss 511.
Preferably, referring to fig. 2 and 6, the portion of the second epitaxial layer 220 located on the boss 511 is configured as a U-shape with the U-shaped opening facing the opposite side of the second partition 520; the second epitaxial layer 220 covers the entire area of the second partition 520 in the circumferential direction of the light emitting mesa. In other words, the first portion 221 is configured in a U shape with the U-shaped opening toward the opposite side of the second partition 520, the first portion 221 extending inward from the outer wall surface of the boss 511 by a preset width; the second portion 222 covers the entire area of the second partition 520 in the circumferential direction of the light emitting mesa.
As an alternative embodiment, referring to fig. 3, the second epitaxial layer 220 covers a partial region of the second partition 520 in the circumferential direction of the light emitting mesa. In other words, in the circumferential direction of the light emitting mesa, the second portion 222 covers a partial region of the second partition 520, and the length of the second portion 222 in the circumferential direction of the light emitting mesa 200 is preferably less than 1/2 of the length of the second partition 520 in the circumferential direction of the light emitting mesa 200.
Preferably, the outer wall surface of the portion of the second epitaxial layer 220 located in the second partition 520 is configured to be arc-shaped or slope, that is, the outer wall surface of the second portion 222 is arc-shaped or slope, and the slope of the outer wall surface decreases from bottom to top. The portion of the second epitaxial layer 220 located in the second partition 520 is configured as the above structure, so that the second epitaxial layer 220 can be smoothly transited to the second partition 520 without the second epitaxial layer 220, a gap is avoided at the junction of the second epitaxial layer 220 and the second partition 520 without the second epitaxial layer 220, and further, the etching solution is prevented from penetrating into the structural layer and damaging the structural layer in the subsequent process, thereby improving the reliability of the light emitting diode.
In one embodiment, referring to fig. 4, the second epitaxial layer 220 is in a "T" shape, which covers a side of the boss 511 adjacent to the light emitting mesa 200 and a portion of the second partition 520 adjacent to the light emitting mesa 200. The side of the boss 511 remote from the light emitting mesa 200 and the portion of the second partition 520 remote from the light emitting mesa 200 are not covered with the second epitaxial layer 220.
Preferably, in the second epitaxial layer 220, the width of the second portion 222 is greater than the width of the first portion 221.
Preferably, the first portion 221 covers only an end of the boss 511 near the second partition 520, and one side outer wall surface of the boss 511 near the light emitting mesa 200.
In one embodiment, referring to fig. 5 and 6, the height of boss 511 is 40% to 80% of the height of light emitting mesa 200; the upper surface of the second epitaxial layer 220 is at the same height as the upper surface of the light emitting mesa 200.
As an alternative embodiment, the height of the boss 511 is 40% -80% of the height of the light emitting mesa 200; the height of the upper surface of the second epitaxial layer 220 is 70% to 95% of the height of the upper surface of the light emitting mesa 200.
In one embodiment, the sum L of the lengths of the first partitions 510 in the circumferential direction of the light emitting mesa 200 1 Sum of lengths L of the second partitions 520 in the circumferential direction of the light emitting mesa 200 2 The ratio of (2) is between 5 and 20.
In one embodiment, referring to fig. 5 to 8, a reflective layer 310 and a conductive layer 320 are included between the first insulating layer 300 and the second insulating layer 330. The reflective layer 310 is connected to the first epitaxial layer 210 through the first insulating layer 300. The conductive layer 320 is coated on the periphery of the reflective layer 310, and the surface facing the first epitaxial layer 210 is electrically connected to the contact electrode 600. The second insulating layer 330 is coated on the periphery of the conductive layer 320. The metal layer 340 has a conductive pillar 341 electrically connected to the first epitaxial layer 210, and a sidewall of the conductive pillar 341 is covered with the second insulating layer 330 and the first insulating layer 300.
Preferably, a transparent conductive layer 350 is included between the first insulating layer 300 and the first epitaxial layer 210, and the reflective layer 310 passes through the first insulating layer 300 to contact with the transparent conductive layer 350.
Specifically, the first insulating layer 300 under the first epitaxial layer 210 is provided with a plurality of first openings 301, and the first openings 301 penetrate the first insulating layer 300 in a vertical direction. The reflective layer 310 is located under the first insulating layer 300 and fills the first opening 301 in the first insulating layer 300. The material of the first insulating layer 300 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or aluminum oxide. The material of the reflective layer 310 includes, but is not limited to, silver.
The conductive layer 320 is located under the reflective layer 310 and wraps around the reflective layer 310. The first insulating layer 300 has a second opening 302, and the second opening 302 and the first opening 301 are located on the same side of the conductive pillar 341 and vertically penetrate through the first insulating layer 300. A contact electrode 600 is formed at the second opening 302, and the contact electrode 600 is in ohmic contact with the second semiconductor layer 213 through the second opening 302, the conductive layer 320, the reflective layer 310, the first opening 301, to electrically connect the contact electrode 600 with the second semiconductor layer 213, which is substantially the second electrode. The material of the conductive layer 320 is Ag, au, ti, al, cr, pt, tiW alloy, ni or any combination thereof, and the material of the conductive layer 320 is preferably Ti, au, cr, pt, tiW alloy with relatively stable performance. The material of the contact electrode 600 includes one or at least two of Al, ni, ti, pt or Au.
The second insulating layer 330 is located on a side of the conductive layer 320 away from the reflective layer 310, and is coated on the periphery of the conductive layer 320. The material of the second insulating layer 330 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or aluminum oxide.
The metal layer 340 is located at a side of the second insulating layer 330 remote from the conductive layer 320, and has a conductive post 341 electrically connected to the first epitaxial layer 210. The material of the metal layer 340 includes one or at least two of Al, ni, ti, pt or Au. The conductive column 341 extends into the first semiconductor layer 211 and is electrically connected to the first semiconductor layer 211, which is substantially a first electrode, and the sidewall of the conductive column 341 includes a second insulating layer 330 and a first insulating layer 300, where the second insulating layer 330 and the first insulating layer 300 insulate and protect the non-electrode area of the first epitaxial layer 210.
In one embodiment, the dicing area 500 outside the light-emitting mesa 200 includes at least one second partition 520, which can ensure uniform distribution of the electric potential in the light-emitting diode, avoid electromigration of the light-emitting diode, and improve reliability of the light-emitting diode. In the present embodiment, the cutting area 500 outside the light emitting mesa 200 includes four second partitions 520, and the second partitions 520 are equally spaced apart in the circumferential direction of the light emitting mesa 200.
In one embodiment, referring to fig. 5 to 8, the boss 511 is obtained by extending up a predetermined height from the metal layer 340, the second insulating layer 330, and the first insulating layer 300 in the structural layer. In the boss 511, the first insulating layer 300 and the second insulating layer 330 inside the boss are distributed in a trapezoid, and the trapezoid distribution manner can effectively improve the continuous direction of stress, reduce the continuous accumulation of stress, further reduce or eliminate the phenomena that the stress lines and the first epitaxial layer 210 are easy to peel and fall off, effectively improve the appearance yield of the light emitting diode, and improve the product quality of the light emitting diode.
Preferably, in the boss 511, the second insulating layer 330 covers the sidewall and the upper surface of the metal layer 340, and the first insulating layer 300 covers the sidewall and the upper surface of the second insulating layer 330.
In one embodiment, referring to fig. 5 to 8, the light emitting diode further includes a third insulating layer 700, the third insulating layer 700 covering the surface of the light emitting mesa 200, the sidewalls, and the region of the structural layer except the light emitting mesa 200 and exposing the contact electrode 600 and a portion of the surface of the light emitting mesa 200 for protecting the entire light emitting diode. The material of the third insulating layer 700 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or aluminum oxide.
According to one aspect of the present application, a method of manufacturing a light emitting diode is provided. Fig. 9, 10, 12-18 disclose a schematic A-A cross-section of the led during different fabrication processes, fig. 11 discloses a schematic B-B cross-section of the led during formation of the first trench and the second trench, and fig. 19 discloses a schematic B-B cross-section of the led with the second epitaxial layer remaining at the second region. The preparation method comprises the following steps:
s1, referring to fig. 9, a semiconductor stack layer is formed on a substrate 100. The semiconductor stack layer is used to form a first epitaxial layer 210 and a second epitaxial layer 220.
The substrate 100 is one of a sapphire patterned substrate, a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, a silicon carbide substrate, a silicon substrate, or the like. In this embodiment, the substrate 100 is specifically a sapphire patterned substrate or a sapphire flat bottom substrate.
A semiconductor stack layer is formed on the substrate 100. The semiconductor stack layer includes, from bottom to top, a first semiconductor layer 211, an active layer 212, and a second semiconductor layer 213. In this embodiment, the first semiconductor layer 211 is an N-type semiconductor layer, the second semiconductor layer 213 is a P-type semiconductor layer, and the active layer 212 is a multi-layer quantum well layer. The N-type semiconductor layer, the multi-layer quantum well layer and the P-type semiconductor layer are only basic constituent units of the semiconductor stacked layer, and the semiconductor stacked layer can also comprise other functional structure layers with an optimization function on the performance of the light-emitting diode chip.
S2, referring to fig. 10 and 11, the semiconductor stack layer is etched, and a first trench 214 for providing the boss 511 and a second trench 215 for providing the conductive column 341 are formed; the first trenches 214 are intermittently distributed annular structures and have a depth less than the height of the semiconductor stack layers. The first trench 214 and the second trench 215 each extend from the second semiconductor layer 213 to the inside of the first semiconductor layer 211, and the depths of the first trench 214 and the second trench 215 are equal.
S3, forming a structural layer on the semiconductor stacked layer, wherein the structural layer at least comprises a first insulating layer 300, a second insulating layer 330 and a metal layer 340 from bottom to top, and the first insulating layer 300, the second insulating layer 330 and the metal layer 340 extend to the first groove 214 and form a boss 511; the structural layer is bonded to the substrate 400.
Specifically, forming a structural layer on a semiconductor stack layer includes the steps of:
s31, referring to fig. 12, a transparent conductive layer 350 is formed on the second semiconductor layer 213 in the etched semiconductor stack layer, and the transparent conductive layer 350 includes, but is not limited to, indium tin oxide, indium oxide, tin oxide, cadmium tin oxide, antimony tin oxide, zinc oxide, or gallium phosphide.
The first insulating layer 300 is formed on the transparent conductive layer 350, the second semiconductor layer 213, the sidewall and bottom of the first trench 214, and the sidewall of the second trench 215, where the first insulating layer 300 has a first opening 301 extending to the transparent conductive layer 350, and in a vertical projection, the first opening 301 is located in the transparent conductive layer 350. The material of the first insulating layer 300 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or aluminum oxide.
S32, referring to fig. 13, a reflective layer 310 is formed on the first insulating layer 300 above the second semiconductor layer 213, and the reflective layer 310 fills the first opening 301. The material of the reflective layer 310 is preferably silver.
S33, referring to fig. 14, a conductive layer 320 is formed on the reflective layer 310, and the conductive layer 320 is coated on the periphery of the reflective layer 310. The material of the conductive layer 320 is Ag, au, ti, al, cr, pt, tiW alloy, ni or any combination thereof, and the material of the conductive layer 320 is preferably Ti, au, cr, pt, tiW alloy with relatively stable performance.
S34, referring to fig. 15, a second insulating layer 330 is formed on the conductive layer 320, where the second insulating layer 330 wraps around the conductive layer 320 and covers the sidewalls of the second trench 215, so as to insulate and protect the non-electrically connected region of the semiconductor stacked layer. Preferably, the second insulating layer 330 also covers the sidewalls and bottom of the first trench 214. The material of the second insulating layer 330 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or aluminum oxide.
In S35, referring to fig. 16, a metal layer 340 is formed on the surface of the second insulating layer 330, the first trench 214 and the second trench 215, the metal layer 340 includes a conductive pillar 341 electrically connected to the semiconductor stacked layer, and the conductive pillar 341 extends into the first semiconductor layer 211 and is electrically connected to the first semiconductor layer 211, which is substantially the first electrode. The material of the metal layer 340 includes one or at least two of Al, ni, ti, pt or Au.
Specifically, referring to fig. 16, the semiconductor stack layer is bonded to a substrate 400 through a metal layer 340, the substrate 400 being a permanent substrate for transferring the semiconductor stack layer grown on the substrate 100. The material of the substrate 400 is selected from GaAs, ge, si, cu, mo, WCu or MoCu.
S4, referring to FIGS. 17-19, removing the substrate 100; etching the semiconductor stack layer and forming a light emitting mesa 200, the light emitting mesa 200 including a first epitaxial layer 210; the region surrounding the outside of the light emitting mesa 200 is a cutting region 500, the cutting region 500 includes a first partition 510 and a second partition 520 which are spaced apart in the circumferential direction of the light emitting mesa 200, the first partition 510 includes a boss 511, and the boss 511 is obtained by extending upward a predetermined height from the metal layer 340, the second insulating layer 330 and the first insulating layer 300 in the structural layer. The second partition 520 does not include a boss, ensures uniform distribution of potential in the light emitting diode, and improves reliability of the light emitting diode.
S5, referring to fig. 17 to 19, the semiconductor stack layer at the dicing area 500 is continuously etched, so that the second epitaxial layer 220 remains in the second partition 520, and the second epitaxial layer 220 extends from the second partition 520 onto the boss 511. The second epitaxial layer 220 encapsulates at least the end of the boss 511 near the second partition 520. The second epitaxial layer 220 is spaced apart from the light emitting mesa 200. The second epitaxial layer 220 covers at least one side of the mesa 511 adjacent to the light emitting mesa 200.
Specifically, the second epitaxial layer 220 includes a first portion 221 and a second portion 222 connected, the first portion 221 being located on the boss 511, and the second portion 222 being located in the second partition 520.
Preferably, referring to fig. 1 and 17, the first portion 221 covers the upper surface, the side wall, and the second portion 222 covers the entire area of the second partition 520 in the circumferential direction of the light emitting mesa. The width of the first portion 221 is preferably equal to the width of the second portion 222, and the width of both the first portion 221 and the second portion 222 is greater than the width of the boss 511.
Preferably, referring to fig. 2 and 18, the first portion 221 is configured in a U shape with the U-shaped opening toward the opposite side of the second partition 520, the first portion 221 extending inward from the outer wall surface of the boss 511 by a preset width; the second portion 222 covers the entire area of the second partition 520 in the circumferential direction of the light emitting mesa.
Preferably, referring to fig. 3, in the circumferential direction of the light emitting mesa, the second portion 222 covers a partial region of the second partition 520, and the length of the second portion 222 in the circumferential direction of the light emitting mesa 200 is preferably less than 1/2 of the length of the second partition 520 in the circumferential direction of the light emitting mesa 200. The outer wall surface of the second portion 222 is preferably curved or sloped with the slope of the outer wall surface decreasing from bottom to top.
Preferably, referring to fig. 4, the second epitaxial layer 220 has a "T" shape, which covers a side of the boss 511 adjacent to the light emitting mesa 200 and a portion of the second partition 520 adjacent to the light emitting mesa 200. The side of the boss 511 remote from the light emitting mesa 200 and the portion of the second partition 520 remote from the light emitting mesa 200 are not covered with the second epitaxial layer 220. The width of the second portion 222 is greater than the width of the first portion 221. The first portion 221 covers only an end of the boss 511 near the second partition 520, and an outer wall surface of one side of the boss 511 away from the light emitting mesa 200.
Preferably, the height of the boss 511 is 40% -80% of the height of the light emitting mesa 200; the upper surface of the second epitaxial layer 220 is at the same height as the upper surface of the light emitting mesa 200.
Preferably, the height of the boss 511 is 40% -80% of the height of the light emitting mesa 200; the height of the upper surface of the second epitaxial layer 220 is 70% to 95% of the height of the upper surface of the light emitting mesa 200.
S6, referring to fig. 17 to 19, the first insulating layer 300 is etched and a second opening 302 is formed, and the second opening 302 and the first opening 301 are located on the same side of the conductive pillar 341 and vertically penetrate through the first insulating layer 300 to expose a portion of the conductive layer 320 beyond the reflective layer 310.
S7, a contact electrode 600 is formed on the exposed conductive layer 320, and the contact electrode 600 is in ohmic contact with the second semiconductor layer 213 through the second opening 302, the conductive layer 320, the reflective layer 310, the first opening 302, so as to electrically connect the contact electrode 600 with the second semiconductor layer 213, which is substantially a second electrode. The material of the contact electrode 600 includes one or at least two of Al, ni, ti, pt or Au.
Preferably, a third insulating layer 700 is formed on the surface, sidewalls and structural layer of the light emitting mesa 200 except for the light emitting mesa 200, and the third insulating layer 700 exposes the contact electrode 600 and a portion of the surface of the light emitting mesa 200 and serves to protect the entire light emitting diode. The material of the third insulating layer 700 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or aluminum oxide.
The light emitting diode in the above embodiment can be obtained after the above operation is completed.
According to the technical scheme, the second epitaxial layer 220 is arranged on the second partition 520 and the adjacent boss 511, the second epitaxial layer 220 can protect the second partition 520 and the end part of the boss 511, which is close to the second partition 520, so that the damage phenomenon such as a gap and the like at the joint of the boss 511 and the second partition 520 is effectively avoided, the phenomenon that etching liquid is easy to penetrate into the structural layer and damage the structural layer due to the damage phenomenon in the subsequent process is avoided, and the reliability of the light-emitting diode is improved.
The foregoing is merely a preferred embodiment of the present application, and it should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present application, and these modifications and substitutions should also be considered as being within the scope of the present application.
Claims (14)
1. A light emitting diode, comprising:
a substrate, the upper surface of which is provided with a light-emitting area and a cutting area surrounding the light-emitting area;
the structure layer is paved on the light-emitting area and the cutting area; the structure layer at least comprises a first insulating layer, a second insulating layer and a metal layer from top to bottom; a light-emitting table top is arranged on the structural layer at the light-emitting area, and the light-emitting table top comprises a first epitaxial layer;
the cutting area comprises a first partition area and a second partition area which are arranged at intervals in the circumferential direction of the light-emitting table top; the first partition is provided with a boss which is connected to the structural layer and is formed by extending the first insulating layer, the second insulating layer and the metal layer upwards, the height of the boss is lower than that of the light-emitting table top, and the boss and the light-emitting table top are arranged at intervals; the second partition is provided with a second epitaxial layer, and the second epitaxial layer extends from the second partition to the boss; and the second epitaxial layer at least coats the end part of the boss, which is close to the second partition.
2. The light emitting diode of claim 1, wherein the second epitaxial layer is spaced apart from the light emitting mesa.
3. The led of claim 1, wherein the second epitaxial layer covers at least a side of the mesa adjacent the light emitting mesa.
4. The light emitting diode of claim 1, wherein the portion of the second epitaxial layer on the mesa is configured as a U-shape with the U-shaped opening facing opposite sides of the second partition.
5. The light emitting diode of claim 1, wherein a width of the second epitaxial layer at the mesa is equal to a width of the second epitaxial layer at the second region.
6. The light emitting diode of claim 1, wherein the second epitaxial layer covers an entire area or a partial area of the second partition in a circumferential direction of the light emitting mesa.
7. The led of claim 6, wherein when the second epitaxial layer covers a portion of the second partition in the circumferential direction of the light emitting mesa, the outer wall of the portion of the second epitaxial layer located in the second partition is curved or sloped with the slope of the outer wall decreasing from bottom to top.
8. The light emitting diode of claim 1, wherein an upper surface of the second epitaxial layer is at the same height as an upper surface of the light emitting mesa.
9. The light emitting diode of claim 1, wherein the layer structure of the second epitaxial layer is the same as the layer structure of the first epitaxial layer.
10. The led of claim 1, wherein the sum of lengths L of the first partitions in the circumferential direction of the light emitting mesa 1 Sum L of lengths of the second partition in the circumferential direction of the light emitting mesa 2 The ratio of (2) is 5-20.
11. The light-emitting diode according to any one of claims 1 to 10, wherein a reflective layer and a conductive layer are included between the first insulating layer and the second insulating layer, the reflective layer passes through the first insulating layer and is connected with the first epitaxial layer, the conductive layer is coated on the periphery of the reflective layer, and a contact electrode is electrically connected to the surface facing the first epitaxial layer; the second insulating layer is coated on the periphery of the conductive layer; the metal layer is provided with a conductive column electrically connected with the first epitaxial layer, and the side wall of the conductive column is coated with the second insulating layer and the first insulating layer.
12. The light emitting diode of claim 11, wherein the first epitaxial layer comprises a first semiconductor layer, an active layer, and a second semiconductor layer from top to bottom, the conductive pillar is electrically connected to the first semiconductor layer, and the contact electrode is electrically connected to the second semiconductor layer.
13. A method of manufacturing a light emitting diode, comprising:
forming a semiconductor stack layer on a substrate;
etching the semiconductor stacked layer, and forming a first groove for arranging a boss and a second groove for arranging a conductive post; the first grooves are of annular structures which are distributed intermittently, and the depth of the first grooves is smaller than the height of the semiconductor stacked layers;
forming a structural layer on the semiconductor stacked layer, wherein the structural layer at least comprises a first insulating layer, a second insulating layer and a metal layer from bottom to top, and the first insulating layer, the second insulating layer and the metal layer extend to the first groove and form a boss; bonding the structural layer to a substrate;
removing the substrate; etching the semiconductor stacked layer and forming a light emitting mesa, wherein the light emitting mesa comprises a first epitaxial layer; the cutting area comprises a first partition area and a second partition area which are arranged at intervals in the circumferential direction of the light-emitting table top, and the first partition area comprises a boss;
and continuing to etch the semiconductor stacked layer at the cutting area to ensure that a second epitaxial layer is reserved in the second partition, wherein the second epitaxial layer extends from the second partition to the boss, and at least coats the end part of the boss, which is close to the second partition, of the second epitaxial layer.
14. The method of claim 13, wherein the second epitaxial layer is spaced apart from the light emitting mesa.
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| KR20120039811A (en) * | 2010-10-18 | 2012-04-26 | 서울옵토디바이스주식회사 | High efficiency light emitting diode and method of fabricating the same |
| CN112335060A (en) * | 2020-04-09 | 2021-02-05 | 厦门市三安光电科技有限公司 | Light emitting diode device and preparation method thereof |
| CN112614920A (en) * | 2020-12-28 | 2021-04-06 | 厦门市三安光电科技有限公司 | Light emitting diode chip and preparation method thereof |
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| KR101669641B1 (en) * | 2012-06-28 | 2016-10-26 | 서울바이오시스 주식회사 | Light Emitting Diode for Surface Mount Technology, Method of manufacturing the same and Method of manufacturing of Light Emitting Diode Module |
| CN103022306B (en) * | 2012-12-21 | 2015-05-06 | 安徽三安光电有限公司 | Light emitting diode and production method thereof |
| US9425327B2 (en) * | 2013-11-18 | 2016-08-23 | Infineon Technologies Ag | Junction field effect transistor cell with lateral channel region |
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| KR20120039811A (en) * | 2010-10-18 | 2012-04-26 | 서울옵토디바이스주식회사 | High efficiency light emitting diode and method of fabricating the same |
| CN112335060A (en) * | 2020-04-09 | 2021-02-05 | 厦门市三安光电科技有限公司 | Light emitting diode device and preparation method thereof |
| CN112614920A (en) * | 2020-12-28 | 2021-04-06 | 厦门市三安光电科技有限公司 | Light emitting diode chip and preparation method thereof |
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