CN114141920A - Light emitting diode and preparation method thereof - Google Patents
Light emitting diode and preparation method thereof Download PDFInfo
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- CN114141920A CN114141920A CN202111376242.7A CN202111376242A CN114141920A CN 114141920 A CN114141920 A CN 114141920A CN 202111376242 A CN202111376242 A CN 202111376242A CN 114141920 A CN114141920 A CN 114141920A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
Abstract
The application discloses a light-emitting diode and a preparation method thereof, wherein the light-emitting diode comprises a substrate, a structural layer and a light-emitting table top, wherein a light-emitting area and a cutting area surrounding the light-emitting area are arranged on the upper surface of the substrate; the structural layer is laid on the light emitting area and the cutting area; a light emitting table top is arranged on the structural layer at the light emitting region and comprises a first epitaxial layer; the cutting area comprises a first subarea and a second subarea which are arranged at intervals in the circumferential direction of the light-emitting table top, the first subarea is provided with a boss, and the boss is connected on the structural layer and is obtained by upwards extending a first insulating layer, a second insulating layer and a metal layer in the structural layer; the second partition is formed with a second epitaxial layer extending from the second partition onto the mesa. According to the method, the second epitaxial layer is arranged on the second partition and the boss adjacent to the second partition, so that a gap can be prevented from being formed at the joint of the boss and the second partition, and further etching liquid in a follow-up process is prevented from permeating into the structural layer and damaging the structural layer.
Description
Technical Field
The application relates to the technical field of semiconductor correlation, in particular to a light-emitting diode and a preparation method thereof.
Background
Light emitting diodes have been widely used in many fields due to their high luminous efficiency. The light-emitting diode comprises a light-emitting table top and a cutting area surrounding the light-emitting table top, and because the light-emitting table top, the structural layer and the substrate have different thermal expansion coefficients, the light-emitting diode is easy to generate stress with different sizes, and even is easy to generate stress lines or the phenomena of breakage and falling of the light-emitting table top. In order to solve the above problem, a boss surrounding the light emitting mesa is formed in the cutting region.
After the lug boss surrounding the light-emitting table surface is introduced, the potential distribution of the whole light-emitting diode is not uniform, so that the phenomenon of electromigration of the light-emitting diode is easily caused, and the reliability of the light-emitting diode is influenced. Therefore, in order to improve the phenomenon that the light emitting diode is easy to generate electromigration, the cutting area is divided into a first subarea and a second subarea, and a boss is only formed in the first subarea, so that the phenomenon that the light emitting diode generates electromigration is avoided.
However, after the cutting area is divided into the first partition and the second partition, and the bosses are formed only in the first partition, since the heights of the first partition and the second partition are different, the distance between adjacent bosses is small, and a crack or other damage phenomenon is likely to occur at the joint of the bosses and the second partition in a subsequent process, so that an etching solution penetrates into the structural layer and damages the structural layer, thereby affecting the reliability of the light emitting diode.
Disclosure of Invention
An object of the application is to provide a light emitting diode, it is through setting up the second epitaxial layer on second subregion and rather than adjacent boss, can avoid the boss to appear the gap with the department of meeting of second subregion, and then avoids etching solution to permeate to in the structural layer and cause the damage to the structural layer in the follow-up technology, improves light emitting diode's reliability.
Another object is to provide a method for manufacturing the light emitting diode.
In a first aspect, an embodiment of the present application provides a light emitting diode, which includes:
the upper surface of the substrate is provided with a luminous zone and a cutting zone surrounding the luminous zone;
the structure layer is laid on the light emitting area and the cutting area; the structural layer at least comprises a first insulating layer, a second insulating layer and a metal layer from top to bottom; a light emitting table top is arranged on the structural layer at the light emitting region and comprises a first epitaxial layer;
the cutting area comprises a first partition and a second partition, and the first partition and the second partition are arranged at intervals in the circumferential direction of the light-emitting table top; the first subarea is provided with a boss, the boss is connected on the structural layer and is obtained by upwards extending a first insulating layer, a second insulating layer and a metal layer, the height of the boss is lower than that of the light-emitting table top, and the boss and the light-emitting table top are arranged at intervals; the second partition is formed with a second epitaxial layer extending from the second partition onto the mesa.
In one possible embodiment, the second epitaxial layer wraps around at least an end portion of the mesa near the second segment.
In one possible embodiment, the second epitaxial layer is spaced apart from the light emitting mesa.
In one possible embodiment, the second epitaxial layer covers at least a side of the mesa adjacent the light emitting mesa.
In one possible embodiment, the portion of the second epitaxial layer on the mesa is configured as a U-shape with the U-shaped opening facing the opposite side of the second partition.
In one possible implementation, the width of the second epitaxial layer at the mesa is equal to the width of the second epitaxial layer at the second partition.
In a possible embodiment, the second epitaxial layer covers the entire region or a partial region of the second partition in the circumferential direction of the light emitting mesa.
In a possible implementation manner, when the second epitaxial layer covers a partial region of the second partition in the circumferential direction of the light-emitting table, the outer wall surface of the portion of the second epitaxial layer located in the second partition is arc-shaped or inclined, and the inclination of the outer wall surface decreases from bottom to top.
In one possible embodiment, the upper surface of the second epitaxial layer is level with the upper surface of the light emitting mesa.
In a possible embodiment, the layer structure of the second epitaxial layer is identical to the layer structure of the first epitaxial layer.
In a possible embodiment, the sum L of the lengths of the first sections in the circumferential direction of the luminous mesa1The total length L of the second partition and the light-emitting table surface in the circumferential direction2The ratio of (A) to (B) is 5 to 20.
In a possible embodiment, a reflecting layer and a conducting layer are included between the first insulating layer and the second insulating layer, the reflecting layer penetrates through the first insulating layer to be connected with the first epitaxial layer, the conducting layer wraps the periphery of the reflecting layer, and the surface facing the first epitaxial layer is electrically connected with a contact electrode; the second insulating layer is wrapped on the periphery of the conducting layer; the metal layer is provided with a conductive column electrically connected with the first epitaxial layer, and the side wall of the conductive column is coated with a second insulating layer and a first insulating layer.
In one possible embodiment, the first epitaxial layer includes, from top to bottom, a first semiconductor layer, an active layer, and a second semiconductor layer, the conductive pillar is electrically connected to the first semiconductor layer, and the contact electrode is electrically connected to the second semiconductor layer.
In a second aspect, an embodiment of the present application provides a method for manufacturing a light emitting diode, including:
forming a semiconductor stack layer on a substrate;
etching the semiconductor stacking layer, and forming a first groove for arranging the boss and a second groove for arranging the conductive post; the first grooves are in an annular structure which is distributed discontinuously, and the depth of the first grooves is smaller than the height of the semiconductor stacked layer;
forming a structural layer on the semiconductor stacking layer, wherein the structural layer at least comprises a first insulating layer, a second insulating layer and a metal layer from bottom to top, and the first insulating layer, the second insulating layer and the metal layer extend to the first groove and form a boss; bonding the structural layer to the substrate;
removing the substrate; etching the semiconductor stack layer and forming a light-emitting table top, wherein the light-emitting table top comprises a first epitaxial layer; the area surrounding the light-emitting table top is a cutting area, the cutting area comprises a first subarea and a second subarea which are arranged at intervals in the circumferential direction of the light-emitting table top, and the first subarea comprises a boss;
and continuously etching the semiconductor stack layer at the cutting area to ensure that the second epitaxial layer is reserved in the second area and extends to the boss from the second area.
In one possible embodiment, the second epitaxial layer covers at least an end portion of the mesa near the second segment; the second epitaxial layer is arranged at intervals with the light-emitting table top.
Compared with the prior art, the application has at least the following beneficial effects:
this application sets up the second epitaxial layer on second subregion and rather than adjacent boss, and the second epitaxial layer can be protected the tip that is close to the second subregion in second subregion and the boss, effectively avoids the boss and the department of meeting of second subregion damaged phenomena such as gap appear, and then avoids easily permeating to the structural layer and cause the phenomenon of damage to the structural layer because of having the etching solution that damaged phenomenon leads to in the follow-up technology, improves emitting diode's reliability.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a top view of a light emitting diode according to an embodiment of the present application;
FIG. 2 is a top view of a light emitting diode according to an embodiment of the present application;
FIG. 3 is a top view of a light emitting diode according to an embodiment of the present application;
FIG. 4 is a top view of an LED according to an embodiment of the present application;
FIG. 5 is a schematic cross-sectional view A-A of a light emitting diode according to an embodiment of the present application;
FIG. 6 is a schematic cross-sectional view A-A of a light emitting diode according to an embodiment of the present application;
FIG. 7 is a schematic cross-sectional view B-B of a light emitting diode according to an embodiment of the present application;
FIG. 8 is a schematic cross-sectional view B-B of a light emitting diode according to an embodiment of the present application
Fig. 9 to 19 are schematic structural diagrams illustrating a light emitting diode at different stages of manufacturing according to an embodiment of the present application.
Illustration of the drawings:
100 a substrate; 200 of a light emitting table top; 210 a first epitaxial layer; 211 a first semiconductor layer; 212 an active layer; 213 a second semiconductor layer; 214 a first trench; 215 a second trench; 220 a second epitaxial layer; 221 a first section; 222 a second portion; 300 a first insulating layer; 301 a first opening; 302 a second opening; 310 a reflective layer; 320 a conductive layer; 330 a second insulating layer; 340 a metal layer; 341 conductive posts; 350 a transparent conductive layer; 400 a substrate; 500 cutting area; 510 a first partition; 511 boss; 520 a second partition; 600 contacting the electrode; 700 a third insulating layer.
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and variations in various respects, all without departing from the spirit of the present application.
In the description of the present application, it should be noted that the terms "upper" and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements that are referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second," etc. are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
According to one aspect of the present application, a light emitting diode is provided. Fig. 1 to 4 are plan views of the light emitting diode, fig. 5 and 6 are schematic sectional views a-a of the light emitting diode, and fig. 7 and 8 are schematic sectional views B-B of the light emitting diode. The curve a in fig. 1 to 4 is a cut line of the light emitting diode. Each of regions I in fig. 5 to 8 is a light emitting diode cut along a cutting line a.
The light emitting diode includes a substrate 400, a structure layer, and a light emitting mesa 200. The upper surface of the substrate 400 is provided with a light emitting region and a cutting region 500 surrounding the light emitting region. The structural layer is laid on the light emitting region and the cutting region 500, and the structural layer at least comprises a first insulating layer 300, a second insulating layer 330 and a metal layer 340 from top to bottom; a light emitting mesa 200 is disposed on the structural layer at the light emitting region, and the light emitting mesa 200 includes a first epitaxial layer 210. The cutting region 500 includes a first partition 510 and a second partition 520, the first partition 510 and the second partition 520 being arranged at intervals in a circumferential direction of the light emitting table 200; the first sub-region 510 is formed with a protrusion 511, the protrusion 511 is connected to the structural layer and is extended upward from the first insulating layer 300, the second insulating layer 330 and the metal layer 340, the height of the protrusion 511 is lower than that of the light emitting mesa 200, and the protrusion 511 is spaced apart from the light emitting mesa 200. The second sub-region 520 is formed with a second epitaxial layer 220, the second epitaxial layer 220 extending from the second sub-region 520 onto the mesa 511. The circumferential direction of the light emitting mesa refers to the circumferential direction of the side wall of the light emitting mesa.
The layer structure of the second epitaxial layer 220 is the same as that of the first epitaxial layer 210, and is formed by etching the semiconductor stack. The semiconductor stacked layer comprises a first semiconductor layer 211, an active layer 212 and a second semiconductor layer 213 from top to bottom, wherein the first semiconductor layer 211 is an N-type semiconductor layer, the second semiconductor layer 213 is a P-type semiconductor layer, and the active layer 212 is a multi-layer quantum well layer. The N-type semiconductor layer, the multi-layer quantum well layer and the P-type semiconductor layer are only basic constituent units of the semiconductor stacked layer, and on the basis, the semiconductor stacked layer can also comprise other functional structure layers with an optimization effect on the performance of the light emitting diode.
The base plate 400 is a permanent base plate for transferring the light emitting mesas 200 grown on the substrate 100. The material of the substrate 400 is selected from GaAs, Ge, Si, Cu, Mo, WCu or MoCu.
The second epitaxial layer 220 is arranged on the second partition 520 and the boss 511 adjacent to the second partition 520, so that the second epitaxial layer 220 at least covers the second partition 520 and the end part of the boss 511 in the circumferential direction of the light-emitting table top 200, the end part of the boss 511 close to the second partition 520 in the second partition 520 is protected, the phenomena of gaps and the like at the joint of the boss 511 and the second partition 520 are effectively avoided, the phenomena that etching liquid easily permeates into a structural layer and damages the structural layer due to the damage phenomenon in the subsequent process are further avoided, and the reliability of the light-emitting diode is improved.
In one embodiment, referring to fig. 1-4, the second epitaxial layer 220 covers at least the end of the mesa 511 near the second partition 520, and the second epitaxial layer 220 is spaced apart from the light emitting mesa 200. The second epitaxial layer 220 covers at least one side of the mesa 511 adjacent to the light emitting mesa 200.
In one embodiment, the second epitaxial layer 220 includes a first portion 221 and a second portion 222 connected, the first portion 221 being located on the mesa 511, and the second portion 222 being located in the second partition 520.
Preferably, referring to fig. 1 and 5, the portion of the second epitaxial layer 220 located on the mesa 511 covers the upper surface and the sidewall of the mesa 511, the second epitaxial layer 220 covers the entire region of the second partition 520 in the circumferential direction of the light emitting mesa, and the width of the second epitaxial layer 220 at the mesa 511 is equal to the width of the second epitaxial layer 220 at the second partition 520. In other words, the first portion 221 covers the upper surface and the sidewall of the boss 511, and the second portion 222 covers the entire area of the second partition 520 in the circumferential direction of the light emitting mesa. The width of the first portion 221 is preferably equal to the width of the second portion 222, and the widths of the first portion 221 and the second portion 222 are both greater than the width of the boss 511.
Preferably, referring to fig. 2 and 6, the portion of the second epitaxial layer 220 on the mesa 511 is configured as a U shape, and the U-shaped opening faces the opposite side of the second partition 520; the second epitaxial layer 220 covers the entire area of the second partition 520 in the circumferential direction of the light emitting mesa. In other words, the first portion 221 is configured in a U shape with a U-shaped opening facing the opposite side of the second partition 520, the first portion 221 extends inward from the outer wall surface of the boss 511 by a predetermined width; the second portion 222 covers the entire area of the second partition 520 in the circumferential direction of the light emitting mesa.
As an alternative embodiment, referring to fig. 3, the second epitaxial layer 220 covers a partial region of the second partition 520 in a circumferential direction of the light emitting mesa. In other words, the second portion 222 covers a partial area of the second partition 520 in the circumferential direction of the light emitting table top, and the length of the second portion 222 in the circumferential direction of the light emitting table top 200 is preferably 1/2 smaller than the length of the second partition 520 in the circumferential direction of the light emitting table top 200.
Preferably, the outer wall surface of the portion of the second epitaxial layer 220 located in the second partition 520 is configured to be an arc or a slope, that is, the outer wall surface of the second portion 222 is an arc or a slope, and the slope of the outer wall surface decreases from bottom to top. The portion of the second epitaxial layer 220 located in the second partition 520 is configured to have the above structure, so that the second epitaxial layer 220 can be smoothly transited to the second partition 520 without the second epitaxial layer 220, a gap is prevented from occurring at a joint of the second epitaxial layer 220 and the second partition 520 without the second epitaxial layer 220, and further etching solution is prevented from permeating into the structural layer and damaging the structural layer in a subsequent process, and the reliability of the light emitting diode is improved.
In one embodiment, referring to fig. 4, the second epitaxial layer 220 is "T" shaped, covering a side of the mesa 511 adjacent to the light emitting mesa 200 and a portion of the second partition 520 adjacent to the light emitting mesa 200. The side of the mesa 511 remote from the light emitting mesa 200 and the portion of the second partition 520 remote from the light emitting mesa 200 are not covered with the second epitaxial layer 220.
Preferably, in the second epitaxial layer 220, the width of the second portion 222 is greater than the width of the first portion 221.
Preferably, the first portion 221 covers only an end portion of the boss 511 near the second partition 520, and one side outer wall surface of the boss 511 near the light emitting mesa 200.
In one embodiment, referring to fig. 5 and 6, the height of the bosses 511 is 40% to 80% of the height of the light emitting mesa 200; the upper surface of the second epitaxial layer 220 is as high as the upper surface of the light emitting mesa 200.
As an alternative embodiment, the height of the boss 511 is 40% to 80% of the height of the light emitting mesa 200; the height of the upper surface of the second epitaxial layer 220 is 70% to 95% of the height of the upper surface of the light emitting mesa 200.
In one embodiment, the sum L of the lengths of the first sections 510 in the circumferential direction of the light emitting mesa 2001The total length L of the second partition 520 in the circumferential direction of the light emitting table 2002The ratio of (A) to (B) is 5 to 20.
In one embodiment, referring to fig. 5 to 8, a reflective layer 310 and a conductive layer 320 are included between a first insulating layer 300 and a second insulating layer 330. The reflective layer 310 is connected to the first epitaxial layer 210 through the first insulating layer 300. The conductive layer 320 is wrapped around the reflective layer 310, and the surface facing the first epitaxial layer 210 is electrically connected to the contact electrode 600. The second insulating layer 330 covers the periphery of the conductive layer 320. The metal layer 340 has a conductive pillar 341 electrically connected to the first epitaxial layer 210, and a sidewall of the conductive pillar 341 is covered with the second insulating layer 330 and the first insulating layer 300.
Preferably, a transparent conductive layer 350 is included between the first insulating layer 300 and the first epitaxial layer 210, and the reflective layer 310 contacts the transparent conductive layer 350 through the first insulating layer 300.
Specifically, the first insulating layer 300 under the first epitaxial layer 210 is provided with a plurality of first openings 301, and the first openings 301 penetrate through the first insulating layer 300 in the vertical direction. The reflective layer 310 is located under the first insulating layer 300 and fills the first opening 301 in the first insulating layer 300. The material of the first insulating layer 300 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium dioxide, or aluminum oxide. The material of the reflective layer 310 includes, but is not limited to, silver.
The conductive layer 320 is located below the reflective layer 310 and covers the reflective layer 310. The first insulating layer 300 has a second opening 302, and the second opening 302 and the first opening 301 are located on the same side of the conductive pillar 341 and vertically penetrate through the first insulating layer 300. The contact electrode 600 is formed at the second opening 302, and the contact electrode 600 is in ohmic contact with the second semiconductor layer 213 through the second opening 302, the conductive layer 320, the reflective layer 310, the first opening 301, and the second semiconductor layer 213 to electrically connect the contact electrode 600 and the second semiconductor layer 213, which is substantially a second electrode. The conductive layer 320 is made of Ag, Au, Ti, Al, Cr, Pt, TiW alloy, Ni, or any combination thereof, and the conductive layer 320 is preferably made of Ti, Au, Cr, Pt, TiW alloy having stable properties. The material of the contact electrode 600 includes one or at least two of Al, Ni, Ti, Pt, or Au.
The second insulating layer 330 is disposed on a side of the conductive layer 320 away from the reflective layer 310 and covers the conductive layer 320. The material of the second insulating layer 330 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium dioxide, or aluminum oxide.
The metal layer 340 is located on a side of the second insulating layer 330 away from the conductive layer 320, and has a conductive pillar 341 electrically connected to the first epitaxial layer 210. The material of the metal layer 340 includes one or at least two of Al, Ni, Ti, Pt, or Au. The conductive pillar 341 extends into the first semiconductor layer 211 and is electrically connected to the first semiconductor layer 211, and is substantially a first electrode, the sidewall of the conductive pillar 341 includes a second insulating layer 330 and a first insulating layer 300, and the second insulating layer 330 and the first insulating layer 300 perform insulation protection on the non-electrode-disposed region of the first epitaxial layer 210.
In one embodiment, the cutting region 500 outside the light emitting mesa 200 includes at least one second partition 520, which can ensure that the electric potential in the light emitting diode is uniformly distributed, prevent the light emitting diode from electromigration, and improve the reliability of the light emitting diode. In the present embodiment, the cutting zone 500 outside the lighting mesa 200 comprises four second sub-zones 520, the second sub-zones 520 being arranged at equal intervals in the circumferential direction of the lighting mesa 200.
In one embodiment, referring to fig. 5 to 8, the mesa 511 is formed by extending the metal layer 340, the second insulating layer 330, and the first insulating layer 300 in the structural layer up to a predetermined height. In the boss 511, the first insulating layer 300 and the second insulating layer 330 inside the boss 511 are distributed in a trapezoidal manner, and the trapezoidal distribution manner can effectively improve the continuous direction of stress and reduce the continuous accumulation of stress, thereby reducing or eliminating the phenomena that stress lines and the first epitaxial layer 210 are easy to peel off and fall off, effectively improving the appearance yield of the light emitting diode, and improving the product quality of the light emitting diode.
Preferably, in the bump 511, the second insulating layer 330 covers the sidewall and the upper surface of the metal layer 340, and the first insulating layer 300 covers the sidewall and the upper surface of the second insulating layer 330.
In one embodiment, referring to fig. 5 to 8, the light emitting diode further includes a third insulating layer 700, where the third insulating layer 700 covers the surface, the sidewalls, and the structural layer of the light emitting mesa 200 except for the light emitting mesa 200 and exposes the contact electrode 600 and a portion of the surface of the light emitting mesa 200, which is used to protect the entire light emitting diode. The material of the third insulating layer 700 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium dioxide, or aluminum oxide.
According to one aspect of the present application, a method of fabricating a light emitting diode is provided. Fig. 9, 10, 12-18 show a cross-sectional view a-a of the led during different fabrication processes, fig. 11 shows a cross-sectional view B-B of the led during formation of the first trench and the second trench, and fig. 19 shows a cross-sectional view B-B of the led with the second epitaxial layer remaining at the second partition. The preparation method comprises the following steps:
s1, referring to fig. 9, a semiconductor stack layer is formed on the substrate 100. The semiconductor stack is used to form a first epitaxial layer 210 and a second epitaxial layer 220.
The substrate 100 is one of a sapphire patterned substrate, a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, a silicon carbide substrate, a silicon substrate, or the like. In the present embodiment, the substrate 100 is embodied as a sapphire patterned substrate or a sapphire flat-bottomed substrate.
A semiconductor stack is formed on a substrate 100. The semiconductor stacked layer includes, from bottom to top, a first semiconductor layer 211, an active layer 212, and a second semiconductor layer 213. In this embodiment, the first semiconductor layer 211 is an N-type semiconductor layer, the second semiconductor layer 213 is a P-type semiconductor layer, and the active layer 212 is a multi-layer quantum well layer. The N-type semiconductor layer, the multi-layer quantum well layer and the P-type semiconductor layer are only basic constituent units of the semiconductor stacked layer, and on the basis, the semiconductor stacked layer can also comprise other functional structure layers with an optimization effect on the performance of the light emitting diode chip.
S2, referring to fig. 10 and 11, the semiconductor stack is etched, and a first trench 214 for disposing the mesa 511 and a second trench 215 for disposing the conductive pillar 341 are formed; the first trenches 214 are in a ring shape with a discontinuous distribution, and have a depth smaller than the height of the semiconductor stack. The first trench 214 and the second trench 215 both extend from the second semiconductor layer 213 to the inside of the first semiconductor layer 211, and the depths of the first trench 214 and the second trench 215 are equal.
S3, forming a structural layer on the semiconductor stack layer, wherein the structural layer at least includes the first insulating layer 300, the second insulating layer 330 and the metal layer 340 from bottom to top, and the first insulating layer 300, the second insulating layer 330 and the metal layer 340 extend to the first trench 214 and form a boss 511; the structural layer is bonded to the substrate 400.
Specifically, the forming of the structural layer on the semiconductor stack layer comprises the following steps:
s31, referring to fig. 12, a transparent conductive layer 350 is formed on the second semiconductor layer 213 in the etched semiconductor stack, wherein the transparent conductive layer 350 includes, but is not limited to, indium tin oxide, indium oxide, tin oxide, cadmium tin oxide, antimony tin oxide, zinc oxide, or gallium phosphide.
A first insulating layer 300 is formed on the transparent conductive layer 350, the second semiconductor layer 213, the sidewall and the bottom of the first trench 214, and the sidewall of the second trench 215, wherein the first insulating layer 300 has a first opening 301 extending to the transparent conductive layer 350, and in a vertical projection, the first opening 301 is located in the transparent conductive layer 350. The material of the first insulating layer 300 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium dioxide, or aluminum oxide.
S32, referring to fig. 13, a reflective layer 310 is formed on the first insulating layer 300 over the second semiconductor layer 213, and the reflective layer 310 fills the first opening 301. The material of the reflective layer 310 is preferably silver.
S33, referring to fig. 14, a conductive layer 320 is formed on the reflective layer 310, and the conductive layer 320 covers the reflective layer 310. The conductive layer 320 is made of Ag, Au, Ti, Al, Cr, Pt, TiW alloy, Ni, or any combination thereof, and the conductive layer 320 is preferably made of Ti, Au, Cr, Pt, TiW alloy having stable properties.
S34, referring to fig. 15, a second insulating layer 330 is formed on the conductive layer 320, and the second insulating layer 330 covers the periphery of the conductive layer 320 and covers the sidewall of the second trench 215 to protect the non-electrical connection region of the semiconductor stack layer. Preferably, the second insulating layer 330 also covers the sidewalls and bottom of the first trench 214. The material of the second insulating layer 330 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium dioxide, or aluminum oxide.
S35, referring to fig. 16, a metal layer 340 is formed on the surface of the second insulating layer 330, the first trench 214 and the second trench 215, the metal layer 340 includes a conductive pillar 341 electrically connected to the semiconductor stack layer, and the conductive pillar 341 extends into the first semiconductor layer 211 and is electrically connected to the first semiconductor layer 211, and is substantially a first electrode. The material of the metal layer 340 includes one or at least two of Al, Ni, Ti, Pt, or Au.
Specifically, referring to fig. 16, the semiconductor stack is bonded to a base plate 400 through a metal layer 340, and the base plate 400 is a permanent base plate for transferring the semiconductor stack grown on the substrate 100. The material of the substrate 400 is selected from GaAs, Ge, Si, Cu, Mo, WCu or MoCu.
S4, see fig. 17 to 19, removing the substrate 100; etching the semiconductor stack layer and forming a light-emitting table 200, wherein the light-emitting table 200 comprises a first epitaxial layer 210; the region surrounding the light emitting mesa 200 is a cutting region 500, the cutting region 500 includes a first partition 510 and a second partition 520 spaced apart from each other in the circumferential direction of the light emitting mesa 200, the first partition 510 includes a boss 511, and the boss 511 is obtained by extending the metal layer 340, the second insulating layer 330 and the first insulating layer 300 in the structural layer by a predetermined height. The second sub-area 520 does not include a boss, so that the electric potential in the light emitting diode is uniformly distributed, and the reliability of the light emitting diode is improved.
S5, referring to fig. 17-19, the semiconductor stack layer at the dicing area 500 is etched continuously, such that the second epitaxial layer 220 remains in the second partition 520, and the second epitaxial layer 220 extends from the second partition 520 to the pad 511. The second epitaxial layer 220 wraps around at least the end of the mesa 511 near the second partition 520. The second epitaxial layer 220 is disposed spaced apart from the light emitting mesa 200. The second epitaxial layer 220 covers at least one side of the mesa 511 adjacent to the light emitting mesa 200.
Specifically, the second epitaxial layer 220 includes a first portion 221 and a second portion 222 connected, the first portion 221 being located on the mesa 511, and the second portion 222 being located in the second partition 520.
Preferably, referring to fig. 1 and 17, the first portion 221 covers an upper surface, a sidewall, of the boss 511, and the second portion 222 covers an entire area of the second partition 520 in a circumferential direction of the light emitting mesa. The width of the first portion 221 is preferably equal to the width of the second portion 222, and the widths of the first portion 221 and the second portion 222 are both greater than the width of the boss 511.
Preferably, referring to fig. 2 and 18, the first portion 221 is configured in a U shape with a U-shaped opening facing an opposite side of the second partition 520, the first portion 221 extending inward from an outer wall surface of the boss 511 by a predetermined width; the second portion 222 covers the entire area of the second partition 520 in the circumferential direction of the light emitting mesa.
Preferably, referring to fig. 3, the second portion 222 covers a partial area of the second partition 520 in the circumferential direction of the light emitting table top, and the length of the second portion 222 in the circumferential direction of the light emitting table top 200 is preferably smaller than 1/2 of the length of the second partition 520 in the circumferential direction of the light emitting table top 200. The outer wall surface of the second portion 222 is preferably curved or sloped, and the slope of the outer wall surface decreases from bottom to top.
Preferably, referring to fig. 4, the second epitaxial layer 220 has a "T" shape, which covers a side of the mesa 511 near the light emitting mesa 200 and a portion of the second partition 520 near the light emitting mesa 200. The side of the mesa 511 remote from the light emitting mesa 200 and the portion of the second partition 520 remote from the light emitting mesa 200 are not covered with the second epitaxial layer 220. The width of the second portion 222 is greater than the width of the first portion 221. The first portion 221 covers only an end portion of the boss 511 close to the second partition 520, and an outer wall surface of one side of the boss 511 far from the light emitting mesa 200.
Preferably, the height of the boss 511 is 40% -80% of the height of the light emitting table-board 200; the upper surface of the second epitaxial layer 220 is as high as the upper surface of the light emitting mesa 200.
Preferably, the height of the boss 511 is 40% -80% of the height of the light emitting table-board 200; the height of the upper surface of the second epitaxial layer 220 is 70% to 95% of the height of the upper surface of the light emitting mesa 200.
S6, referring to fig. 17 to 19, the first insulating layer 300 is etched to form a second opening 302, and the second opening 302 and the first opening 301 are both located on the same side of the conductive pillar 341 and vertically penetrate through the first insulating layer 300 to expose the portion of the conductive layer 320 that exceeds the reflective layer 310.
S7, forming a contact electrode 600 on the exposed conductive layer 320, wherein the contact electrode 600 is in ohmic contact with the second semiconductor layer 213 through the second opening 302, the conductive layer 320, the reflective layer 310, the first opening 302, and the second semiconductor layer 213 to electrically connect the contact electrode 600 and the second semiconductor layer 213, which is substantially a second electrode. The material of the contact electrode 600 includes one or at least two of Al, Ni, Ti, Pt, or Au.
Preferably, a third insulating layer 700 is formed on the surface, sidewalls and structural layer of the light emitting mesa 200 except the light emitting mesa 200, and the third insulating layer 700 exposes the contact electrode 600 and a portion of the surface of the light emitting mesa 200 and protects the entire light emitting diode. The material of the third insulating layer 700 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, titanium dioxide, or aluminum oxide.
After the above operations are completed, the light emitting diode in the above embodiment can be obtained.
According to the technical scheme, the second epitaxial layer 220 is arranged on the second partition 520 and the boss 511 adjacent to the second partition 520, the second epitaxial layer 220 can protect the second partition 520 and the end part, close to the second partition 520, of the boss 511, the damage phenomena such as gaps and the like at the joint of the boss 511 and the second partition 520 are effectively avoided, the phenomena that etching liquid is easy to permeate into a structural layer and damages the structural layer due to the damage phenomena in the subsequent process are further avoided, and the reliability of the light emitting diode is improved.
The foregoing is only a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and substitutions can be made without departing from the technical principle of the present application, and these modifications and substitutions should also be regarded as the protection scope of the present application.
Claims (15)
1. A light emitting diode, comprising:
the upper surface of the substrate is provided with a light emitting area and a cutting area surrounding the light emitting area;
the structural layer is laid on the light emitting area and the cutting area; the structural layer at least comprises a first insulating layer, a second insulating layer and a metal layer from top to bottom; a light emitting table top is arranged on the structural layer at the light emitting region, and the light emitting table top comprises a first epitaxial layer;
the cutting area comprises a first partition and a second partition, and the first partition and the second partition are arranged at intervals in the circumferential direction of the light-emitting table top; the first partition is provided with a boss, the boss is connected to the structural layer and is obtained by upwards extending the first insulating layer, the second insulating layer and the metal layer, the height of the boss is lower than that of the light-emitting table top, and the boss and the light-emitting table top are arranged at intervals; the second partition is formed with a second epitaxial layer extending from the second partition onto the boss.
2. The led of claim 1, wherein the second epitaxial layer covers at least an end portion of the mesa proximate the second segment.
3. The led of claim 1, wherein the second epitaxial layer is spaced apart from the light emitting mesa.
4. The led of claim 1, wherein said second epitaxial layer covers at least a side of said mesa adjacent said light emitting mesa.
5. The led of claim 1, wherein the portion of the second epitaxial layer on the mesa is configured as a U-shape with the U-shaped opening facing an opposite side of the second segment.
6. The led of claim 1, wherein the width of the second epitaxial layer at the mesa is equal to the width of the second epitaxial layer at the second partition.
7. The led of claim 1, wherein the second epitaxial layer covers the entire area or a partial area of the second segment in a circumferential direction of the light emitting mesa.
8. The light-emitting diode of claim 7, wherein when the second epitaxial layer covers a partial region of the second partition in the circumferential direction of the light-emitting mesa, an outer wall surface of a portion of the second epitaxial layer located in the second partition is arc-shaped or inclined, and an inclination of the outer wall surface decreases from bottom to top.
9. The led of claim 1, wherein an upper surface of the second epitaxial layer is flush with an upper surface of the light emitting mesa.
10. The light-emitting diode of claim 1, wherein the layer structure of the second epitaxial layer is the same as the layer structure of the first epitaxial layer.
11. The led of claim 1, wherein the sum L of the lengths of the first segments in the circumferential direction of the light emitting mesa1The total length L of the second partition and the light-emitting table surface in the circumferential direction2The ratio of (A) to (B) is 5 to 20.
12. The light-emitting diode according to claims 1 to 11, wherein a reflective layer and a conductive layer are included between the first insulating layer and the second insulating layer, the reflective layer is connected with the first epitaxial layer through the first insulating layer, the conductive layer covers the periphery of the reflective layer, and a contact electrode is electrically connected to a surface facing the first epitaxial layer; the second insulating layer is wrapped on the periphery of the conducting layer; the metal layer is provided with a conductive column electrically connected with the first epitaxial layer, and the side wall of the conductive column is coated with the second insulating layer and the first insulating layer.
13. The led of claim 12, wherein the first epitaxial layer comprises, from top to bottom, a first semiconductor layer, an active layer, and a second semiconductor layer, the conductive pillar is electrically connected to the first semiconductor layer, and the contact electrode is electrically connected to the second semiconductor layer.
14. A method for manufacturing a light emitting diode, comprising:
forming a semiconductor stack layer on a substrate;
etching the semiconductor stacking layer, and forming a first groove for arranging a boss and a second groove for arranging a conductive column; the first grooves are in an annular structure which is distributed discontinuously, and the depth of the first grooves is smaller than the height of the semiconductor stacked layer;
forming a structural layer on the semiconductor stacking layer, wherein the structural layer at least comprises a first insulating layer, a second insulating layer and a metal layer from bottom to top, and the first insulating layer, the second insulating layer and the metal layer extend to the first groove and form a boss; bonding the structural layer to a substrate;
removing the substrate; etching the semiconductor stack layer and forming a light-emitting table top, wherein the light-emitting table top comprises a first epitaxial layer; the area surrounding the light-emitting table top is a cutting area, the cutting area comprises a first subarea and a second subarea which are arranged at intervals in the circumferential direction of the light-emitting table top, and the first subarea comprises a boss;
and continuously etching the semiconductor stack layer at the cutting region to enable a second epitaxial layer to be reserved in the second region, wherein the second epitaxial layer extends to the boss from the second region.
15. The method of claim 14, wherein the second epitaxial layer covers at least an end portion of the mesa near the second segment; the second epitaxial layer and the light-emitting table top are arranged at intervals.
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Effective date of registration: 20231016 Address after: Yuanqian village, Shijing Town, Nan'an City, Quanzhou City, Fujian Province Patentee after: QUANZHOU SAN'AN SEMICONDUCTOR TECHNOLOGY Co.,Ltd. Address before: 361009 no.1721-1725, Luling Road, Siming District, Xiamen City, Fujian Province Patentee before: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY Co.,Ltd. |