CN114141625B - Preparation method of T-shaped column chip for charge management - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 238000001259 photo etching Methods 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 67
- 239000011248 coating agent Substances 0.000 claims description 24
- 238000000576 coating method Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 description 12
- 238000000407 epitaxy Methods 0.000 description 11
- 239000000243 solution Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000006872 improvement Effects 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 241001270131 Agaricus moelleri Species 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003245 working effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention discloses a preparation method of a T-shaped column chip for charge management, which comprises the steps of forming a first groove on a first epitaxial layer, photoetching the first groove to form second grooves positioned at two sides of the first groove, photoetching and removing part of a second epitaxial layer along a first etching window to form a third groove, filling polycrystalline silicon into the third groove to form a first polycrystalline silicon layer, photoetching and removing the second epitaxial layer along a second etching window to form a fourth groove, photoetching the fourth groove, removing the second epitaxial layer in the second groove and part of the first polycrystalline silicon layer to form a fifth groove vertical to the fourth groove and a second polycrystalline silicon layer positioned on the fifth groove, removing the second polycrystalline silicon layer to expose the first groove, filling the third epitaxial layer into the first groove, removing the third epitaxial layer in the first groove, reserving the second epitaxial layer and the third epitaxial layer in the second groove, filling the fourth epitaxial layer into the first groove, adjusting charge balance of a PN column, and improving the working performance of a device.
Description
Technical Field
The invention relates to the technical field of semiconductor chip manufacturing processes, in particular to a preparation method of a T-shaped column chip for charge management.
Background
With the rapid development of the mobile internet, the functions of portable electronic products are more and more powerful, the use frequency is higher and higher, the overall power consumption is faster and faster, the endurance time becomes a problem to be solved urgently, the quick-charging technology is one of key technologies for solving the endurance problem, the quick-charging power management system is composed of a main circuit and a control circuit, and the main circuit mainly comprises a DC-DC voltage reduction conversion circuit, a quick-charging protocol identification circuit, a signal detection feedback circuit and other modules. The DC-DC conversion circuit module mainly completes the step-down conversion of input voltage according to a control signal, a core device of the module is a VDMOS power chip, the conversion efficiency and the maximum power of the DC-DC conversion circuit module using the super-junction VDMOS are remarkably improved, but the super-junction device is complex in structure, and the existing manufacturing method has many defects.
At present, the super-junction M0SFET adopts an alternate P-N-structure to replace a low-doped drift layer in a traditional power device as a voltage maintaining layer, and the essence of the super-junction M0SFET is to perform charge compensation on an N region by using an electric field generated by a P region (for an N-channel device) inserted in the drift region, so as to achieve the purposes of improving breakdown voltage and reducing on-resistance. Because a large number of complex injection structures are often formed on the surface of the device, the regions are often gathered together and overlapped with each other, so that the charge balance on the surface of the silicon wafer is very difficult, and the performance of the device is further influenced. Usually, the P-type epitaxy with different doping concentrations is filled in the groove, and is combined to form a P column, so that the aim of different concentrations of the P column on the upper surface of the silicon wafer and the P column in the silicon wafer is fulfilled, the influence of the surface structure of the device on the charge balance of the PN column is further reduced, but the problem of unbalanced surface charge cannot be thoroughly solved, meanwhile, the control on the epitaxy concentration and the process difficulty are great, and the manufacturing cost of the device is increased.
Disclosure of Invention
In view of the above, the present invention provides a method for manufacturing a T-pillar chip for charge management, which uses a single epitaxy with a reduced area on the surface of a silicon wafer, and ensures the charge balance on the upper surface of the epitaxy and the process difficulty is reduced, so as to solve the above-mentioned technical problems.
The invention provides a preparation method of a T-shaped column chip for charge management, which comprises the following steps:
etching to form a first groove on the first epitaxial layer of the first conductivity type;
coating a first light reflecting layer on the bottom of the first groove, coating first photoresist on the side wall of the first groove and the first epitaxial layer, and photoetching the first groove to form second grooves positioned at two sides of the first groove;
filling a second epitaxial layer of a second conductivity type into the first trench and the second trench and removing the first photoresist;
coating second photoresist on the first epitaxial layer at intervals, forming a first etching window positioned on part of the second epitaxial layer between the second photoresist, carrying out photoetching along the first etching window to remove part of the second epitaxial layer to form a third groove, filling polycrystalline silicon into the third groove to form a first polycrystalline silicon layer, and removing the second photoresist;
coating third photoresist on the first epitaxial layer at intervals, forming a second etching window positioned on the second epitaxial layer between the third photoresist, and photoetching along the second etching window to remove the second epitaxial layer to form a fourth groove;
coating a second reflecting layer on the bottom of the fourth groove, coating a fourth photoresist on the side wall of the fourth groove, photoetching the fourth groove, removing the second epitaxial layer in the second groove and part of the first polycrystalline silicon layer to form a fifth groove vertical to the fourth groove and a second polycrystalline silicon layer positioned on the fifth groove;
removing the fourth photoresist, part of the third photoresist and the second polysilicon layer to expose the first trench, and filling a third epitaxial layer of a second conductivity type into the first trench;
and removing the third epitaxial layer in the first trench, reserving the second epitaxial layer and the third epitaxial layer in the second trench, and filling a fourth epitaxial layer of the second conduction type in the first trench.
As a further improvement of the above technical solution, the first conductivity type is an N type, and the second conductivity type is a P type.
As a further improvement of the above technical solution, the width of the first etching window is the same as the width of the second etching window.
As a further improvement of the above technical solution, the first trench, the third trench, and the fourth trench are prepared by dry etching, and the second trench and the fifth trench are prepared by wet etching.
As a further improvement of the above technical solution, the second epitaxial layer and the third epitaxial layer are symmetrically disposed with respect to the fourth epitaxial layer.
As a further improvement of the above technical solution, the doping concentration of the fourth epitaxial layer is greater than the doping concentration of the first epitaxial layer.
As a further improvement of the above technical solution, the second epitaxial layer, the third epitaxial layer, the fourth epitaxial layer and the first epitaxial layer form a T-type column super junction.
The invention provides a preparation method of a T-shaped column chip for charge management, which has the following beneficial effects compared with the prior art:
form first slot through the sculpture on first epitaxial layer, to first slot bottom coating first reflector layer, first slot lateral wall coating first photoresist carries out the photoetching and forms the second slot, pack the second epitaxial layer different with first epitaxial layer conductivity type in first slot and the second slot, adopt quintic photoetching to form the fourth epitaxial layer in the slot, second epitaxial layer and third epitaxial layer set up about fourth epitaxial layer symmetry and form T type post, can adjust charge balance, only have an epitaxy in the slot, the technology degree of difficulty has been reduced, through photoetching, the combination of sculpture and many times epitaxy technique is used, reach the different target of silicon chip upper surface P post concentration and silicon chip internal P post concentration, further reduce device surface structure to the influence of PN post charge balance, the working property of device has been promoted to a certain extent.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a flowchart of a method for manufacturing a T-pillar chip for charge management according to an embodiment of the present invention;
fig. 2 to 15 illustrate a method for manufacturing a T-pillar chip for charge management according to an embodiment of the present invention;
fig. 16 is a block diagram of a charging source management system according to an embodiment of the present invention.
The main element symbols are as follows:
10-a first epitaxial layer; 11-a first trench; 12-a first light-reflective layer; 13-a first photoresist; 14-a second trench; 15-a second epitaxial layer; 16-a second photoresist; 17-a first etch window; 18-a third trench; 19-a first polysilicon layer; 20-a third photoresist; 21-a second etching window; 22-a fourth trench; 23-a second light-reflecting layer; 24-a fourth photoresist; 25-a fifth trench; 26-a second polysilicon layer; 27-a third epitaxial layer; 28-a fourth epitaxial layer; 30-a power supply circuit; 31-DC-DC conversion circuit; 32-a rapid charging protocol identification circuit; 33-a charging unit; 34-a control circuit; 35-a microprocessor; 36-a feedback circuit; 37-OLED display unit.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1, 2 to 15, the present invention provides a method for manufacturing a T-pillar chip for charge management, including the following steps:
s1: etching a first epitaxial layer 10 of a first conductivity type to form a first trench 11;
referring to fig. 2, in the present embodiment, photoresist (not shown) is coated on the first epitaxial layer 10 at intervals, photolithography is performed on the first epitaxial layer 10 which is not covered by the photoresist, a deep trench, that is, a first trench 11, is formed by dry etching, and then the photoresist is removed. The first epitaxial layer 10 is prepared by low-voltage epitaxial growth, so that different P-type epitaxy can be filled and doped in the first trench 11 in the subsequent process.
S2: coating a first light reflecting layer 12 on the bottom of the first groove 11, coating a first photoresist 13 on the side wall of the first groove 11 and the first epitaxial layer 10, and performing photoetching on the first groove 11 to form second grooves 14 positioned at two sides of the first groove 11;
referring to fig. 3 and 4, in the present embodiment, during the photoresist exposure process, incident light is partially reflected at the air/photoresist and photoresist/substrate interfaces, and for normal incident light, if the thickness of the photoresist is an integer multiple of the optical path difference between the two reflected lights, interference is formed, and thus light intensity of interference constructive and interference destructive occurs. The greater the intensity of the two beams of reflected light relative to the intensity of the incident light, the more pronounced this effect is; the smaller the difference in the intensity of the two reflected beams, the smaller the standing wave effect, which depends on factors such as the optical thickness of the photoresist and the reflectivity of the substrate. The method comprises the steps of firstly coating a first reflective layer 12 with a certain height at the bottom of a first groove 11, then coating a first photoresist 13 on the side wall of the first groove 11 and a first epitaxial layer 10, using the first photoresist 13 as a mask to expose the first groove 11 with a large dose, increasing exposure amount to be removed by development due to the fact that light is reflected by the first reflective layer 12 for multiple times, then carrying out wet etching under the protection of the first photoresist 13 to form second grooves 14 located on two sides of the first groove 11, wherein the first groove 11 and the second grooves 14 are in a T shape, namely the area of the bottom of the first groove 11 is increased, and a subsequent preparation process is facilitated.
S3: filling a second epitaxial layer 15 of a second conductivity type into the first trench 11 and the second trench 14 and removing the first photoresist 13;
referring to fig. 5, in the present embodiment, the first photoresist 13 is used as a barrier layer, the second conductive type ions are filled into the first trench 11 and the second trench 14 to form the second epitaxial layer 15, the conductivity type of the second epitaxial layer 15 is different from that of the first epitaxial layer 10 to form a PN junction, and then the first photoresist 13 is removed by using a chemical solution.
S4: coating second photoresist 16 on the first epitaxial layer 10 at intervals, forming first etching windows 17 located on a part of the second epitaxial layer 15 between the second photoresist 16, performing photoetching along the first etching windows 17 to remove a part of the second epitaxial layer 15 to form third trenches 18, filling polysilicon into the third trenches 18 to form a first polysilicon layer 19, and removing the second photoresist 16;
referring to fig. 6, 7 and 8, in the present embodiment, first, second photoresist 16 is coated on the first epitaxial layer 10 at intervals, the second photoresist 16 covers a portion of the upper surface of the second epitaxial layer 15, the first etching window 17 is located between the second photoresist 16, the second photoresist 16 is used as a mask to perform photolithography on the second epitaxial layer 15 along the first etching window 17 to remove a portion of the second epitaxial layer 15, so as to form a third trench 18, and the third trench 18 is connected to the second epitaxial layer 15 in the second trench 14. And continuously taking the second photoresist 16 as a mask, filling polycrystalline silicon into the third trench 18 to form a first polycrystalline silicon layer 19, wherein the first polycrystalline silicon layer 19 can isolate the second epitaxial layer 15 and reduce the interface stress, and then removing the second photoresist 16 by using a chemical solution.
S5: coating third photoresist 20 on the first epitaxial layer 10 at intervals, forming second etching windows 21 located on the second epitaxial layer 15 between the third photoresist 20, and performing photolithography along the second etching windows 21 to remove the second epitaxial layer 15 to form fourth trenches 22;
referring to fig. 9 and 10, in the present embodiment, third photoresist 20 is coated on the upper surface of the first epitaxial layer 10 at intervals, the third photoresist 20 covers the first polysilicon layer 19 and exposes the second epitaxial layer 15, a second etching window 21 is formed between the third photoresist 20, the third photoresist 20 is used as a mask to remove a portion of the second epitaxial layer 15 by photolithography along the second etching window 21 to form a fourth trench 22, and the fourth trench 22 is located between the second trench 14 and the third trench 18 and is connected to the second epitaxial layer 15.
S6: coating a second light reflecting layer 23 on the bottom of the fourth trench 22, coating a fourth photoresist 24 on the side wall of the fourth trench 22, and performing photolithography on the fourth trench 22, removing the second epitaxial layer 15 in the second trench 14 and a part of the first polysilicon layer 19 to form a fifth trench 25 perpendicular to the fourth trench 22 and a second polysilicon layer 26 on the fifth trench 25;
referring to fig. 11 and 12, in the present embodiment, the second light reflecting layer 23 with a certain height is coated on the bottom of the fourth trench 22, preferably, the second light reflecting layer 23 with the same depth as the second trench 14, and the fourth photoresist 24 is coated on the sidewall of the fourth trench 22, the fourth trench 22 is subjected to photolithography using the fourth photoresist 24 and the third photoresist 20 as masks, and the fourth trench 22 is exposed with a large dose, and the light is reflected by the second light reflecting layer 23 multiple times, so that the light exposure increased may be removed by development. And performing wet etching on the second epitaxial layer 15 and the fourth trench 22 in the second trench 14, removing the second epitaxial layer 15 connected with the fourth trench 22 and a part of the first polysilicon layer 19 to form a fifth trench 25, wherein the second polysilicon layer 26 is located on the fifth trench 25, and the fifth trench 25 is connected with the remaining second epitaxial layer 15.
S7: removing the fourth photoresist 24, a part of the third photoresist 20 and the second polysilicon layer 26 to expose the first trench 11, and filling a third epitaxial layer 27 of a second conductivity type into the first trench 11;
referring to fig. 13, in this embodiment, a chemical solution is used to remove a portion of the third photoresist 20 on the fourth photoresist 24 and the second polysilicon layer 26, the remaining third photoresist 20 is used as an etching barrier layer, the second polysilicon layer 26 is removed by dry etching to expose the first trench 11, the third epitaxial layer 27 of the second conductivity type ions is filled in the first trench 11 and the fifth trench 25, the second conductivity type is P type, the P type ions may be boron, the third epitaxial layer 27 is L-shaped, and then the third photoresist 20 is removed.
S8: removing the third epitaxial layer 27 in the first trench 11, leaving the second epitaxial layer 15 and the third epitaxial layer 27 in the second trench 14, and filling the first trench 11 with a fourth epitaxial layer 28 of the second conductivity type.
Referring to fig. 14 and 15, in this embodiment, an etching barrier layer such as photoresist or silicon oxide, silicon nitride, or the like is coated on the first epitaxial layer 10 at both sides of the third epitaxial layer 27, dry etching is performed on the exposed third epitaxial layer 27, the second epitaxial layer 15 and the third epitaxial layer 27 in the second trench 14 are retained, then ions with the same conductivity type as the second epitaxial layer 15 and the third epitaxial layer 27 are filled into the first trench 11 to form a fourth epitaxial layer 28, the fourth epitaxial layer 28 is located between the second epitaxial layer 15 and the third epitaxial layer 27, the second epitaxial layer 15, the fourth epitaxial layer 28 and the third epitaxial layer 27 form a T-type P column, and the T-type P column and the N-type first epitaxial layer 10 form a super junction structure.
It should be noted that the first conductive type is an N-type, the second conductive type is a P-type, the width of the first etching window 17 is the same as the width of the second etching window 21, the first trench 11, the third trench 18, and the fourth trench 22 are prepared by dry etching, and the second trench 14 and the fifth trench 25 are prepared by wet etching. The second epitaxial layer 15 and the third epitaxial layer 27 are symmetrically arranged with respect to the fourth epitaxial layer 28. The doping concentration of the fourth epitaxial layer 28 is greater than the doping concentration of the first epitaxial layer 10. The second epitaxial layer 15, the third epitaxial layer 27, the fourth epitaxial layer 28 and the first epitaxial layer 10 form a T-shaped column super junction.
It should be understood that the P-pillar formed by the T-shaped groove is the most ideal scheme for the super junction power device, the charge balance is adjusted by different epitaxy in the silicon body, and the single epitaxy with a reduced area is used on the surface of the silicon wafer, so that the charge balance of the upper surface is ensured, only one epitaxy is provided, and the difficulty in controlling the manufacturing process is greatly reduced. The preparation method related by the invention is a preparation method of the active region of the trench type power device, and the preparation methods of the other regions are not limited. According to the invention, through the combined use of photoetching, etching and multi-time epitaxy technologies and through the process and device structure design, the preparation method of the T-shaped column chip for charge management is realized, and the performance of the super junction power device after the T-shaped column is used can be improved.
Referring to fig. 16, in another possible embodiment, the charging management system mainly includes a power circuit 30, a DC-DC conversion circuit 31, a rapid charging protocol identification circuit 32, a charging unit 33, a control circuit 34, a microprocessor 35, a feedback circuit 36, and an OLED display unit 37, where the DC-DC conversion circuit 31 is connected to the power circuit 30, the control circuit 34, and the rapid charging protocol identification circuit 32, the microprocessor 35 is connected to the control circuit 34, the OLED display unit 37, and the feedback circuit 36, and the rapid charging protocol identification circuit 32 is connected to the charging unit 33 and the feedback circuit 36. The DC-DC conversion circuit 31 mainly completes the step-down conversion of the input voltage according to the control signal, the core device of the module is a VDMOS power chip, and the performance of the VDMOS directly affects the charging efficiency, the charging speed, the reliability, and the like of the fast charging system. The VDMOS with the traditional structure has large on-resistance of devices, and limits the performance improvement of a quick charging system. The super-junction VDMOS greatly reduces the on-resistance of the device, the conversion efficiency and the maximum power of the DC-DC conversion circuit module using the super-junction VDMOS are obviously improved, and the structure of the super-junction device is complex.
It should be noted that the drain-source electrodes of the trench-type vertical double-diffused field effect transistor (VDMOS) are respectively disposed on two sides of the device, so that current flows vertically in the device, the current density is increased, the rated current is improved, the on-resistance per unit area is also small, and the device is a power device with a very wide application. The conventional power M0SFET generally adopts a VDM0S structure, and in order to withstand high withstand voltage, the doping concentration of a drift region needs to be reduced or the thickness of the drift region needs to be increased, which has the direct consequence that the on-resistance is increased sharply. The on-resistance of a typical conventional power M0SFET is related to the breakdown voltage by a power of 2.5, which is referred to as the "silicon limit". The super-junction VDMOS is based on the charge compensation principle, so that the on-resistance and the breakdown voltage of the device are in a 1.32 power relation, and the contradiction between the on-resistance and the breakdown voltage is well solved. Compared with the conventional power VDM0S structure, the super-junction M0SFET adopts an alternate P-N-structure to replace a low-doped drift layer in the conventional power device to serve as a voltage maintaining layer. The super junction M0SFET is characterized in that the electric field generated by a P region (for an N-channel device) inserted into a drift region is utilized to carry out charge compensation on an N region, so that the purposes of improving breakdown voltage and reducing on-resistance are achieved.
The super-junction MOSFET is characterized in that charge compensation is carried out by utilizing an N column and a P column which are alternately arranged in a composite buffer layer, so that a P area and an N area are mutually depleted, an ideal flat-top electric field distribution and an even electric potential distribution are formed, and the purposes of improving breakdown voltage and reducing on-resistance are achieved. The prerequisite for achieving the desired effect is charge balance. The preparation method of the T-shaped column chip for charge management provided by the invention can improve the performance of the device and realize the charge balance on the surface of the device.
The invention provides a preparation method of a T-shaped column chip for charge management, which comprises the steps of forming a first groove 11 on a first epitaxial layer 10 in an etching mode, coating a first reflecting layer 12 at the bottom of the first groove 11, coating a first photoresist 13 on the side wall of the first groove 11, carrying out photoetching to form a second groove 14, filling a second epitaxial layer 15 with a conductivity type different from that of the first epitaxial layer 10 into the first groove 11 and the second groove 14, forming a fourth epitaxial layer 28, a second epitaxial layer 15 and a third epitaxial layer 27 in the grooves by adopting five times of photoetching, and symmetrically arranging the second epitaxial layer 15 and the third epitaxial layer 27 relative to the fourth epitaxial layer 28 to form a T-shaped column.
In all examples shown and described herein, any particular value should be construed as exemplary only and not as a limitation, and thus other examples of example embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
Claims (5)
1. A preparation method of a T-shaped column chip for charge management is characterized by comprising the following steps:
etching to form a first groove on the first epitaxial layer of the first conductivity type;
coating a first light reflecting layer on the bottom of the first groove, coating first photoresist on the side wall of the first groove and the first epitaxial layer, and photoetching the first groove to form second grooves positioned at two sides of the first groove;
filling a second epitaxial layer of a second conductivity type into the first trench and the second trench and removing the first photoresist;
coating second photoresist on the first epitaxial layer at intervals, forming a first etching window positioned on part of the second epitaxial layer between the second photoresist, carrying out photoetching along the first etching window to remove part of the second epitaxial layer to form a third groove, filling polycrystalline silicon into the third groove to form a first polycrystalline silicon layer, and removing the second photoresist;
coating third photoresist on the first epitaxial layer at intervals, forming a second etching window positioned on the second epitaxial layer between the third photoresist, and photoetching along the second etching window to remove the second epitaxial layer to form a fourth groove;
coating a second reflecting layer on the bottom of the fourth groove, coating a fourth photoresist on the side wall of the fourth groove, photoetching the fourth groove, and removing a second epitaxial layer in the second groove and a part of the first polycrystalline silicon layer to form a fifth groove vertical to the fourth groove and a second polycrystalline silicon layer positioned on the fifth groove;
removing the fourth photoresist, part of the third photoresist and the second polysilicon layer to expose the first trench, and filling a third epitaxial layer of a second conductivity type into the first trench;
removing the third epitaxial layer in the first trench, reserving the second epitaxial layer and the third epitaxial layer in the second trench, and filling a fourth epitaxial layer of a second conduction type into the first trench;
the doping concentration of the fourth epitaxial layer is larger than that of the first epitaxial layer, and the second epitaxial layer, the third epitaxial layer, the fourth epitaxial layer and the first epitaxial layer form a T-shaped column super junction.
2. The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
3. The method of claim 1, wherein the first etch window has a width that is the same as a width of the second etch window.
4. The method of claim 1, wherein the first trench, the third trench, and the fourth trench are formed by dry etching, and the second trench and the fifth trench are formed by wet etching.
5. The method of manufacturing a T-pillar chip for charge management of claim 1, wherein the second epitaxial layer and the third epitaxial layer are symmetrically disposed about the fourth epitaxial layer.
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