CN114141620A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114141620A
CN114141620A CN202010917285.0A CN202010917285A CN114141620A CN 114141620 A CN114141620 A CN 114141620A CN 202010917285 A CN202010917285 A CN 202010917285A CN 114141620 A CN114141620 A CN 114141620A
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CN
China
Prior art keywords
mask layer
mask
layer
forming
fin
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Pending
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CN202010917285.0A
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Chinese (zh)
Inventor
赵君红
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010917285.0A priority Critical patent/CN114141620A/en
Publication of CN114141620A publication Critical patent/CN114141620A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate comprising: the device comprises a first area and a second area, wherein the first area is provided with a first fin part, and the second area is provided with a second fin part; forming a first mask layer covering the top and the side wall of the second fin part and an opening positioned in the first mask layer on a substrate, wherein the opening exposes the top surface and the side wall surface of the first fin part; forming a second mask layer covering the side wall of the first fin part in the opening, wherein the second mask layer exposes the top surface of the first fin part, and the first mask layer and the second mask layer are made of different materials; and removing the first fin part by taking the first mask layer and the second mask layer as masks. In the process of removing the first fin portion, the second mask layer is less damaged in etching, the performance of the formed semiconductor structure is improved, and meanwhile, the process for forming the first mask layer is simple, and the process cost is favorably reduced.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.
In order to overcome the short channel Effect of the device and suppress the leakage current, the prior art proposes a Fin Field Effect Transistor (Fin FET), which is a new multi-gate device and generally includes a Fin portion protruding from the surface of a semiconductor substrate, a gate structure covering a part of the top surface and the sidewall of the Fin portion, and source-drain doped layers in the Fin portion located at both sides of the gate structure.
However, since the shape of the fin plays a crucial role in the performance of the finfet, the existing process of removing the fin in the inactive region is likely to damage the fin in the active region.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to improve the performance of the formed semiconductor structure and reduce the process cost.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising: the device comprises a first area and a second area, wherein the first area is provided with a first fin part, and the second area is provided with a second fin part; forming a first mask layer covering the top and the side wall of the second fin part and an opening positioned in the first mask layer on the substrate, wherein the opening exposes the top surface and the side wall surface of the first fin part; forming a second mask layer covering the side wall of the first fin part in the opening, wherein the second mask layer exposes the top surface of the first fin part, and the first mask layer and the second mask layer are made of different materials; and removing the first fin part by taking the first mask layer and the second mask layer as masks.
Optionally, the opening exposes a portion of a sidewall surface of the first fin.
Optionally, the etching selection ratio of the process for removing the first fin portion to the first fin portion and the second mask layer ranges from 4:1 to 1.5: 1.
Optionally, the etching selection ratio of the process for removing the first fin portion to the first fin portion and the first mask layer ranges from 3:1 to 1: 1.
Optionally, the process of removing the first fin portion is a dry etching process.
Optionally, the method for forming the first mask layer and the opening in the first mask layer includes: forming a first mask material layer on the substrate, wherein the first mask material layer covers the first fin portion and the second fin portion; forming a patterning layer on the surface of the first mask material layer, wherein the patterning layer exposes the surface of the first mask material layer on the first region; and etching the first mask material layer by taking the patterning layer as a mask until the top and part of the side wall of the first fin part are exposed to form a first mask layer and an opening in the first mask layer.
Optionally, the material of the first mask material layer includes: a carbon-oxygen containing organic material.
Optionally, the forming process of the first mask material layer includes: and (4) spin coating.
Optionally, the top surfaces of the first fin portion and the second fin portion further have a hard mask structure; the method for forming the semiconductor structure further comprises the following steps: and removing the hard mask structure on the top surface of the first fin part in the process of etching the first mask material layer by taking the patterning layer as a mask.
Optionally, the hard mask structure includes: the mask comprises a first hard mask layer and a second hard mask layer positioned on the surface of the first hard mask layer; the first hard mask layer is made of materials including: silicon oxide; the second hard mask layer is made of materials including: silicon nitride.
Optionally, the forming method of the second mask layer includes: forming a second mask material layer in the opening and on the surface of the first mask layer; and etching the second mask material layer until the top surface of the first fin part is exposed to form the second mask layer.
Optionally, the process of etching the second mask material layer is a dry etching process.
Optionally, the material of the second mask layer includes an oxide; the oxide includes silicon oxide.
Optionally, the forming process of the second mask layer is a low-temperature oxidation process.
Optionally, the method for forming the first fin portion and the second fin portion includes a multiple patterning process.
Optionally, the method further includes: and removing the first mask layer and the second mask layer after removing the first fin part.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the second mask layer covering the side wall of the first fin part is formed in the opening in the first mask layer, the second mask layer exposes the top surface of the first fin part, and the first mask layer and the second mask layer are made of different materials. On the other hand, the process for forming the first mask layer is simple, and the process cost is favorably reduced.
Furthermore, the etching selection ratio of the process for removing the first fin part to the first fin part and the second mask layer is large enough, so that the etching on the second mask layer is favorably reduced in the process of removing the first fin part, the possibility of etching damage on the second fin part in the second area is greatly reduced, the requirement of undersize the opening in the first mask layer is reduced, and the process window is favorably improved.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a conventional semiconductor structure;
fig. 4 to 10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
It should be noted that "surface" and "upper" in the present specification are used to describe a relative positional relationship in space, and are not limited to direct contact or not.
First, the reason for the poor performance of the conventional semiconductor structure will be described in detail with reference to the accompanying drawings, and fig. 1 to 3 are schematic structural diagrams of steps of a method for forming the conventional semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes: the first region I has a first fin 110 thereon, and the second region II has a second fin 120 thereon.
Referring to fig. 2, a mask layer 130 covering the top and sidewalls of the second fins 120 and an opening 140 in the mask layer 130 are formed in the substrate 100, and the opening 140 exposes the top surface and sidewall surface of the first fin 110.
Referring to fig. 3, the first fin portion 110 is removed by using the mask layer 130 as a mask.
In the method, the material 130 of the mask layer is selected from organic matters containing carbon and oxygen, the material has good fluidity, and the mask layer 130 with a flat surface can be formed, so that a patterned layer can be directly formed on the surface of the mask layer 130, the patterned layer is used as a mask, the mask layer 130 is etched, and the opening 140 is formed in the mask layer 130.
However, since the mask layer 130 formed by the organic matter containing carbon and oxygen is soft, the mask layer 130 is easy to etch the mask layer 130 in the process of removing the first fin portion 110 by using the mask layer 130 as a mask, and further, the second fin portion 120 adjacent to the first fin portion 110 is damaged by etching, so that the performance of the formed semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, in which a first mask layer covering a top and a sidewall of a second fin portion and an opening located in the first mask layer are formed on a substrate, and the opening exposes a top surface and a sidewall surface of the first fin portion; and forming a second mask layer covering the side wall of the first fin part in the opening, wherein the second mask layer is exposed out of the top surface of the first fin part, and the first mask layer and the second mask layer are made of different materials.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 4, a substrate 200 is provided, the substrate 200 includes: the first region I has a first fin portion 210 thereon, and the second region II has a second fin portion 220 thereon.
The first region I serves as an inactive region, the first fin portion 210 on the first region I is removed in a subsequent process, and the second region II serves as an active region, so that a functional device, such as a transistor or a diode, is formed in a subsequent process.
The method for forming the first fin portion 210 and the second fin portion 220 includes a multiple patterning process.
In the present embodiment, the forming method of the first fin portion 210 and the second fin portion 220 is a Self-Aligned quad patterning process (SAQP).
Specifically, the method for forming the first fin portion 210 and the second fin portion 220 includes: forming a fin material film, a core material film on the surface of the fin material film and a mask layer of a patterned layer on the surface of the core material film on the first region I and the second region II of the substrate 200; etching the core material layer by taking the patterned mask layer as a mask to form a patterned core layer; forming a first side wall material film on the surface of the fin material film and the surface of the core layer; etching the first side wall material film back until the top surfaces of the core layer and the fin material film are exposed, and forming a first side wall on the side wall of the core layer; removing the core layer; after the core layer is removed, forming a second side wall material film on the surface of the fin material film and the surface of the first side wall; etching the second side wall material film back until the fin material film and the top surface of the first side wall are exposed, and forming a second side wall on the side wall of the first side wall; removing the first side wall; after removing the first sidewall, the fin material film is etched using the second sidewall as a mask, a first fin 210 is formed on the first region I, and a second fin 220 is formed on the second region II.
In the present embodiment, the substrate 200, the first fin portion 210 and the second fin portion 220 are made of the same material and are made of single crystal silicon.
In other embodiments, the substrate and the first fin portion are made of different materials, and the substrate and the second fin portion are made of different materials. Specifically, the substrate, the first fin portion and the second fin portion may be made of semiconductor materials such as single crystal germanium, silicon germanium and gallium arsenide. In other embodiments, the substrate and the first and second fins can also be semiconductor-on-insulator structures.
In the present embodiment, the top surfaces of the first fin portion 210 and the second fin portion 220 further have a hard mask structure (not shown).
The hard mask structure includes: a first hard mask layer 231 and a second hard mask layer 232 on the surface of the first hard mask layer 231.
The material of the first hard mask layer 231 includes: silicon oxide; the material of the second hard mask layer 232 includes: silicon nitride.
The first hard mask layer 231 is used for increasing the interface adhesion between the second hard mask layer 232 and the first fin 210, and between the second hard mask layer 232 and the second fin 220, and the second hard mask layer 232 is used as an etching stop layer of a subsequent process.
Next, a first mask layer covering the top and sidewalls of the second fin portion 220 and an opening in the first mask layer are formed on the substrate 200, and the opening exposes the top surface and sidewall surface of the first fin portion 210.
In the present embodiment, the opening exposes a portion of the sidewall surface of the first fin 210, and please refer to fig. 5 to 6 for a process of forming the first mask layer and the opening in the first mask layer.
Referring to fig. 5, a first mask material layer 240 is formed on the substrate 200, wherein the first mask material layer 240 covers the first fin portion 210 and the second fin portion 220; a patterned layer is formed on the surface of the first masking material layer 240, and the patterned layer exposes the surface of the first masking material layer 240 on the first region I.
The material of the first mask material layer 240 includes: a carbon-oxygen containing organic material.
The carbon-oxygen-containing organic material has good fluidity and good filling property, and is beneficial to forming the first mask material layer 240 with a flat surface, so that a patterning layer can be directly formed on the surface of the first mask material layer 240 in the follow-up process, the first mask material layer is patterned to form a first mask layer and an opening in the first mask layer, the process steps for forming the first mask layer are reduced, and the process cost is reduced.
The forming process of the first mask material layer 240 includes: and (4) spin coating.
Through a spin coating process, a first mask material layer 240 covering the first fin portion 210 and the second fin portion 220 is formed on the substrate 200, and the surface of the first mask material layer 240 is relatively flat, so that an additional planarization process or an etching process is not required, and process steps and process time are saved.
In this embodiment, the patterning layer includes: a first patterning part 2411 and a second patterning part 2412 located on the surface of the first patterning part 2411.
The material of the first patterning part 2411 includes: an antireflective material.
The first patterning portion 2411 is beneficial to improving the accuracy of the subsequent formation of the second patterning portion 2412 with a pattern.
The second patterned portion 2412 is made of photoresist, and a second patterned portion 2412 having a pattern, which determines the position and size of a subsequent opening, is formed through a photolithography process.
Referring to fig. 6, the first mask material layer 240 is etched using the patterned layer as a mask until the top and a portion of the sidewalls of the first fin 210 are exposed, thereby forming a first mask layer 250 and an opening 251 in the first mask layer 250.
The opening 251 provides a space for a second mask layer to be formed later.
In the present embodiment, the opening 251 exposes a portion of the sidewall surface of the first fin 210.
Since the first mask material layer 240 is etched to form the first mask layer 250, and the opening 251 in the first mask layer 250 exposes a portion of the sidewall surface of the first fin portion 210, the first mask material layer 240 with the whole thickness does not need to be etched in forming the opening 251, that is, the etching process time is reduced, so that excessive etching damage cannot be caused to the first mask material layer 240 on the sidewall of the opening 251 in the transverse direction, and the second fin portion 220 is prevented from being damaged by etching.
In this embodiment, since the top surfaces of the first fin portion 210 and the second fin portion 220 further have a hard mask structure, the hard mask structure on the top surface of the first fin portion 210 is removed in the process of etching the first mask material layer 240 by using the patterning layer as a mask.
In this embodiment, after forming the first mask layer 250 and the opening 251 in the first mask layer, the method further includes: and removing the patterning layer.
After the first mask layer 250 and the opening 251 in the first mask layer 250 are formed, a second mask layer covering the sidewall of the first fin portion 210 is formed in the opening 251, the second mask layer exposes the top surface of the first fin portion 210, the first mask layer 250 and the second mask layer are made of different materials, and please refer to fig. 7 to 8 in detail.
Referring to fig. 7, a second masking material layer 260 is formed in the opening 251 and on the surface of the first masking layer 250.
The material of the second masking material layer 260 includes an oxide.
In this embodiment, the material of the second mask material layer 260 is silicon oxide.
The forming process of the second mask material layer 260 is a low temperature oxidation process.
Because the first mask layer 250 is made of an organic material containing carbon and oxygen, the first mask layer 250 has good high temperature resistance, and the second mask material layer 260 is formed through a low-temperature oxidation process, so that the appearance and performance of the first mask layer 250 can be well maintained, and the accuracy of a subsequent process is improved.
Referring to fig. 8, the second mask material layer 260 is etched until the top surface of the first fin 210 is exposed, so as to form the second mask layer 270.
The process of etching the second mask material layer 260 is a dry etching process.
Since the second mask layer 270 is formed by etching the second mask material layer 260, correspondingly, the material of the second mask layer 270 includes: an oxide. In this embodiment, the material of the second mask layer 270 is silicon oxide.
On one hand, in the subsequent process of removing the first fin portion 210, the second mask layer 270 is less damaged by etching, and further the first mask layer 250 on the side wall of the second mask layer 270 and the second fin portion 220 covered by the first mask layer 250 are less damaged by etching, so that the first fin portion 210 in the first area I is removed, the second fin portion 220 in the second area II is not damaged by etching, and the performance of the semiconductor structure in the second area II is ensured to be better. On the other hand, the process for forming the first mask layer 250 is simple, which is beneficial to reducing the process cost.
Referring to fig. 9, the first fin portion 210 is removed by using the first mask layer 250 and the second mask layer 270 as masks.
The etching selectivity of the process for removing the first fin portion 210 to the first fin portion 210 and the second mask layer 270 ranges from 4:1 to 1.5: 1.
The etching rate of the process for removing the first fin portion 210 on the second mask layer 270 is far less than that of the process for removing the first fin portion 210 on the first fin portion 210, so that in the process of removing the first fin portion 210, etching damage to the material of the second mask layer 270 on the side wall of the first fin portion 210 is reduced, especially, lateral etching in the second mask layer 270 is reduced, and further, the reduction of etching damage to the second fin portion 220 in the second region II is facilitated.
The etching selection ratio of the process for removing the first fin portion 210 to the first fin portion 210 and the first mask layer 250 ranges from 3:1 to 1: 1.
The process of removing the first fin portion 210 is a dry etching process.
Due to the fact that the etching selection ratio of the process for removing the first fin portion 210 to the first fin portion 210 and the first mask layer 250 is large enough, in the process of removing the first fin portion 210, etching on the first mask layer 250 is favorably reduced, the possibility of etching damage on the second fin portion 220 of the second area II is greatly reduced, the requirement that the size of the opening 251 in the first mask layer 250 is too small is also reduced, and the process window is favorably improved.
Referring to fig. 10, after the first fin 210 is removed, the first mask layer 250 and the second mask layer 270 are removed.
The process of removing the first mask layer 250 and the second mask layer 270 includes: one or two of the dry etching process and the wet etching process are combined.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising: the device comprises a first area and a second area, wherein the first area is provided with a first fin part, and the second area is provided with a second fin part;
forming a first mask layer covering the top and the side wall of the second fin part and an opening positioned in the first mask layer on the substrate, wherein the opening exposes the top surface and the side wall surface of the first fin part;
forming a second mask layer covering the side wall of the first fin part in the opening, wherein the second mask layer exposes the top surface of the first fin part, and the first mask layer and the second mask layer are made of different materials;
and removing the first fin part by taking the first mask layer and the second mask layer as masks.
2. The method of forming a semiconductor structure of claim 1, wherein the opening exposes a portion of a sidewall surface of the first fin.
3. The method of claim 1, wherein an etch selectivity ratio of the first fin portion removal process to the first fin portion and the second mask layer is in a range from 4:1 to 1.5: 1.
4. The method of claim 3, wherein an etch selectivity ratio of the first fin portion removal process to the first fin portion and the first mask layer is in a range from 3:1 to 1: 1.
5. The method of claim 4, wherein the removing the first fin portion is a dry etching process.
6. The method of claim 1, wherein the first mask layer and the opening in the first mask layer are formed by a method comprising: forming a first mask material layer on the substrate, wherein the first mask material layer covers the first fin portion and the second fin portion; forming a patterning layer on the surface of the first mask material layer, wherein the patterning layer exposes the surface of the first mask material layer on the first region; and etching the first mask material layer by taking the patterning layer as a mask until the top and part of the side wall of the first fin part are exposed to form a first mask layer and an opening in the first mask layer.
7. The method of forming a semiconductor structure of claim 6, wherein the material of the first masking material layer comprises: a carbon-oxygen containing organic material.
8. The method of claim 7, wherein the forming of the first masking material layer comprises: and (4) spin coating.
9. The method of forming a semiconductor structure of claim 6, wherein the top surfaces of the first and second fins further have a hard mask structure; the method for forming the semiconductor structure further comprises the following steps: and removing the hard mask structure on the top surface of the first fin part in the process of etching the first mask material layer by taking the patterning layer as a mask.
10. The method of forming a semiconductor structure of claim 9, wherein the hardmask structure comprises: the mask comprises a first hard mask layer and a second hard mask layer positioned on the surface of the first hard mask layer; the first hard mask layer is made of materials including: silicon oxide; the second hard mask layer is made of materials including: silicon nitride.
11. The method of forming a semiconductor structure of claim 1, wherein the method of forming the second mask layer comprises: forming a second mask material layer in the opening and on the surface of the first mask layer; and etching the second mask material layer until the top surface of the first fin part is exposed to form the second mask layer.
12. The method of forming a semiconductor structure of claim 11, wherein the process of etching the second masking material layer is a dry etching process.
13. The method of forming a semiconductor structure of claim 1, wherein a material of the second mask layer comprises an oxide; the oxide includes silicon oxide.
14. The method of claim 13, wherein the second mask layer is formed by a low temperature oxidation process.
15. The method of forming a semiconductor structure of claim 1, wherein the first fin and the second fin are formed by a multi-patterning process.
16. The method of forming a semiconductor structure of claim 1, further comprising: and removing the first mask layer and the second mask layer after removing the first fin part.
CN202010917285.0A 2020-09-03 2020-09-03 Method for forming semiconductor structure Pending CN114141620A (en)

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CN202010917285.0A CN114141620A (en) 2020-09-03 2020-09-03 Method for forming semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010917285.0A CN114141620A (en) 2020-09-03 2020-09-03 Method for forming semiconductor structure

Publications (1)

Publication Number Publication Date
CN114141620A true CN114141620A (en) 2022-03-04

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Family Applications (1)

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CN202010917285.0A Pending CN114141620A (en) 2020-09-03 2020-09-03 Method for forming semiconductor structure

Country Status (1)

Country Link
CN (1) CN114141620A (en)

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