CN114141281A - Pre-charging circuit of sensitive amplifier circuit - Google Patents

Pre-charging circuit of sensitive amplifier circuit Download PDF

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Publication number
CN114141281A
CN114141281A CN202111344927.3A CN202111344927A CN114141281A CN 114141281 A CN114141281 A CN 114141281A CN 202111344927 A CN202111344927 A CN 202111344927A CN 114141281 A CN114141281 A CN 114141281A
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CN
China
Prior art keywords
mos tube
circuit
charge signal
tube
mos
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Pending
Application number
CN202111344927.3A
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Chinese (zh)
Inventor
杨光军
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202111344927.3A priority Critical patent/CN114141281A/en
Publication of CN114141281A publication Critical patent/CN114141281A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof

Abstract

The invention discloses a pre-charging circuit of a sensitive amplifier circuit, wherein a second end of a first MOS tube is connected with a power supply voltage, a first end of the first MOS tube is connected with a second end of a second MOS tube, and a first end of the second MOS tube is connected with a storage unit; the first end of the second MOS tube feeds the potential of the first end of the second MOS tube back to the third end of the second MOS tube through a feedback circuit; the second end of the eighth MOS tube is connected to the first end of the second MOS tube, the first end of the eighth MOS tube is grounded, and the third end of the eighth MOS tube is connected with a second pre-charge signal; the first end of the seventh MOS tube is connected with a power supply voltage, the third end of the seventh MOS tube is connected with a second pre-charge signal, and the second end of the seventh MOS tube is connected with the third end of the second MOS tube; and the third end of the first MOS tube is connected with a first pre-charge signal. The pre-charging circuit adopts dual-phase charging, so that the feedback nodes can be pre-charged simultaneously in the pre-charging stage, the charging speed is improved, and the 0 induction speed is improved.

Description

Pre-charging circuit of sensitive amplifier circuit
Technical Field
The present invention relates to the field of semiconductor integrated circuit design and manufacture, and more particularly to a precharge circuit for a sense amplifier circuit.
Background
Flash memory is a mechanism that stores no data information by storing charge on a floating gate. The SA reads memory cell information by sensing the current of the memory cell under well-defined conditions. In a read reference condition, a programmed memory cell draws less current because it has a high threshold voltage; the erased memory cell draws a larger current because it has a low threshold voltage. The SA generally detects memory cell information by comparing the memory cell current with a reference current. The reference current can be obtained by mirroring the reference unit current through a current mirror, and can also be generated by other reference current source circuits. SA can be divided into a single-ended structure and a differential structure according to whether a reference cell is used for comparison in the read circuit. A sense amplifier is an important component of a memory, and senses a small signal on a Bit Line (BL) and reads data stored in a memory cell by amplifying the small signal. In order to read the data stored in the memory cell, the bit line of the memory cell needs to be precharged.
The conventional sense amplifier includes a precharge circuit, in which a MOS transistor is used as a switching transistor, as shown in fig. 1, the MOS transistor M1 is connected to a power supply, a gate is connected to a precharge control signal pre, and the other end is connected to a bit line of a memory cell. When the precharge control signal controls the MOS transistor to be turned on, the MOS transistor outputs a current to the bit line through the M2 transistor, so that the bit line BL voltage of the memory cell is increased. The potential of the point C is the potential of the feedback node, and the potential of the node D is fed back to the point C through the inverter formed by M3 and M4, and as can be seen from the structure of the circuit, the potential of the feedback node C limits the pre-charging speed, so that the rising rate of the bit line BL is too slow, which affects the sensing speed of 0.
Disclosure of Invention
The invention aims to provide a sensitive amplifier circuit which adopts two-phase charging and has high charging speed.
In order to solve the above problem, the present invention provides a pre-charge circuit of a sense amplifier circuit, comprising;
the second end of the first MOS tube is connected with a power supply voltage, the first end of the first MOS tube is connected with the second end of the second MOS tube, and the first end of the second MOS tube is connected with the storage unit.
The first end of the second MOS tube feeds the potential of the first end of the second MOS tube back to the third end of the second MOS tube through a feedback circuit.
The second end of the eighth MOS tube is connected to the first end of the second MOS tube, the first end of the eighth MOS tube is grounded, and the third end of the eighth MOS tube is connected with a second pre-charge signal.
The first end of the seventh MOS tube is connected with power supply voltage, the third end of the seventh MOS tube is connected with a second pre-charging signal, and the second end of the seventh MOS tube is connected with the third end of the second MOS tube.
And the third end of the first MOS tube is connected with a first pre-charge signal.
The further improvement is that the feedback circuit is an inverter, the input end of the inverter is connected with the first end of the second MOS tube, and the output tube of the CMOS inverter is connected with the third end of the second MOS tube.
In a further improvement, the inverter is a CMOS inverter, and the inverter and the second MOS transistor form a clamp circuit.
The storage unit comprises a fifth MOS tube, a sixth MOS tube and a storage tube, wherein the third ends of the fifth MOS tube and the sixth MOS tube are connected with external control signals to perform data reading and writing operations.
In a further improvement, the storage device further comprises an output circuit, a first input end of the output circuit is connected with a first end of the first MOS tube and a second end of the second MOS tube, a second input end of the output circuit is connected with a reference voltage, and an output end of the output circuit outputs a storage signal of the storage unit.
In a further improvement, the output circuit is a comparator.
In a further improvement, the first pre-charge signal and the second pre-charge signal are active at a high level, the second pre-charge signal is first converted to the high level before the first pre-charge signal is converted to the high level, when the second pre-charge signal returns to the low level, the first pre-charge signal is converted to the high level, and a period of the first pre-charge signal being the high level is longer than a period of the second pre-charge signal being the high level.
The pre-charging circuit of the sensitive amplifier circuit adopts dual-phase charging, so that the feedback node can be pre-charged at the same time in the pre-charging stage, the charging speed is improved, and the 0 induction speed is improved.
Drawings
Fig. 1 is a schematic diagram of a precharge circuit of a conventional sense amplifier circuit.
Fig. 2 is a schematic diagram of a precharge circuit of a sense amplifier circuit according to the present invention.
Fig. 3 is a waveform diagram of first Pre-charge signal Pre and second Pre-charge signal Pre2 according to the present invention.
Detailed Description
The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
As shown in FIG. 2, M1-M8 in the figure correspond to the first to eighth MOS transistors, respectively. In this embodiment, the third MOS transistor and the seventh MOS transistor are PMOS transistors, and the other MOS transistors are NMOS transistors, and the connection relationship is that the drain terminal of the first MOS transistor is connected to the power voltage VDD, the source terminal of the first MOS transistor is connected to the drain terminal of the second MOS transistor, and the source terminal of the second MOS transistor is connected to the memory cell; the storage unit comprises a fifth MOS tube, a sixth MOS tube and a storage tube at the lowest part, and the grid ends of the fifth MOS tube and the sixth MOS tube are connected with external control signals to carry out data reading and writing operations. The gate terminal of the storage tube is connected with a word line signal VWL, and CBL is a bit line equivalent capacitor.
The source end of the second MOS tube feeds the potential of the source end of the second MOS tube back to the grid end of the second MOS tube through a feedback circuit. The feedback circuit is a CMOS phase inverter consisting of a third MOS tube and a fourth MOS tube, the input end of the inverter is connected with the source electrode of the second MOS tube, and the source electrode potential D of the second MOS tube is fed back to the point C to form a clamping circuit.
The drain terminal of the eighth MOS transistor is connected to the source terminal of the second MOS transistor, the source terminal of the eighth MOS transistor is grounded, and the gate terminal of the eighth MOS transistor is connected to the second Pre-charge signal Pre 2.
The source end of the seventh MOS tube is connected with a power supply voltage VDD, the gate end of the seventh MOS tube is connected with a second pre-charge signal, the drain end of the seventh MOS tube is connected with the gate end of the second MOS tube, and the drain end of the second MOS tube is also connected with the power supply VDD to supply current for the storage unit.
And the grid end of the first MOS tube is connected with a first Pre-charge signal Pre.
The figure is also provided with an output circuit connected with the first MOS tube and the second MOS tube, and the output circuit is a comparator. The first input end + is connected with the source end of the first MOS tube and the drain end of the second MOS tube, the second input end-of the output circuit is connected with the reference voltage Vref, and the output end outputs the storage signal DOUT of the storage unit.
The first Pre-charge signal Pre and the second Pre-charge signal Pre2 are inverted with respect to each other. That is, when the first Pre-charge signal Pre is at a low level, the second Pre-charge signal Pre2 is at a high level. The waveform diagram is shown in fig. 3.
The circuit adopts dual-phase Pre-charging, when a first MOS tube of a Pre-charging tube is charged on a bit line through M2, a second Pre-charging signal Pre2 firstly provides a high level, at the moment, an eighth MOS tube is conducted, the potential of a point D is pulled to a low level, the potential of a point C is at the high level at the moment, the second MOS tube is conducted in advance, when the second Pre-charging signal Pre2 returns to the low level, the first Pre-charging signal Pre is switched to the high level at the moment, the first MOS tube is conducted, at the moment, a seventh MOS tube is in a conducting state, the potential of the point C is still at the high level, the second MOS tube is kept in the conducting state, and at the moment, the first MOS tube charges the bit line through the second MOS tube. Since the feedback node C is also precharged in the precharge stage before the first precharge signal Pre arrives, the second MOS transistor is turned on in advance, which will increase the 0 sensing speed, so the present invention increases the corresponding speed through two-phase precharge.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (7)

1. A precharge circuit for a sense amplifier circuit, characterized by: the pre-charging circuit comprises;
the second end of the first MOS tube is connected with a power supply voltage, the first end of the first MOS tube is connected with the second end of the second MOS tube, and the first end of the second MOS tube is connected with the storage unit;
the first end of the second MOS tube feeds the potential of the first end of the second MOS tube back to the third end of the second MOS tube through a feedback circuit;
the second end of the eighth MOS tube is connected to the first end of the second MOS tube, the first end of the eighth MOS tube is grounded, and the third end of the eighth MOS tube is connected with a second pre-charge signal;
the first end of the seventh MOS tube is connected with a power supply voltage, the third end of the seventh MOS tube is connected with a second pre-charge signal, and the second end of the seventh MOS tube is connected with the third end of the second MOS tube;
and the third end of the first MOS tube is connected with a first pre-charge signal.
2. A precharge circuit for a sense amplifier circuit as claimed in claim 1, wherein: the feedback circuit is a phase inverter, the input end of the phase inverter is connected with the first end of the second MOS tube, and the output tube of the CMOS phase inverter is connected with the third end of the second MOS tube.
3. A precharge circuit for a sense amplifier circuit as claimed in claim 2, wherein: the phase inverter is a CMOS phase inverter, and the phase inverter and the second MOS tube form a clamping circuit.
4. A precharge circuit for a sense amplifier circuit as claimed in claim 1, wherein: the storage unit comprises a fifth MOS tube, a sixth MOS tube and a storage tube, and the third ends of the fifth MOS tube and the sixth MOS tube are connected with external control signals to carry out data reading and writing operations.
5. A precharge circuit for a sense amplifier circuit as claimed in claim 1, wherein: the first input end of the output circuit is connected with the first end of the first MOS tube and the second end of the second MOS tube, the second input end of the output circuit is connected with the reference voltage, and the output end of the output circuit outputs a storage signal of the storage unit.
6. The precharge circuit of the sense amplifier circuit of claim 5, wherein: the output circuit is a comparator.
7. A precharge circuit for a sense amplifier circuit as claimed in claim 1, wherein: the first pre-charge signal and the second pre-charge signal are effective in high level, the second pre-charge signal is firstly converted into high level before the first pre-charge signal is converted into high level, when the second pre-charge signal returns to low level, the first pre-charge signal is converted into high level, and the period of the first pre-charge signal being high level is longer than the period of the second pre-charge signal being high level.
CN202111344927.3A 2021-11-15 2021-11-15 Pre-charging circuit of sensitive amplifier circuit Pending CN114141281A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111344927.3A CN114141281A (en) 2021-11-15 2021-11-15 Pre-charging circuit of sensitive amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111344927.3A CN114141281A (en) 2021-11-15 2021-11-15 Pre-charging circuit of sensitive amplifier circuit

Publications (1)

Publication Number Publication Date
CN114141281A true CN114141281A (en) 2022-03-04

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111344927.3A Pending CN114141281A (en) 2021-11-15 2021-11-15 Pre-charging circuit of sensitive amplifier circuit

Country Status (1)

Country Link
CN (1) CN114141281A (en)

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