CN114138301A - Device and server for online updating of BIOS chip - Google Patents
Device and server for online updating of BIOS chip Download PDFInfo
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Abstract
The scheme forms a binary tree structure through all transfer switches from a 0 th-level transfer circuit, a first-level transfer circuit to an Nth-level transfer circuit, when a BMC receives an update instruction, the BIOS chip to be updated is determined according to the update instruction, and the corresponding transfer switches are controlled to be switched between the input end and the output end of the BMC so that the BMC is connected with the BIOS chip to be updated through the transfer switches at all levels to update the BIOS chip to be updated on line. The application realizes the online updating of a plurality of BIOS chips by setting the change-over switch in the multistage switching circuit, and the practicability is higher.
Description
Technical Field
The invention relates to the technical field of online updating, in particular to a device for online updating of a BIOS chip and a server.
Background
In the prior art, a BMC (Baseboard Management Controller) is connected to a Processing module, such as a PCH (Platform Controller Hub) or a CPU (Central Processing Unit), by switching a switch to connect to a BIOS (Basic Input Output System) chip. When the BIOS chip works normally, the processing module is connected with the BIOS chip through the selector switch; when the BIOS chip is updated, the BMC is connected with the BIOS chip through the change-over switch, so that the BIOS chip is updated by the BMC; however, a plurality of BIOS chips exist in some servers, the BMC adopting the mode can only complete the updating of one BIOS chip through the change-over switch, and cannot support the online updating of a plurality of BIOS chips, so that the practicability is low.
Disclosure of Invention
The invention aims to provide a device and a server for online updating of BIOS chips.
In order to solve the above technical problem, the present invention provides an online update apparatus for a BIOS chip, comprising:
BMC, 0 th stage switching circuit, the first stage switching circuit to the Nth stage switching circuit, the Nth stage switching circuit including 2nEach of the transfer switches from the 0 th-stage transfer circuit to the first-stage transfer circuit to the (N-1) th-stage transfer circuit is a single-input and two-output switch, each of the transfer switches in the Nth-stage transfer circuit is a two-input and single-output switch, N is a positive integer, and N is a non-negative integer less than or equal to N;
each change-over switch in the 0 th-level change-over circuit, the first-level change-over circuit and the Nth-level change-over circuit forms a binary tree structure, an update pin of the BMC is connected with an input end of the change-over switch of the 0 th-level change-over circuit, the other input end of each change-over switch in the Nth-level change-over circuit is connected with a corresponding processing module, and output ends of each change-over switch in the Nth-level change-over circuit are respectively connected with a corresponding BIOS chip; the control pin of the BMC is also connected with the control ends of all the change-over switches;
the BMC is used for determining the BIOS chip to be updated according to the update instruction when receiving the update instruction, and controlling the corresponding change-over switch to switch between the input end and the output end of the change-over switch so that the BMC is connected with the BIOS chip to be updated through each level of change-over switch to update the BIOS chip to be updated on line.
Preferably, the nth stage switching circuit further includes 2nAnd one end of the resistor is connected with the control end of the change-over switch, the connected public end is connected with the BMC, and the other end of the resistor is grounded.
Preferably, the BMC is further configured to control the corresponding switch to switch between the input end and the output end thereof when receiving a normal operating instruction, so that all the BIOS chips are connected to the corresponding processing modules.
Preferably, the processing module includes a CPU and a level shift module, and the level shift module is connected between the CPU and the switch and is configured to perform level shift on data transmitted between the CPU and the switch.
Preferably, when the update instruction is an instruction for updating a single BIOS chip:
the BMC is specifically configured to determine a single BIOS chip to be updated according to an update instruction when the update instruction is received, and control a corresponding switch to switch between an input end and an output end of the corresponding switch, so that the BMC is connected with the single BIOS chip to be updated through the switches at each stage, and online update is performed on the single BIOS chip to be updated.
Preferably, when the update instruction is an instruction to update a plurality of BIOS chips:
the BMC is specifically configured to, when receiving an update instruction, determine a plurality of BIOS chips to be updated according to the update instruction and determine an update sequence of the plurality of BIOS chips to be updated, and control corresponding switches to switch between an input end and an output end of the corresponding switches according to the update sequence so that the BMC is sequentially connected with the BIOS chips to be updated through the switches at each stage to perform online update on the BIOS chips to be updated.
Preferably, determining an update sequence of the plurality of BIOS chips to be updated includes:
and determining the updating sequence of the plurality of BIOS chips to be updated based on the serial numbers of the plurality of BIOS chips to be updated.
In order to solve the above technical problem, the present invention further provides a server, which comprises the above BIOS chip online updating apparatus, and further comprises 2NA BIOS chip and 2NA processing module, the device for on-line updating of the BIOS chip is respectively connected with 2NThe BIOS chip and 2NThe processing modules are connected.
The scheme is that a binary tree structure is formed by all transfer switches from a 0 th-level switching circuit, a first-level switching circuit to an Nth-level switching circuit, when a BMC receives an updating instruction, the BIOS chip to be updated is determined according to the updating instruction, and the corresponding transfer switches are controlled to be switched between the input end and the output end of the BMC so that the BMC is connected with the BIOS chip to be updated through the transfer switches at all levels to update the BIOS chip to be updated on line. The application realizes the online updating of a plurality of BIOS chips by setting the change-over switch in the multistage switching circuit, and the practicability is higher.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an online BIOS chip updating apparatus according to the present invention;
FIG. 2 is a schematic structural diagram of a device for online updating a BIOS chip according to the prior art;
FIG. 3 is a schematic structural diagram of another device for online updating of a BIOS chip according to the present invention.
Detailed Description
The core of the invention is to provide a device and a server for online updating of BIOS chips, and the scheme realizes online updating of a plurality of BIOS chips by setting a selector switch in a multistage switching circuit, and has higher practicability.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of an online update apparatus for a BIOS chip according to the present invention, the apparatus including:
BMC1, level 0 switching circuit 21, first level switching circuit 22 through Nth level switching circuit, the Nth level switching circuit includes 2nEach change-over switch 3 from the 0 th-stage change-over circuit 21 to the first-stage change-over circuit 22 to the N-1 th-stage change-over circuit is a single-input and two-output switch, each change-over switch 3 in the N-stage change-over circuit is a two-input and single-output switch, N is a positive integer, and N is a non-negative integer less than or equal to N;
the 0 th-level switching circuit 21, the first-level switching circuit 22 and all the switches 3 in the nth-level switching circuit form a binary tree structure, an update pin of the BMC1 is connected with an input end of the switch 3 of the 0 th-level switching circuit 21, another input end of each switch 3 in the nth-level switching circuit is connected with a corresponding processing module 4, and output ends of all the switches 3 in the nth-level switching circuit are respectively connected with corresponding BIOS chips; the control pin of the BMC1 is also connected with the control ends of all the change-over switches 3;
the BMC1 is configured to determine, when receiving an update instruction, a BIOS chip to be updated according to the update instruction, and control the corresponding switch 3 to switch between the input end and the output end thereof, so that the BMC1 is connected to the BIOS chip to be updated through each stage of the switch 3, so as to perform online update on the BIOS chip to be updated.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a device for updating a BIOS chip online according to the prior art, in which a BMC and a processing module, such as a PCH or a CPU, are switched to be connected to the BIOS chip through a switch in the prior art. The specific control mode of the change-over switch can be as follows: when the BIOS chip normally works, the change-over switch receives a low-level control signal SEL, the port A of the change-over switch is connected with the port B1, and the processing module sends a PCH _ SPI (Serial Peripheral interface) signal to the BIOS chip to serve as a BIOS _ SPI signal of the BIOS chip; when the BIOS chip is updated, the BMC outputs a high level through a GPIO (General-Purpose Input/Output) interface to enable the change-over switch to receive a high-level control signal SEL, at the moment, an A port of the change-over switch is connected with a B2 port, and the BMC sends a BMC-SPI (Serial Peripheral interface) signal to the BIOS chip to serve as a BIOS-SPI signal of the BIOS chip, so that the update of the BIOS chip by the BMC is realized; however, some servers have a plurality of BIOS chips, and the above method cannot support online update of the plurality of BIOS chips, and is low in practicability.
Specifically, in the present application, 4 BIOS chips are taken as an example, referring to fig. 1, in order to implement online update of the BMC1 on the 4 BIOS chips, it is necessary to complete connection between the BMC1 and the 4 BIOS chips online, in the present application, a circuit with a binary tree structure is set between the BMC1 and the 4 BIOS chips by the 0 th-stage switching circuit 21, the first-stage switching circuit 22, and the second-stage switching circuit 23, and after receiving an update instruction and determining a to-be-updated BIOS chip according to the update instruction, the BMC1 may form a communicated circuit in the binary tree structure by controlling the switch 3 in each stage of switching circuit to switch between the input end and the output end thereof to connect the to-be-updated BIOS chip, so as to perform online update on the to-be-updated BIOS chip.
In addition, the last stage switching circuit connected to the BIOS chip, i.e., the second stage switching circuit 23, is composed of two input single output switches, one of which is connected to the first stage switching circuit, i.e., the first stage switching circuit 22, and the other of which is connected to the processing module 4; the second-stage switching circuit 23 connects the processing module 4 or the first-stage switching circuit 22 to the BIOS chip under the control of the BMC1, and updates the BIOS chip when the first-stage switching circuit 22 is connected to the BIOS chip.
In summary, the present application provides an online update device for BIOS chips, where the device forms a binary tree structure through the 0 th stage switching circuit 21, the first stage switching circuit 22, and through each of the switches 3 in the nth stage switching circuit, when receiving an update instruction, the BMC1 determines a BIOS chip to be updated according to the update instruction, and controls the corresponding switch 3 to switch between the input end and the output end thereof, so that the BMC1 is connected to the BIOS chip to be updated through each stage of switches 3, thereby updating the BIOS chip to be updated online. The application realizes the online updating of a plurality of BIOS chips by setting the change-over switch 3 in the multistage switching circuit, and the practicability is higher.
On the basis of the above-described embodiment:
referring to fig. 3, fig. 3 is a schematic structural diagram of another device for online updating of a BIOS chip according to the present invention.
As a preferred embodiment, the nth stage switching circuit further comprises 2nAnd one end of the resistor R is connected with the control end of the change-over switch 3, the connected public end is connected with the BMC1, and the other end of the resistor R is grounded.
In this embodiment, the input signal of the control end of the switch 3 is set to the low level by default through the resistor R, specifically, the control mode of the switch 3 at this time may be: when the control end of the switch 3 receives a low-level control signal SEL, the port A of the switch 3 is connected with the port B1; when the control end of the change-over switch 3 receives a high-level control signal SEL sent by the BMC1, the A port of the change-over switch 3 is connected with the B2 port; other modes may be selected for the control of the changeover switch 3, and are not particularly limited herein.
In addition, after the BMC1 completes the update instruction, the control terminals of all the switches 3 may be released back to the default value, which facilitates the next control.
In summary, the control terminal of the switch 3 is connected to the grounded resistor R, so that the control terminal of the switch 3 is set to the low level by default, and becomes the high level upon receiving the high level signal sent by the BMC1, and the control method is simple.
As a preferred embodiment, the BMC1 is further configured to control the corresponding switch 3 to switch between its input and output terminals when receiving a normal operation command, so that all BIOS chips are connected to the corresponding processing modules 4.
In this embodiment, when the BIOS chips do not need to be updated, the BMC1 receives the normal operating instruction, and then controls all the BIOS chips to connect to the respective corresponding processing modules 4, so that the BIOS chips operate normally; the BIOS chip can be better controlled according to actual conditions.
As a preferred embodiment, the processing module 4 includes a CPU41 and a level shift module 42, and the level shift module 42 is connected between the CPU41 and the switch 3 for performing level shift on data transmitted between the CPU41 and the switch 3.
In this embodiment, when the BIOS chip operates normally, and when the BIOS chip is connected to the CPU41, the BIOS chip is a boot storage chip of the CPU41, and is used to load a boot program when the BIOS chip is turned on, but considering that the working voltage of some CPUs 41 is 1.8V, and at this time, the working voltage needs to be converted into a general 3.3V working voltage, and only the working voltage can be connected to the BIOS chip through the switch 3, so that the level conversion module 42 needs to be further provided between the CPU41 and the switch 3 to perform level conversion on data transmitted between the CPU41 and the switch 3, so that reliability of data transmission is improved, and the transmitted data may be a CPU _ SPI signal, which is used as a BIOS _ SPI signal of the BIOS chip.
In a preferred embodiment, when the update command is a command for updating a single BIOS chip:
the BMC1 is specifically configured to, when receiving an update instruction, determine a single BIOS chip to be updated according to the update instruction, and control the corresponding switch 3 to switch between the input end and the output end thereof, so that the BMC1 is connected to the single BIOS chip to be updated through each stage of the switch 3, so as to perform online update on the single BIOS chip to be updated.
Taking 4 BIOS chips as an example, referring to fig. 3, in this embodiment, for example, when the BMC1 receives an update instruction, it determines that a single BIOS chip to be updated is the first BIOS chip from top to bottom in fig. 3 according to the update instruction, and controls the corresponding switch 3 to switch between the input end and the output end thereof, so that the BMC1 is connected to the first BIOS chip from top to bottom in fig. 3 through each stage of switches 3 to update the BIOS chip.
Specifically, the binary tree structure corresponding to the 4 BIOS chips may be: the BMC _ SPI signal of the BMC1 is first divided into two signals, namely, a BMC _ SPI _ B1 signal and a BMC _ SPI _ B2 signal, by the level 0 switching circuit 21; then, the first-stage switching circuit 22 divides the two signals into four signals, namely, a BMC _ SPI0 signal, a BMC _ SPI1 signal, a BMC _ SPI2 signal and a BMC _ SPI3 signal; the control flow to the corresponding diverter switch 3 may be: the control signal SEL0 is set to be high level through a GPIO0 interface of the BMC1, the control signal SEL1, 2 and 3 is set to be low level through a GPIO1 interface, a GPIO2 interface and a GPIO3 interface, at the moment, the BMC _ SPI signal is switched to a BMC _ SPI _ B1 signal and then to a BMC _ SPI0 signal, and the BMC _ SPI0 signal is used as a BIOS _ SPI signal of a first BIOS chip from top to bottom in the picture 3.
In summary, the BMC1 is connected with a single BIOS chip to be updated by controlling the switching circuits at different levels, so that the update of the single BIOS chip to be updated is completed, the connection of the BMC1 to any BIOS chip can be realized, and the practicability is higher.
As a preferred embodiment, when the update instruction is an instruction to update a plurality of BIOS chips:
the BMC1 is specifically configured to, when receiving an update instruction, determine a plurality of BIOS chips to be updated and an update sequence of the plurality of BIOS chips to be updated according to the update instruction, and control the corresponding switches 3 to switch between the input end and the output end thereof according to the update sequence, so that the BMC1 is sequentially connected to the BIOS chips to be updated through the switches 3 at each stage, so as to perform online update on the BIOS chips to be updated.
Taking 4 BIOS chips as an example, referring to fig. 3, in this embodiment, for example, when the BMC1 receives an update instruction, it determines that a plurality of BIOS chips to be updated are 4 BIOS chips in fig. 3 according to the update instruction, determines that an update sequence is sequentially from top to bottom in fig. 3, and controls the corresponding switches 3 to switch between the input end and the output end thereof so that the BMC1 is sequentially connected to the 4 BIOS chips from top to bottom in fig. 3 through the switches 3 at each stage for updating.
Specifically, the binary tree structure corresponding to the 4 BIOS chips may be: the BMC _ SPI signal of the BMC1 is first divided into two signals, namely, a BMC _ SPI _ B1 signal and a BMC _ SPI _ B2 signal, by the level 0 switching circuit 21; the first stage switching circuit 22 then splits the two signals into four signals, i.e., a BMC _ SPI0 signal, a BMC _ SPI1 signal, a BMC _ SPI2 signal, and a BMC _ SPI3 signal.
The control flow to the corresponding diverter switch 3 may be: the control signal SEL0 is set to be high level through a GPIO0 interface of the BMC1, the control signal SEL1, 2 and 3 is set to be low level through a GPIO1 interface, a GPIO2 interface and a GPIO3 interface, at the moment, the BMC _ SPI signal is switched to a BMC _ SPI _ B1 signal and then to a BMC _ SPI0 signal, and the BMC _ SPI0 signal is used as a BIOS _ SPI signal of a first BIOS chip from top to bottom in the picture 3.
The control signals SEL0 and SEL1 are set to be high level through a GPIO0 interface and a GPIO1 interface of the BMC1, the control signals SEL2 and SEL3 are set to be low level through a GPIO2 interface and a GPIO3 interface, at this time, the BMC _ SPI signal is switched to a BMC _ SPI _ B1 signal and then to a BMC _ SPI1 signal, and the BMC _ SPI1 signal is used as a BIOS _ SPI signal of a second BIOS chip from top to bottom in the FIG. 3.
The control signals SEL0 and SEL3 are set to be high level through a GPIO0 interface and a GPIO3 interface of the BMC1, the control signals SEL1 and SEL2 are set to be low level through a GPIO1 interface and a GPIO2 interface, at this time, the BMC _ SPI signal is switched to a BMC _ SPI _ B2 signal and then to a BMC _ SPI2 signal, and the BMC _ SPI2 signal is used as a BIOS _ SPI signal of a third BIOS chip from top to bottom in the FIG. 3.
The control signals SEL0, SEL2 and SEL3 are set to be high level through a GPIO0 interface, a GPIO2 interface and a GPIO3 interface of the BMC1, the control signal SEL1 is set to be low level through the GPIO1 interface, the BMC _ SPI signal is switched to a BMC _ SPI _ B2 signal and then to a BMC _ SPI3 signal at the moment, and the BMC _ SPI3 signal is used as a BIOS _ SPI signal of a fourth BIOS chip from top to bottom in the FIG. 3.
In summary, the BMC1 and the multiple BIOS chips to be updated are sequentially connected by controlling the switching circuits at each stage, the multiple BIOS chips to be updated are updated, the sequential connection of the BMC1 to the multiple BIOS chips can be realized, and the practicability is higher.
As a preferred embodiment, determining an update sequence of a plurality of BIOS chips to be updated includes:
and determining the updating sequence of the plurality of BIOS chips to be updated based on the serial numbers of the plurality of BIOS chips to be updated.
In this embodiment, the update sequence of the BIOS chips to be updated may be determined according to the serial numbers of the BIOS chips to be updated, or may be other features that can indicate the sequence, which is not particularly limited herein, and the BIOS chips can be updated in sequence more clearly and orderly by determining the update sequence according to the serial numbers.
The application also provides a server, which comprises the device for updating the BIOS chip on line and also comprises a device 2NA BIOS chip and 2NA processing module, a device for on-line updating BIOS chip and 2NA BIOS chip and 2NThe processing modules are connected.
The device for updating the BIOS chip in the server online provided by the present application has been described in detail in all the embodiments, and is not described herein again.
It should be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. An apparatus for online updating of a BIOS chip, comprising:
BMC, 0 th stage switching circuit, the first stage switching circuit to the Nth stage switching circuit, the Nth stage switching circuit including 2nEach of the transfer switches from the 0 th-stage transfer circuit to the first-stage transfer circuit to the (N-1) th-stage transfer circuit is a single-input and two-output switch, each of the transfer switches in the Nth-stage transfer circuit is a two-input and single-output switch, N is a positive integer, and N is a non-negative integer less than or equal to N;
each change-over switch in the 0 th-level change-over circuit, the first-level change-over circuit and the Nth-level change-over circuit forms a binary tree structure, an update pin of the BMC is connected with an input end of the change-over switch of the 0 th-level change-over circuit, the other input end of each change-over switch in the Nth-level change-over circuit is connected with a corresponding processing module, and output ends of each change-over switch in the Nth-level change-over circuit are respectively connected with a corresponding BIOS chip; the control pin of the BMC is also connected with the control ends of all the change-over switches;
the BMC is used for determining the BIOS chip to be updated according to the update instruction when receiving the update instruction, and controlling the corresponding change-over switch to switch between the input end and the output end of the change-over switch so that the BMC is connected with the BIOS chip to be updated through each level of change-over switch to update the BIOS chip to be updated on line.
2. The device for updating BIOS chip on-line of claim 1 wherein the nth stage switching circuit further comprises 2nAnd one end of the resistor is connected with the control end of the change-over switch, the connected public end is connected with the BMC, and the other end of the resistor is grounded.
3. The device for updating the BIOS chips on-line of claim 1, wherein the BMC is further configured to control the corresponding switches to switch between the input and the output thereof when receiving a normal operating command, so that all the BIOS chips are connected to the corresponding processing modules.
4. The device for updating the BIOS chip on-line of claim 1, wherein the processing module comprises a CPU and a level shift module, the level shift module is connected between the CPU and the switch for performing level shift on data transmitted between the CPU and the switch.
5. The device for updating the BIOS chip of any one of claims 1 to 4, wherein when the update instruction is an instruction to update a single BIOS chip:
the BMC is specifically configured to determine a single BIOS chip to be updated according to an update instruction when the update instruction is received, and control a corresponding switch to switch between an input end and an output end of the corresponding switch, so that the BMC is connected with the single BIOS chip to be updated through the switches at each stage, and online update is performed on the single BIOS chip to be updated.
6. The device for updating the BIOS chip of any one of claims 1 to 4, wherein when the update command is a command for updating a plurality of BIOS chips:
the BMC is specifically configured to, when receiving an update instruction, determine a plurality of BIOS chips to be updated according to the update instruction and determine an update sequence of the plurality of BIOS chips to be updated, and control corresponding switches to switch between an input end and an output end of the corresponding switches according to the update sequence so that the BMC is sequentially connected with the BIOS chips to be updated through the switches at each stage to perform online update on the BIOS chips to be updated.
7. The apparatus for updating BIOS chips online according to claim 6, wherein determining an update sequence of the plurality of BIOS chips to be updated comprises:
and determining the updating sequence of the plurality of BIOS chips to be updated based on the serial numbers of the plurality of BIOS chips to be updated.
8. ServerDevice for on-line updating of a BIOS chip according to any of claims 1 to 7, further comprising 2NA BIOS chip and 2NA processing module, the device for on-line updating of the BIOS chip is respectively connected with 2NThe BIOS chip and 2NThe processing modules are connected.
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