CN113110862A - Structure and method for realizing dual-redundancy Flash - Google Patents
Structure and method for realizing dual-redundancy Flash Download PDFInfo
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- CN113110862A CN113110862A CN202110404509.2A CN202110404509A CN113110862A CN 113110862 A CN113110862 A CN 113110862A CN 202110404509 A CN202110404509 A CN 202110404509A CN 113110862 A CN113110862 A CN 113110862A
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- 239000000758 substrate Substances 0.000 claims abstract description 35
- 230000009977 dual effect Effects 0.000 claims abstract description 18
- 230000005540 biological transmission Effects 0.000 claims description 17
- 235000015429 Mirabilis expansa Nutrition 0.000 claims description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/187—Voting techniques
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Abstract
One aspect of the application relates to a structure for realizing dual-redundancy Flash, which comprises a control unit, wherein the control unit is electrically connected with a selection module; the control unit controls the selection module to be connected with the substrate management controller and the main Flash or the standby Flash, or controls the selection module to be connected with the CPU and the main Flash or the standby Flash; the control unit is electrically connected with the substrate management controller and the CPU. The other side of the application relates to a method for realizing dual redundant Flash, which comprises the steps that a main Flash and a standby Flash are automatically switched and connected with a CPU in the process of loading a BIOS; and when the BIOS cannot be loaded, the main Flash and the standby Flash are automatically switched to be connected with the substrate management controller in the process of upgrading the Flash through the substrate management controller. According to the method and the device, the CPU or the substrate management controller can be upgraded in a Flash mode, when the BIOS cannot be loaded in two flashes, the CPU cannot work, the BIOS can be maintained more easily through remote upgrading of the substrate management controller, and the reliability is higher.
Description
Technical Field
The application relates to the field of Flash design, in particular to a structure and a method for realizing dual-redundancy Flash.
Background
The CPU is a core component of the computer equipment, and when the CPU is started, the BIOS needs to be loaded from the Flash; in the prior art, in order to ensure that the BIOS can be loaded stably and reliably, redundancy design is generally carried out on Flash, and a main Flash and a standby Flash are set; when the BIOS can not be loaded from the main Flash, the BIOS is automatically switched to another one for operation.
In the prior art, the existing method for realizing switching controls CPU reset and selection of a main Flash and a standby Flash through a CPLD, when BIOS loading from the main Flash fails, the standby Flash is selected by the CPLD, and a reset signal is output to the CPU, so that the CPU loads BIOS starting from the standby Flash, and when the CPU works, firmware updating of the Flash is completed.
Disclosure of Invention
In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides a structure and a method for implementing dual redundant Flash.
In one aspect, the present application provides a structure for implementing dual redundant Flash, including a control unit, wherein,
the control unit is electrically connected with the selection module;
the control unit controls the selection module to be connected with the substrate management controller and the main Flash or the standby Flash, or controls the selection module to be connected with the CPU and the main Flash or the standby Flash;
the control unit is electrically connected with the substrate management controller and the CPU.
Still further, the selection module comprises a high-speed multiplexer and a single-pole double-throw analog switch, and the control unit is electrically connected with the selection ports of the high-speed multiplexer and the single-pole double-throw analog switch.
Furthermore, the high-speed multiplexer is respectively and electrically connected with the substrate management controller and the data transmission port of the CPU, and the high-speed multiplexer is electrically connected with the data transmission ports of the main Flash and the standby Flash;
the high-speed multiplexer is electrically connected with the substrate management controller and the chip selection port of the CPU respectively, the high-speed multiplexer is electrically connected with the input port of the single-pole double-throw analog switch, and the output port of the single-pole double-throw analog switch is connected with the chip selection ports of the main Flash and the standby Flash respectively.
Further, the data transmission ports are MISO port, MOSI port and CLK port among SPI bus ports.
Furthermore, the control unit is electrically connected with the substrate management controller and the CPU respectively through a bus, and is also electrically connected with the CPU through a GPIO.
On the other hand, the application also provides a method for realizing dual-redundancy Flash, which comprises the steps of
1) Initializing a control unit, so that the control unit controls a high-speed multiplexer and a single-pole double-throw analog switch to connect a CPU (central processing unit) and a main Flash;
2) the CPU loads a BIOS and sends indication information to the control unit according to whether the loading of the slave main Flash is successful or not;
3) the control unit controls the single-pole double-throw analog switch to connect the CPU and the chip selection port of the standby Flash according to the indication information indicating failure;
4) the CPU loads a BIOS and sends indication information to the control unit according to whether the loading of the slave Flash is successful or not;
5) and the control unit judges that the loading fails again according to the indication information, and then the control unit controls the high-speed multiplexer and the single-pole double-throw analog switch to be connected with the substrate management controller and the main Flash or the standby Flash for carrying out Flash upgrading, finishing the upgrading and executing 2) -4).
Preferably, the Flash upgrading process performed by the baseboard management controller includes:
judging whether the CPU is upgrading the main Flash or the standby Flash;
if not, the control unit controls the high-speed multiplexer to be connected with the substrate management controller, the main Flash and the standby Flash through a data transmission channel, and controls the single-pole double-throw analog switch to be connected with the main Flash and the substrate management controller through a chip selection channel;
the management controller upgrades the main Flash, after the upgrade is successful, the control unit controls the single-pole double-throw analog switch to be connected with a standby Flash and the substrate management controller through a chip selection channel, and the management controller upgrades the standby Flash.
Preferably, the Flash upgrading process performed by the CPU includes:
judging whether the substrate management controller is upgrading the main Flash or the standby Flash;
if not, the control unit controls the high-speed multiplexer to be connected with the CPU, the main Flash and the standby Flash through a data transmission channel, and controls the single-pole double-throw analog switch to be connected with the main Flash and the CPU through a chip selection channel;
the CPU upgrades the main Flash, after the upgrade is successful, the control unit controls the single-pole double-throw analog switch to connect the standby Flash and the CPU through a chip selection channel, and the CPU upgrades the standby Flash.
Preferably, when the CPU performs Flash upgrade or the baseboard management controller performs Flash upgrade, the CPU or the baseboard management controller sends upgrade information to the control unit.
Preferably, the baseboard management controller or the CPU receives Flash upgrade information, and the baseboard management controller or the CPU notifies the control unit to perform Flash upgrade.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
according to the structure and the method for realizing the dual-redundancy Flash, the control unit controls the selection module to realize the connection between the CPU and the main Flash or the connection between the CPU and the standby Flash, the BIOS is provided through the main Flash or the standby Flash, and the redundancy of the BIOS is realized; the base plate management controller can be connected with the main Flash and the standby Flash, when the CPU fails to load the BIOS, the main Flash and the standby Flash are upgraded through the base plate management controller, and the BIOS is loaded through the CPU after the BIOS is upgraded successfully, so that the BIOS of the equipment applying the base plate management controller is easy to maintain, and when the BIOS cannot be loaded in the main Flash and the standby Flash, the BIOS is upgraded remotely through the base plate management controller, so that the BIOS has high usability; when the CPU works normally, the main Flash and the standby Flash are upgraded through the CPU, and the redundant design of Flash upgrading is realized.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic diagram of a structure of Flash for implementing dual redundancy according to an embodiment of the present application;
FIG. 2 is a flowchart of a method for implementing dual redundant Flash according to an embodiment of the present application;
fig. 3 is a flowchart illustrating Flash upgrading performed by a baseboard management controller according to an embodiment of the present application;
fig. 4 is a flowchart of Flash upgrading performed by the CPU according to the embodiment of the present application.
The reference numbers and meanings in the figures are as follows:
1. the device comprises a control unit 2, a high-speed multiplexer 3, a substrate management controller 4, a single-pole double-throw analog switch 5, a main Flash6, a standby Flash 7 and a CPU.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Fig. 1 is a schematic diagram of a structure of Flash for implementing dual redundancy according to an embodiment of the present application; FIG. 2 is a flowchart of a method for implementing dual redundant Flash according to an embodiment of the present application; fig. 3 is a flowchart illustrating Flash upgrading performed by a baseboard management controller according to an embodiment of the present application; fig. 4 is a flowchart of Flash upgrading performed by the CPU according to the embodiment of the present application. The english meaning referred to herein: the BMC is a substrate management controller, the FLASH is a memory chip, the BIOS is a basic input/output system, the CPLD is a complex programmable logic device, and the COME International industry Electrical Association (PICMG) defines a computer module standard.
Referring to fig. 1, the present invention provides a structure for implementing dual redundant Flash, which includes a control unit 1, where the control unit 1 may be a complex programmable logic device in a specific implementation process.
The control unit 1 is electrically connected with the selection module; the control unit 1 controls the selection module to be connected with a baseboard management controller 3(BMC) and a main Flash5 or a standby Flash6, or controls the selection module to be connected with a CPU7 and a main Flash5 or a standby Flash 6. In a specific implementation process, the selection module includes a high-speed multiplexer 2 and a single-pole double-throw analog switch 4, and the control unit 1 is electrically connected to the selection ports of the high-speed multiplexer 2 and the single-pole double-throw analog switch 4 through GPIO ports. In implementation, the model of the high-speed multiplexer 2 is 74CBTLV3257, the model of the single-pole double-throw analog switch is SN74LVC1G3157, the 74CBTLV3257 is a four-channel two-select one-high-speed multiplexer, two groups of selectable ports of the high-speed multiplexer 2 are electrically connected to SPI bus ports of the bmc 3 and the CPU7, respectively, a MISO port, a MOSI port and a CLK port in the SPI bus ports are data transmission ports, a CS port is a chip select port, three ports of fixed ports of the high-speed multiplexer 2 connected to the data transmission ports are electrically connected to data transmission ports of a main Flash5 and a backup Flash6, one port of the fixed ports of the high-speed multiplexer 2 connected to the chip select port is electrically connected to an input port of the single-pole double-throw analog switch 4, two output ports of the single-pole double-throw analog switch 4 are connected to chip select ports of the main Flash5 and the backup Flash6, respectively, the single-pole double-throw analog switch 4 controls the input port to be connected with one output port or controls the input port to be connected with the other output port.
The control unit 1 is electrically connected to the board management controller 3 and the CPU 7. The control unit 1 is electrically connected to the bmc 3 and the CPU7 through an I2C bus, respectively, and the control unit 1 is also electrically connected to the CPU7 through a GPIO.
In another aspect, referring to fig. 2, the present application further provides a method for implementing dual redundant Flash, including:
1) initializing a control unit, so that the control unit controls a high-speed multiplexer and a single-pole double-throw analog switch to connect a CPU (central processing unit) and a main Flash; the control unit controls the high-speed multiplexer through a CPU _ BMC _ S channel to enable the CPU to be connected with a main Flash and a standby Flash through a data transmission channel; the control unit controls the single-pole double-throw analog switch through a FLASH0/1_ S channel to enable the CPU to be connected with the main FLASH through a chip selection port.
2) The CPU loads a BIOS and sends indication information to the control unit according to whether the loading of the slave Flash is successful or not; in a specific implementation process, when the CPU successfully loads from the main Flash, the CPU sends the indication information 1 to the control unit through an SYS _ ON _ N channel; and when the CPU fails to load, the CPU sends the indication information 0 to the control unit through an SYS _ ON _ N channel.
3) The control unit controls the single-pole double-throw analog switch to connect the CPU and the chip selection port of the standby Flash according to the indication information indicating failure; specifically, when the indication information received by the control unit is 0, the control unit controls the single-pole double-throw analog switch to connect the CPU and the chip selection port of the standby Flash.
4) The CPU loads a BIOS and sends indication information to the control unit according to whether the loading of the standby Flash is successful or not; in a specific implementation process, when the CPU successfully loads the standby Flash, the CPU sends the indication information 1 to the control unit through an SYS _ ON _ N channel; and when the CPU fails to load, the CPU sends the indication information 0 to the control unit through an SYS _ ON _ N channel.
5) And the control unit judges that the loading fails again according to the indication information, and then the control unit controls the high-speed multiplexer and the single-pole double-throw analog switch to be connected with the substrate management controller and the main Flash or the standby Flash for carrying out Flash upgrading, finishing the upgrading and executing 2) -4). In a specific implementation process, the control unit counts the number of times of receiving the indication information of 0, and when the number of times is 2, the control unit controls the high-speed multiplexer through a CPU _ BMC _ S channel to enable the substrate management controller to be connected with a main Flash and a standby Flash through a data transmission channel; the control unit controls the single-pole double-throw analog switch through a FLASH0/1_ S channel to enable the substrate management controller to be connected with the main FLASH through a chip selection port.
In a specific implementation process, referring to fig. 3, the process of performing Flash upgrade by the baseboard management controller includes:
judging whether the CPU is upgrading the main Flash or the standby Flash; in a specific implementation process, a first register and a second register are configured in the control unit; when the CPU upgrades the main Flash or the standby Flash, the CPU writes a first register as 1 through I2C, and judges whether the CPU upgrades the main Flash or the standby Flash according to the state of the first register.
If not, the control unit controls the high-speed multiplexer to be connected with the substrate management controller, the main Flash and the standby Flash through a data transmission channel, and controls the single-pole double-throw analog switch to be connected with the main Flash and a chip selection port of the substrate management controller;
the management controller upgrades the main Flash, after the upgrade is successful, the control unit controls the single-pole double-throw analog switch to connect the spare Flash and a chip selection port of the substrate management controller, and the management controller upgrades the spare Flash. And setting the number of times of counting the received indication information as 0 by the control unit as 0.
In addition, if the CPU is in the normal operation process, the present application can also perform Flash upgrade through the CPU, referring to fig. 4, where the process of performing Flash upgrade by the CPU includes:
judging whether the substrate management controller is upgrading the main Flash or the standby Flash; when the baseboard management controller upgrades the main Flash or the standby Flash, the baseboard management controller writes a second register as 1 through I2C, and judges whether the baseboard management controller upgrades the main Flash or the standby Flash according to the state of the second register.
If not, the control unit controls the high-speed multiplexer to be connected with the CPU, the main Flash and the standby Flash through a data transmission channel, and controls the single-pole double-throw analog switch to be connected with chip selection ports of the main Flash and the CPU through a chip selection channel;
the CPU upgrades the main Flash, after the upgrade is successful, the control unit controls the single-pole double-throw analog switch to connect the spare Flash and a biased port of the CPU, and the CPU upgrades the spare Flash.
In a specific implementation process, the control unit configures a third register, and the third register configures at least one control bit. When the Flash is upgraded, the control unit controls the single-pole double-throw analog switch by the control bit of the register III. When the CPU loads the BIOS, the control unit controls the single-pole double-throw analog switch by SYS _ ON _ N.
And the substrate management controller or the CPU receives Flash upgrading information, and the substrate management controller or the CPU informs the control unit to carry out Flash upgrading.
According to the structure and the method for realizing the dual-redundancy Flash, the control unit controls the selection module to realize the connection between the CPU and the main Flash or the connection between the CPU and the standby Flash, the BIOS is provided through the main Flash or the standby Flash, and the redundancy of the BIOS is realized; the base plate management controller can be connected with the main Flash and the standby Flash, when the CPU fails to load the BIOS, the main Flash and the standby Flash are upgraded through the base plate management controller, and the BIOS is loaded through the CPU after the BIOS is upgraded successfully, so that the BIOS of the equipment applying the base plate management controller is easy to maintain, and when the BIOS cannot be loaded in the main Flash and the standby Flash, the BIOS is upgraded remotely through the base plate management controller, so that the BIOS has high usability; and when the CPU works normally, upgrading is carried out through the main Flash and the standby Flash of the CPU, so that the upgraded redundancy design is realized.
It should be noted that, in this document, terms such as "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A structure for implementing dual redundant Flash, characterized in that it comprises a control unit (1) in which,
the control unit (1) is electrically connected with the selection module;
the control unit (1) controls the selection module to be connected with the substrate management controller (3) and the main Flash (5) or the standby Flash (6) through a bus, or controls the selection module to be connected with the CPU (7) and the main Flash (5) or the standby Flash (6) through the bus;
the control unit (1) is electrically connected with the substrate management controller (3) and the CPU (7).
2. The architecture for Flash implementing dual redundancy according to claim 1, wherein the selection module comprises a high-speed multiplexer (2) and a single-pole double-throw analog switch (4), and the control unit (1) is electrically connected to the selection ports of the high-speed multiplexer (2) and the single-pole double-throw analog switch (4).
3. The structure for realizing dual redundant Flash according to claim 2, wherein the high-speed multiplexer (2) is electrically connected to the data transmission ports of the baseboard management controller (3) and the CPU (7), respectively, and the high-speed multiplexer (2) is electrically connected to the data transmission ports of the main Flash (5) and the spare Flash (6);
the high-speed multiplexer (2) is electrically connected with chip selection ports of the substrate management controller (3) and the CPU (7) respectively, the high-speed multiplexer (2) is electrically connected with an input port of the single-pole double-throw analog switch (4), and an output port of the single-pole double-throw analog switch (4) is connected with chip selection ports of the main Flash (5) and the standby Flash (6) respectively.
4. The Flash architecture for implementing dual redundancy of claim 3, wherein the bus is an SPI bus, and the data transmission ports are MISO port, MOSI port and CLK port of the SPI bus port.
5. The Flash architecture for implementing dual redundancy according to claim 4, wherein the control unit (1) is electrically connected to the baseboard management controller (3) and the CPU (7) through a bus, respectively, and the control unit (1) is further electrically connected to the CPU (7) through a GPIO.
6. A control method for realizing dual-redundancy Flash is characterized by comprising the following steps
1) Initializing a control unit, so that the control unit controls a high-speed multiplexer and a single-pole double-throw analog switch to connect a CPU (central processing unit) and a main Flash;
2) the CPU loads a BIOS and sends indication information to the control unit according to whether the loading of the slave Flash is successful or not;
3) the control unit controls the single-pole double-throw analog switch to connect the CPU and the chip selection port of the standby Flash according to the indication information indicating failure;
4) the CPU loads a BIOS and sends indication information to the control unit according to whether the loading of the standby Flash is successful or not;
5) and the control unit judges that the loading fails again according to the indication information, and then the control unit controls the high-speed multiplexer and the single-pole double-throw analog switch to be connected with the substrate management controller and the main Flash or the standby Flash for carrying out Flash upgrading, finishing the upgrading and executing 2) -4).
7. The method for controlling Flash with dual redundancy according to claim 6, wherein the Flash upgrading process performed by the baseboard management controller includes:
judging whether the CPU is upgrading the main Flash or the standby Flash;
if not, the control unit controls the high-speed multiplexer to be connected with the substrate management controller, the main Flash and the standby Flash through a data transmission channel, and controls the single-pole double-throw analog switch to be connected with the main Flash and the substrate management controller through a chip selection channel;
the management controller upgrades the main Flash, after the upgrade is successful, the control unit controls the single-pole double-throw analog switch to be connected with a standby Flash and the substrate management controller through a chip selection channel, and the management controller upgrades the standby Flash.
8. The method for controlling Flash with dual redundancy according to claim 6, wherein the step of the CPU performing Flash upgrade includes:
judging whether the substrate management controller is upgrading the main Flash or the standby Flash;
if not, the control unit controls the high-speed multiplexer to be connected with the CPU, the main Flash and the standby Flash through a data transmission channel, and controls the single-pole double-throw analog switch to be connected with the main Flash and the CPU through a chip selection channel;
the CPU upgrades the main Flash, after the upgrade is successful, the control unit controls the single-pole double-throw analog switch to connect the standby Flash and the CPU through a chip selection channel, and the CPU upgrades the standby Flash.
9. The method for controlling Flash with dual redundancy according to claim 7 or 8, wherein when the CPU performs Flash upgrade or the baseboard management controller performs Flash upgrade, the CPU or the baseboard management controller sends upgrade information to the control unit.
10. The method for controlling Flash with dual redundancy according to claim 6, wherein the baseboard management controller or the CPU receives Flash upgrade information, and the baseboard management controller or the CPU notifies the control unit to perform Flash upgrade.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110404509.2A CN113110862A (en) | 2021-04-15 | 2021-04-15 | Structure and method for realizing dual-redundancy Flash |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110404509.2A CN113110862A (en) | 2021-04-15 | 2021-04-15 | Structure and method for realizing dual-redundancy Flash |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114110964A (en) * | 2021-11-26 | 2022-03-01 | 珠海格力电器股份有限公司 | Switching control method and device based on FLASH FLASH memory and air conditioner |
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| US20160147604A1 (en) * | 2014-11-25 | 2016-05-26 | Inventec (Pudong) Technology Corporation | Server system |
| US9542195B1 (en) * | 2013-07-29 | 2017-01-10 | Western Digital Technologies, Inc. | Motherboards and methods for BIOS failover using a first BIOS chip and a second BIOS chip |
| CN208141370U (en) * | 2018-05-23 | 2018-11-23 | 郑州云海信息技术有限公司 | A kind of system for realizing double BIOS startings and upgrading |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9542195B1 (en) * | 2013-07-29 | 2017-01-10 | Western Digital Technologies, Inc. | Motherboards and methods for BIOS failover using a first BIOS chip and a second BIOS chip |
| US20160147604A1 (en) * | 2014-11-25 | 2016-05-26 | Inventec (Pudong) Technology Corporation | Server system |
| CN208141370U (en) * | 2018-05-23 | 2018-11-23 | 郑州云海信息技术有限公司 | A kind of system for realizing double BIOS startings and upgrading |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114110964A (en) * | 2021-11-26 | 2022-03-01 | 珠海格力电器股份有限公司 | Switching control method and device based on FLASH FLASH memory and air conditioner |
| CN114110964B (en) * | 2021-11-26 | 2022-11-18 | 珠海格力电器股份有限公司 | Switching control method and device based on FLASH FLASH memory and air conditioner |
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