CN114124100A

CN114124100A - Noise-shaped SAR ADC with background mismatch calibration

Info

Publication number: CN114124100A
Application number: CN202111457615.3A
Authority: CN
Inventors: 张翼; 高昊; 刘依桦; 刘雅琴; 庄宇航; 姚佳飞; 张瑛; 蔡志匡; 肖建; 郭宇锋
Original assignee: Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd; Nanjing University of Posts and Telecommunications
Current assignee: Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd; Nanjing University of Posts and Telecommunications
Priority date: 2021-12-01
Filing date: 2021-12-01
Publication date: 2022-03-01
Anticipated expiration: 2041-12-01
Also published as: CN114124100B

Abstract

The invention provides a noise shaping SAR ADC with background mismatch calibration, and belongs to the technical field of integrated circuits. The SAR ADC framework adopted by the invention is similar to a general SAR ADC, and the structure comprises a sampling and holding (S/H) module, a binary weighted Capacitor DAC (CDAC), an SAR logic block, a comparator and a digital adder; the presented topology differs from a generic SAR ADC in that it embeds two additional modules: a noise shaping and DAC calibration module. An occasionally active calibration module is able to perform DAC mismatch calibration by using a set of sub-DACs; the residual information vreside, which is normally discarded in a typical SAR conversion, is then reused by the NS block, so that the in-band comparator noise and quantization noise can be changed. The invention combines NS-SAR with new background calibration, combines the advantages of sigma delta and SAR framework, realizes high-precision low-power-consumption framework, and overcomes the limit of comparator noise and DAC mismatch error to the circuit.

Description

Noise-shaped SAR ADC with background mismatch calibration

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a noise shaping SAR ADC with background mismatch calibration.

Background

Among various types of ADCs, continuous-time Delta Sigma (Δ Σ) modulators are widely used architectures in high-resolution applications due to their special Noise Shaping (NS) function, which is achieved by changing the spectral shape of errors in the architecture, thus effectively improving the in-band signal-to-noise ratio (SNR), but such architectures generally require active integrators based on high-performance Operational Transconductance Amplifiers (OTA), which makes them power-consuming and less suitable for expansion; for low power applications such as internet of things (IoT) sensors, a successive approximation register (SAR ADC) is typically chosen to digitize the baseband signal into the digital domain because SAR ADCs are known for their excellent power efficiency and flexible conversion rate (kS/s MS/s) and medium resolution (7-12 b). However, due to the stringent requirements of comparator noise, non-linearity issues caused by digital-to-analog converter (DAC) capacitance mismatch, it is still difficult to extend these advantages to higher resolution designs.

Among these problems, the capacitance mismatch caused by CMOS manufacturing variations is a critical factor that must be considered, and these variations can cause the DAC to have non-linearity problems, which in turn causes the comparator to make a decision incorrectly; these errors can produce Harmonic Distortion (HD) in the spectrum, thereby degrading the overall performance of the ADC. Foreground calibration by post-processing is a common method to correct DAC mismatch errors, but it is usually implemented off-chip due to power consumption and delay overhead. Dynamic Element Matching (DEM) technique is another method that can be used to eliminate mismatch errors, however, the DEM technique is costly to implement in high resolution designs because it requires thermometer coding of the calibration DAC, resulting in complex control logic. Although DAC mismatch errors can also be shaped by Mismatch Error Shaping (MES) techniques, the cost is to sacrifice 6dB of dynamic range by applying the inverse LSB operation.

In addition to DAC mismatch, comparator noise becomes a limiting factor for high resolution designs due to reduced supply voltage and limited input signal swing, and is currently solved by two methods, one of which is to average comparator noise by making multiple decisions from oversampling at the expense of extra cycles; another approach is to use a two-stage pipelined SAR ADC that utilizes a residual amplifier to mitigate comparator noise during fine bit conversion; however, the design of the residual amplifier is not trivial, it also introduces pipeline delays between stages. A reconfigurable comparator is used to handle the conversion cycle in both modes. Although this comparator can compensate for 2-mode offsets through the level shifter, it still faces the comparator noise limitation when extending the architecture to higher resolution designs.

Since the structure of the SAR ADC is simple and clear, oversampling and NS techniques can be used in the SAR-based architecture to suppress comparator noise, this type of ADC combines the advantages of Σ Δ and SAR architectures, enabling a high-precision low-power architecture. The hybrid ADC adopts NS technology by utilizing an active FIR-IIR filter embedded into an oversampling SAR ADC, which proves that the NS technology in the SAR ADC can effectively shape quantization noise and comparator noise into a high-pass filter mode, thereby improving the effective in-band resolution of the ADC after filtering.

From the above, comparator noise and DAC mismatch are major problems limiting the signal-to-noise ratio (SNDR) of SAR ADCs; previous NS work proposed unique solutions, but their disadvantage is the power efficiency of DAC mismatch calibration. The present invention is therefore based on the idea of designing a simpler SAR-based architecture with high SNDR and most advanced efficiency to solve both problems.

Disclosure of Invention

In order to solve the technical problem, the invention provides the noise shaping SAR ADC with background mismatch calibration, and the circuit architecture can realize the analog-to-digital conversion function of the SAR ADC and meet the index requirement of improving the noise of a comparator and the mismatch error of the DAC.

The invention relates to a noise shaping SAR ADC with background mismatch calibration, which comprises a sampling and holding module (namely an S/H module), a binary weighted capacitor DAC (namely a CDAC), a comparator, SAR logic, a digital adder, a noise shaping module and a DAC calibration module; the sampling and holding module, the binary weighted capacitor DAC, the comparator, the SAR logic and the digital adder realize the analog-to-digital conversion function of the traditional SAR ADC, and the noise shaping module and the DAC calibration module are used for improving the noise of the comparator and the mismatch error of the DAC;

the integral clock input signal of the SAR ADC is phi clk, the input signal is a differential signal, and the differential signal is input into the sampling and holding module;

the input signal of the sampling and holding module is a differential signal and a clock signal phi S/H, and the output signal is used as an input signal and enters a comparator module for comparison;

the input signal part of the comparator is from a sampling and holding module, the part of the comparator is from a clock signal phi cmp, and the output signal is used as the input signal of the SAR logic circuit;

the output signals of the SAR logic circuit are respectively input into the digital adder, the binary weighted capacitor DAC and the DAC calibration module;

the output result of the digital adder is the output signal of the SAR ADC, and the output signal of the binary weighted capacitor DAC is connected to the input end of the comparator again;

the noise shaping module is structurally provided with a gain unit and a passive FIR filter, an input signal of the gain unit is residual error information Vresidue and is connected to the input end of a comparator, an output signal of the gain unit is connected to the passive FIR filter, the input signal of the passive FIR filter further comprises clock signals phi gain, phi D2 and phi RST, the output signal of the passive FIR filter is an output signal of the noise shaping module and is connected to a switch controlled by a clock signal phi, and the output end of the switch is connected to the output end of the sampling and holding module;

the DAC calibration module structurally comprises a calibration logic module and a sub-DAC module, wherein an input signal from SAR logic is input into the calibration logic module, an output signal of the calibration logic module is input into the sub-DAC module, and an output signal of the sub-DAC module is input into the binary weighted capacitor DAC.

Further, the binary weighted capacitor DAC consists of 18 capacitors, including C15a, C15b, C14a, C14b, C13-C1 and Cres, wherein the upper plates of the capacitors are all connected to the input end of the comparator, input signals DN <15> -DN <0> are sequentially input to the bottom plates of C15a, C14a, C13-C1 and Cres through the inverters, and input signals DP <15>, DP <14> are sequentially input to the bottom plates of C15b and C14b through the two inverters; a binary weighted capacitive DAC and comparator controlled by SAR logic perform a binary search algorithm with a split monotonic switching scheme.

Further, the split monotonic switching scheme is that, in a binary weighted capacitive DAC architecture, the first 2 MSBs (most significant bits) are made up of four capacitors, C15a, C15b, C14a, C14b, whose bottom plates are controlled by two sets of complementary signals: DP <15>/DN <15> and DP <14>/DN <14 >; mismatch errors of the first 6 MSBs, i.e., C15-C10, can be calibrated by six groups of sub-DACs; with two redundant bits, C8/C4, used to mitigate DAC settling errors and trigger a 6 MSB calibration mechanism.

Furthermore, for the noise shaping module, the structure of the gain unit is an amplifier with a gain of G, and the structure of the passive FIR filter is 3 switched capacitors Cres1, Cres2 and Cdelay which are respectively controlled by clock signals phi gain, phi D2 and phi RST; the amplifier has an input connected to the comparator input, an output connected to two switches controlled by φ gain, which in turn connect the positive terminals of Cres1, Cres2, the positive terminal of Cres1 to the output of the sample and hold module, the positive terminal of Cres2 to a switch controlled by φ D2, the switch controlled by φ D2 to the positive terminal of Cdelay, the positive terminal of Cdelay to the output of the sample and hold module and the switch controlled by φ RST.

Further, the clocks include φ clk, φ S/H, φ EF, φ cmp, φ gain, φ D2 and φ RST, and the clocks jointly form clock control in the SAR ADC architecture, and the clock control can be divided into three parts according to time sequence: residual processing, input tracking, and NS-SAR conversion, represent three different operating states of the SAR ADC, in the residual processing part, φ clk is 1, φ S/H, φ EF and φ cmp are 0, the initial states of φ RST, φ D2 and φ gain are 0, and are changed into 1 in sequence for a period of time and then are set to 0, at this time, the noise shaping module of the SAR ADC is in a working state, the comparator does not work, the SAR ADC does not carry out analog-to-digital conversion, in the input tracking section, φ clk, φ EF, φ cmp, φ RST, φ D2 and φ gain are 0, φ S/H is 1, at which point, the SAR ADC is in a signal sampling state, in the NS-SAR conversion section, φ clk, φ EF are 1, φ S/H, φ RST, φ D2 and φ gain are 0, φ cmp is a 16-cycle square wave signal, at this time, the comparator is in a comparison state and the SAR ADC is in a state to perform SAR conversion.

The invention has the beneficial effects that: the invention takes a traditional SAR ADC as a basic structure, and a noise shaping module and a DAC calibration module are added, so that a framework combining NS-SAR and new background calibration is provided, wherein the NS-SAR is the SAR ADC added with the noise shaping module, and the background calibration is the DAC calibration module, wherein the noise shaping module adopts a mode of shaping quantization noise and comparator noise into a high-pass filter, the effective in-band resolution of the ADC can be improved after filtering, meanwhile, the comparator noise is improved, the background calibration executes DAC mismatch calibration by using a mechanism of a group of sub-DACs, so that the DAC mismatch error is improved, and the structure is suitable for high-resolution design; in addition, a split monotonic switching scheme is adopted in the SAR ADC, and compared with a monotonic switching scheme, the scheme can avoid bringing large VCM changes to the system.

Drawings

In order that the present invention may be more readily and clearly understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.

FIG. 1 is a block diagram of a SAR ADC circuit of the present invention;

FIG. 2 is a circuit diagram of a CDAC of the SAR ADC circuitry of the present invention;

FIG. 3 is a clock signal diagram of the SAR ADC circuitry of the present invention;

FIG. 4 is a graph of a complete conversion of the SAR ADC circuitry of the present invention;

FIG. 5 is an ENOB diagram of the SAR ADC circuitry of the present invention under different Ccalu;

fig. 6 is a graph comparing the performance of the SAR ADC circuit of the present invention.

Detailed Description

As shown in fig. 1, a noise-shaped SAR ADC with background mismatch calibration includes a sample-and-hold (S/H) module, a binary-weighted capacitive DAC (cdac), a comparator, SAR logic, a digital summer, a noise-shaping module, and a DAC calibration module. The sampling and holding (S/H) module, the binary weighted Capacitor DAC (CDAC), the comparator, the SAR logic and the digital adder realize the analog-to-digital conversion function of the traditional SAR ADC, and the noise shaping module and the DAC calibration module are used for improving the noise of the comparator and the mismatch error of the DAC.

The working flow of the SAR ADC is as follows, firstly, a differential input signal is sampled to a binary weighted Capacitor DAC (CDAC) through a sampling and holding (S/H) module, and the clock is phi S/H. The CDAC and comparator controlled by the SAR logic block will then execute a binary search algorithm with a split monotonic switching scheme. Due to the use of redundancy, the original code resulting from the 16 comparison cycles is further processed by a digital adder, eventually giving the digital 14b output code Dout.

As shown in fig. 2, in the binary weighted capacitor DAC structure of the SAR ADC, although the monotonic switching scheme can effectively reduce the DAC size and save the switching power, it can also bring large VCM variation to the system; to avoid this, this work employs a split monotonic switching scheme. The binary weighted capacitor DAC consists of 18 capacitors, including C15a, C15b, C14a, C14b, C13-C1 and Cres, wherein the upper electrode plates of the capacitors are all connected to the input end of a comparator, input signals DN <15> -DN <0> are sequentially input to bottom plates of C15a, C14a, C13-C1 and Cres through inverters, and input signals DP <15> and DP <14> are sequentially input to bottom plates of C15b and C14b through two inverters; in a binary weighted capacitive DAC architecture, the first 2 MSBs are composed of four capacitors (C15a, C15b, C14a, C14b), whose bottom plates are controlled by two sets of complementary signals: DP <15>/DN <15> and DP <14>/DN <14 >. In addition to the first 2 MSBs, there are capacitors in the DAC that have unique uses: mismatch errors of the first 6 MSBs (C15-C10) can be calibrated by six groups of sub-DACs, where the entirety of C15a, C15b is C15, the entirety of C14a, and the entirety of C14b is C14; two of the redundant bits (C8/C4) are used to mitigate DAC settling errors and trigger a 6 MSB calibration mechanism.

In the SAR ADC shown in fig. 1 and 2, comparator noise and DAC mismatch are major problems limiting the signal-to-noise ratio (SNDR) of the SAR ADC. For a DAC calibration module, an occasionally activated calibration module is able to perform DAC mismatch calibration by using a set of sub-DACs. For the noise shaping module, the residual information vreside, which is normally discarded in a typical SAR conversion, is being reused by the NS block, so that the in-band comparator noise and quantization noise can be changed. Typically, in a monotonic switching SAR ADC, the DAC capacitor array is 1 bit lower than the actual ADC resolution because the residual charge on the LSB capacitor is discarded after switching. However, in this work, the residual information needs to be processed by the loop filter and added back to the DAC before the next conversion starts, so an extra Cres is used to preserve the residual charge from each side of the SAR conversion. Wherein, the NS module comprises gain unit and passive FIR filter, comprises 3 switched capacitor: cres1, Cres2 and Cdelay, which are controlled by φ gain, φ D2 and φ RST respectively. Together with the amplifier with gain G, these capacitors will be able to create a second order Noise Transfer Function (NTF) to filter Vresidue. Here, the-1 gain in the FIR filter is not a real amplifier, it is generated by a cross-coupled differential setup.

The clock control of the SAR ADC architecture can be divided into three major parts: residual processing, input tracking and NS-SAR conversion. It is important to keep the clock signals isolated from each other, which helps to prevent unnecessary artifacts in the simulation caused by switching problems.

In the embodiment shown in fig. 1, a 14b NS-SAR ADC is shown, it being noted that 14b is not an arbitrarily set number. The use of such a high resolution oversampling architecture for 12ENOB only seems to be over-designed, but the implicit value of this architecture is that it can also work in SAR-only mode by disabling oversampling and NS blocks, which provides a dual solution to the problem in the circuit, a design that makes the architecture more reliable.

As shown in FIG. 3, the clocks used in the SAR ADC architecture include φ clk, φ S/H, φ EF, φ cmp, φ gain, φ D2 and φ RST, which together constitute the clock control in the SAR ADC architecture; the clocking of the SAR ADC architecture can be divided into three major parts: the residual processing, the input tracking and the NS-SAR conversion respectively represent three different working states of the SAR ADC, and all parts are combined to jointly complete the conversion process of the circuit. In the residual processing part, phi clk is 1, phi S/H, phi EF and phi cmp are 0, the initial states of phi RST, phi D2 and phi gain are 0, and are sequentially changed into 1 for a period of time and then are set to 0, at this time, the noise shaping module of the SAR ADC is in a working state, the comparator does not work, the SAR ADC does not perform analog-to-digital conversion, in the input tracking part, the phi clk, phi EF, phi cmp, phi RST, phi D2 and phi gain are 0, the phi S/H is 1, at this time, the SAR ADC is in a signal sampling state, in the NS-SAR conversion part, the phi clk and phi EF are 1, the phi S/H, phi RST, phi D2 and phi gain are 0, the phi cmp is a square wave signal of 16 cycles, at this time, the comparator is in a comparison state, and the SAR ADC is in a state of executing SAR conversion.

As shown in fig. 4, which shows one complete conversion process of an ADC, with 16 cycles for performing SAR conversion, vresiue will feed the NS block after the 16 th cycle. The dashed line marks the calibration mechanism for DAC mismatch that is occasionally activated by the 17 th cycle. In general, the 16 cycles consist of 14 normal cycles and two redundant cycles (8 th cycle and 12 th cycle). Although the digital adder will eventually give the 14b output code by removing the redundant bits, these redundancy periods can still be used for SAR conversion to mitigate DAC settling errors; more importantly, the first redundancy bit also implements a calibration scheme such that the first 6 MSB capacitors can be calibrated by a bank of sub-DACs.

The model of the EF loop is composed of a gain unit and a charge sharing block, and can be represented by a second-order Noise Transfer Function (NTF), as follows:

NTF(z)＝1-K EF(z-1-0.5z-2)

where KEF is the EF coefficient.

In the SAR ADC architecture, the background calibration topology can be divided into two parts: error detection and error correction; due to redundancy, error detection may be used to check if a DNL error does exist on the MSB; and the MSB will have a coherent sub-DAC, which is a binary weighted capacitor array with unit capacitance Ccalu, that will compensate for DNL loss from the MSB; therefore, like Cu, the size of Ccalu is also an important parameter to determine, since size affects the calibration of MSB. In principle, a smaller Ccalu calibrates better, which results in better performance of the entire ADC, as can be demonstrated by fig. 5. In fig. 5, the calibration works best when Ccalu is 1/16Cu, and it is evident that all of the cases shown in fig. 5 have a substantial improvement after the main DAC calibration is enabled.

As shown in FIG. 6, by combining the above, the overall performance of the circuit is improved, and the SFDR average value is changed from 83.32dB to 95.27 dB.

In summary, compared to the conventional Σ Δ and SAR architecture, the noise-shaping SAR ADC architecture with background mismatch calibration proposed by the present invention embeds two additional modules in the circuit: the noise shaping and DAC calibration module creatively combines NS-SAR with new background calibration, combines the advantages of sigma delta and SAR architectures, realizes a high-precision low-power-consumption architecture, and overcomes the limitation of comparator noise and DAC mismatch error on circuits.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and all equivalent variations made by using the contents of the present specification and the drawings are within the protection scope of the present invention.

Claims

1. A noise-shaping SAR ADC with background mismatch calibration, the SAR ADC comprising a sample-and-hold module, a binary weighted capacitive DAC, a comparator, SAR logic, a digital adder, a noise-shaping module, a DAC calibration module;

2. The SAR ADC of claim 1, wherein the binary weighted capacitor DAC comprises 18 capacitors including C15a, C15b, C14a, C14b, C13-C1 and Cres, upper plates of the capacitors are connected to an input end of the comparator, input signals DN <15> -DN <0> are sequentially input to bottom plates of C15a, C14a, C13-C1 and Cres through inverters, and input signals DP <15>, DP <14> are sequentially input to bottom plates of C15b and C14b through two inverters; a binary weighted capacitive DAC and comparator controlled by SAR logic perform a binary search algorithm with a split monotonic switching scheme.

3. A noise-shaping SAR ADC with background mismatch calibration according to claim 2, wherein said split monotonic switching scheme is such that, in a binary weighted capacitive DAC architecture, the first 2 MSBs are composed of four capacitors C15a, C15b, C14a, C14b whose plates are controlled by two sets of complementary signals: DP <15>/DN <15> and DP <14>/DN <14 >; mismatch errors of the first 6 MSBs, i.e., C15-C10, can be calibrated by six groups of sub-DACs; with two redundant bits, C8/C4, used to mitigate DAC settling errors and trigger a 6 MSB calibration mechanism.

4. The SAR ADC with background mismatch calibration as claimed in claim 1, wherein for the noise shaping module, the structure is gain unit and passive FIR filter, the gain unit is gain amplifier, the passive FIR filter is 3 switched capacitors Cres1, Cres2 and Cdelay, respectively controlled by clock signals φ gain, φ D2 and φ RST; the amplifier has an input connected to the comparator input, an output connected to two switches controlled by φ gain, which in turn connect the positive terminals of Cres1, Cres2, the positive terminal of Cres1 to the output of the sample and hold module, the positive terminal of Cres2 to a switch controlled by φ D2, the switch controlled by φ D2 to the positive terminal of Cdelay, the positive terminal of Cdelay to the output of the sample and hold module and the switch controlled by φ RST.

5. The noise-shaping SAR ADC with background mismatch calibration of claim 1, wherein: the clock comprises phi clk, phi S/H, phi EF, phi cmp, phi gain, phi D2 and phi RST, and the clocks jointly form clock control in the SAR ADC framework, and the clock control can be divided into three parts according to time sequence: residual processing, input tracking, and NS-SAR conversion, represent three different operating states of the SAR ADC, in the residual processing part, φ clk is 1, φ S/H, φ EF and φ cmp are 0, the initial states of φ RST, φ D2 and φ gain are 0, and are changed into 1 in sequence for a period of time and then are set to 0, at this time, the noise shaping module of the SAR ADC is in a working state, the comparator does not work, the SAR ADC does not carry out analog-to-digital conversion, in the input tracking section, φ clk, φ EF, φ cmp, φ RST, φ D2 and φ gain are 0, φ S/H is 1, at which point, the SAR ADC is in a signal sampling state, in the NS-SAR conversion section, φ clk, φ EF are 1, φ S/H, φ RST, φ D2 and φ gain are 0, φ cmp is a 16-cycle square wave signal, at this time, the comparator is in a comparison state and the SAR ADC is in a state to perform SAR conversion.