CN114124066B - Environment slowly-changing self-adaptive capacitance induction detection system - Google Patents
Environment slowly-changing self-adaptive capacitance induction detection system Download PDFInfo
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Abstract
The invention relates to the technical field of capacitance induction detection, in particular to an environment-graded self-adaptive capacitance induction detection system, which comprises an analog system and a digital system; the analog system comprises a gating circuit and an analog processing circuit; the digital system comprises a counter, a shift data difference subtracter, a comparison decision device, a one-time programming memory, a data latch and a digital master control circuit. In the detection process of the system, ADC is not needed to participate in conversion detection, so that the system power consumption is obviously reduced; when the threshold environment self-adaptive algorithm is executed, the threshold does not drift, and when the system is delivered to a client, the client can directly use the system only by performing simple OTP programming, does not need to develop again, and is convenient to use.
Description
Technical Field
The invention relates to the technical field of capacitance induction detection, in particular to an environment-graded self-adaptive capacitance induction detection system.
Background
The principle of the existing capacitive sensing detection system is generally as follows: the circuit is provided with an emitter TX and a receiver RX, the capacitance sub-capacitance or mutual capacitance is firstly converted into an electric signal, the electric signal is then digitized through the ADC circuit, a specific digital quantized value is obtained, and a decision logic judges and gives a conclusion according to the digital quantized value. As shown in fig. 1, the invention patent with publication number CN107247529a discloses a capacitive sensing detection scheme, from which it can be seen that the capacitive sensing circuit has an emitter TX and a receiver RX, and the capacitive sub-capacitance or mutual capacitance is firstly converted into an electrical signal, and then the electrical signal is digitized after being converted by the processing circuit ADC, so as to obtain a specific digital quantized value; finally, judging and giving a conclusion according to the numerical quantization value by a judgment logic. In the above circuit structure, as shown in fig. 2, the judgment threshold is given according to the application environment: 1) And the finger threshold and the upper and lower hysteresis ranges are used for judging the touch and the departure of the finger. The upper hysteresis judgment touches, and the lower hysteresis judgment leaves. 2) A noise threshold is given for baseline updating. The method is characterized in that the drift (the slow change of the numerical value) of an output result is caused by the slow change of the environment, and the change caused by the environment change is different from the rapid change of noise introduced by interference, so that a noise threshold value is required to be set, noise judgment is required to be carried out, a base line is updated, the judgment is based on an absolute value, then the threshold value, a hysteresis range, the base line, the noise threshold value and the like are set on the basis of the absolute value, so that data to be processed are huge and complex, and the final judgment can be completed only by matching the MCU+algorithm, thereby increasing the requirement of a system on resources. In summary, the traditional capacitance sensing detection system has a complex circuit structure, needs AD conversion, and the conversion structure from the capacitor to the voltage (namely C2V) is easily affected by external interference, and the judging process needs MCU or a filter for processing, so that the complexity, the area, the cost and the energy consumption of the system are high, and the popularization and the application of the system are not facilitated.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an environment-friendly adaptive capacitance induction detection system.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
an environment-adaptive capacitance sensing detection system comprises an analog system and a digital system;
the analog system comprises a gating circuit and an analog processing circuit;
The digital system comprises a counter, a shift data difference subtracter, a comparison decision device, a one-time programming memory, a data latch and a digital main control circuit;
the analog processing circuit provides reference current and reference voltage for the whole system, provides a reset signal for the digital system, provides a clock signal for the counter, and is matched with the frequency of the touch key signal, receives the touch key signal accessed by the gating circuit and converts the touch key signal into a pulse signal to be output to the counter;
The counter counts the number of the received pulse signals in the length of the matched clock signals, the counted value is recorded as a converted pulse value and is sent into a shift data difference subtracter, and the lengths of the clock signals matched with different touch key signals are different;
The shift data difference subtracter divides the received conversion pulse value and stores the divided value into a shift register corresponding to the touch key signal, and performs subtraction operation on the value and a certain subtraction number to generate a difference result, the difference result is sent into a comparison decision device, and the certain subtraction number in the subtraction operation is selected from the stored values in the shift register;
the comparison decision device receives the difference result, selects a preset threshold value matched with the touch key signal for comparison, generates a decision result and sends the decision result to the digital main control circuit;
The digital main control circuit is responsible for controlling the operation of the whole system, the gating circuit is controlled by the data latch to gate N touch keys, the analog processing circuit is controlled by the data latch to output clock signals matched with the frequency of the touch key signals, the length of the clock signals matched with the counter is controlled, the shift register selection and the reduction selection of the shift data difference subtracter are controlled, the preset threshold selection of the comparison decision device is controlled, the decision result output by the comparison decision device is received and compared with the continuous triggering condition corresponding to the touch keys, and the key triggering result is output to the upper computer;
The one-time programmable memory is used for writing the clock signal frequency, the reduction selection condition, the clock signal length selection condition, the preset threshold information and the touch key continuous triggering condition required by the system and providing the conditions for the digital main control circuit.
Preferably, the gating circuit comprises a switch decoding circuit and N communicating switches, and the analog processing circuit comprises a capacitance pulse conversion circuit, a clock circuit, a reference voltage circuit, a reference current circuit and a reset circuit; n input ends of the switch decoding circuit are respectively connected with N touch keys through N communication switches, and an output end of the switch decoding circuit is connected with the digital main control circuit through a data latch; the input end of the capacitance pulse conversion circuit receives N touch key signals in a time sharing way, and the output end of the capacitance pulse conversion circuit is connected with the input end of the counter; the reference current circuit provides reference currents for the capacitor pulse conversion circuit, the clock circuit, the reference voltage circuit and the reset circuit respectively; the reference voltage circuit provides reference voltage for the reset circuit; the clock circuit receives the control signal from the digital main control circuit and outputs a clock signal to the counter; the reset circuit provides a reset signal to the digital system.
Preferably, the capacitive pulse conversion circuit includes a first current source Idcp, a second current source Idcn, a switch SW0, a switch SW1, an inverter Inv2, and a buffer Buf1; one end of the switch SW0, one end of the switch SW1 and the input end of the inverter Inv1 are connected as the input ends of the capacitance pulse conversion circuit; the output end of the inverter Inv1 is connected with the input end of the inverter Inv 2; the output end of the inverter Inv2 is connected with the input end of the buffer Buf1; the output end of the buffer Buf1 is used as the output end of the capacitor pulse conversion circuit; one end of the current source Idcp is taken as a VDD end, the other end of the current source Idcp is respectively connected with the other end of the switch SW0, one end of the current source Idcn is taken as ground, and the other end of the current source Idcp is connected with the other end of the switch SW 1.
Preferably, the clock circuit includes a switch SW10, a switch SW11, an inverter Inv3, an inverter Inv4, a buffer Buf2 and a gate capacitance group; the gating capacitor group comprises M+1 capacitors and M+1 switches, each capacitor is matched with one switch, one end of each M+1 capacitor is grounded, and the other end of each M+1 capacitor is connected with one end of a switch SW10, one end of a switch SW11 and the input end of an inverter Inv3 after passing through the matched switches; the output end of the inverter Inv3 is connected with the input end of the inverter Inv 4; the output end of the inverter Inv4 is connected with the input end of the buffer Buf 2; the output end of the buffer Buf2 is used as the output end of the clock circuit; the other end of the switch SW10 is connected with the VDD terminal; the other end of the switch SW11 is grounded.
Preferably, the shift data difference subtracter comprises a data storage selector, N shift registers and N subtractors, wherein the input end of the data storage selector is connected with the output end of the counter, the enabling end is connected with the digital main control circuit, the N output ends are respectively connected with the input ends of the N shift registers, the output ends of the N shift registers are respectively connected with the input ends of the N subtractors, and the output ends of the N subtractors are connected with the input ends of the comparison decision device.
Preferably, each shift register is composed of M registers connected in a stepwise manner, the output end of the 1 st register is connected with the input end of a subtracter corresponding to the shift register, the input end of the 1 st register is connected with the output end of the 2 nd register, the input end of the 2 nd register is connected with the output end of the 3 rd register, and so on, the input end of the M-1 st register is connected with the output end of the M-th register, the input end of the M-th register is connected with the output end of the data storage selector, the subtracted number of the subtracter when performing subtraction operation is from the 1 st register, and the subtracted number is from any one of the M registers.
Preferably, the comparison decision device comprises a decision device and a threshold value register, wherein the input end of the decision device is connected with the output ends of the N subtractors, and the threshold value register stores N preset threshold values which are matched with the N touch key signals respectively and provides the N preset threshold values for the decision device.
From the above description, it can be seen that the present invention has the following advantages:
1. in the system detection process, ADC is not needed to participate in conversion detection, so that the power consumption of the system is obviously reduced;
2. The system does not need to set a fixed threshold, but is used as a threshold environment self-adaptive algorithm, and the required threshold is written into a one-time programmable memory (OTP for short) according to the algorithm;
3. When the environment changes slowly, the difference result output by the subtracter is not influenced by the environment change, and when the difference result is compared with the threshold value of the comparison decision device, the threshold value is used as a judgment standard without changing, so that the judgment threshold value of the system is accurate and drift does not occur;
4. the system subtracter outputs a relative difference value, when the environment changes slowly, the change of the output result of the comparison decision device is negligible, and the system can automatically adapt to the environment change;
5. When the system is delivered to a customer, the customer can directly use the system after only simple OTP programming, and does not need to develop again.
Drawings
FIG. 1 is a schematic diagram of a conventional capacitive sensing circuit;
FIG. 2 is a schematic diagram of a judgment principle of the circuit structure shown in FIG. 1;
FIG. 3 is a system block diagram of the present invention;
FIG. 4 is a block diagram of a simulation system of the present invention;
FIG. 5 is a schematic diagram of a capacitive pulse conversion circuit of the present invention;
FIG. 6 is a schematic diagram of a clock circuit of the present invention;
FIG. 7 is a timing diagram of the system initialization signal according to the present invention;
FIG. 8 is a schematic diagram of OTP programming in accordance with the present invention;
FIG. 9 is a schematic diagram of the counter operation principle of the present invention;
FIG. 10 is a schematic diagram of the counter of the present invention;
FIG. 11 is a timing diagram of a clock circuit signal according to the present invention;
FIG. 12 is a schematic diagram of a signal timing diagram of a capacitive pulse conversion circuit according to the present invention;
FIG. 13 is a schematic diagram of the operation of the data storage selector of the present invention;
FIG. 14 is a schematic diagram of the working principle of the shift data difference subtractor of the present invention;
Fig. 15 is a schematic diagram of the working principle of the decision device of the present invention;
fig. 16 is a schematic diagram of the working principle of the digital master control circuit of the present invention.
Detailed Description
One embodiment of the present invention will be described in detail with reference to fig. 3 to 16, but does not limit the claims of the present invention.
As shown in fig. 3, an environment-friendly adaptive capacitive sensing detection system comprises an analog system and a digital system;
(1) As shown in fig. 4, the analog system includes a gate circuit and an analog processing circuit; wherein:
the gating circuit comprises a switch decoding circuit and N communication switches;
The analog processing circuit comprises a capacitance pulse conversion circuit, a clock circuit, a reference voltage circuit, a reference current circuit and a reset circuit;
N input ends (K1, K2 … … Kn) of the switch decoding circuit are respectively connected with N touch keys through N communicating switches (K1, K2 … … Kn), an output end is connected with the digital main control circuit through a data latch, the input end of the capacitance pulse conversion circuit receives N touch key signals in a time sharing way, the output end is connected with the input end of the counter, the reference current circuit respectively provides reference current for the capacitance pulse conversion circuit, the clock circuit, the reference voltage circuit and the reset circuit, the reference voltage circuit provides reference voltage for the reset circuit, the clock circuit receives control signals from the digital main control circuit and outputs clock signals to the counter; the reset circuit provides a reset signal to the digital system.
As shown in fig. 5, the preferred scheme of the capacitive pulse conversion circuit is: the circuit comprises a first current source Idcp, a second current source Idcn, a switch SW0, a switch SW1, an inverter Inv2 and a buffer Buf1; one end of the switch SW0, one end of the switch SW1 and the input end of the inverter Inv1 are connected as the input ends of the capacitance pulse conversion circuit; the output terminal of the inverter Inv1 is connected to the input terminal of the inverter Inv 2; the output end of the inverter Inv2 is connected with the input end of the buffer Buf1; the output end of the buffer Buf1 is used as the output end of the capacitor pulse conversion circuit; one end of the current source Idcp is taken as a VDD end, the other end of the current source Idcp is respectively connected with the other end of the switch SW0, one end of the current source Idcn is taken as ground, and the other end of the current source Idcp is connected with the other end of the switch SW 1.
As shown in fig. 6, the preferred scheme of the clock circuit is: including a switch SW10, a switch SW11, an inverter Inv3, an inverter Inv4, a buffer Buf2 and a gate capacitance group; the gating capacitor group comprises M+1 capacitors and M+1 switches, each capacitor is matched with one switch, one end of each M+1 capacitor is grounded, and the other end of each M+1 capacitor is connected with one end of a switch SW10, one end of a switch SW11 and the input end of an inverter Inv3 after passing through the matched switches; the output terminal of the inverter Inv3 is connected to the input terminal of the inverter Inv 4; the output end of the inverter Inv4 is connected with the input end of the buffer Buf 2; the output end of the buffer Buf2 is used as the output end of the clock circuit; the other end of the switch SW10 is connected with the VDD terminal; the other end of the switch SW11 is grounded.
(2) As shown in fig. 3, the digital system includes a counter, a shift data difference subtractor, a comparison decision device, a one-time programmable memory, a data latch, and a digital master circuit;
The shift data difference subtracter comprises a data storage selector, N shift registers and N subtractors, wherein the input end of the data storage selector is connected with the output end of the counter, the enabling end of the data storage selector is connected with the digital main control circuit, the N output ends of the data storage selector are respectively connected with the input ends of the N shift registers, the output ends of the N shift registers are respectively connected with the input ends of the N subtractors, and the output ends of the N subtractors are connected with the input ends of the comparison decision device;
Each shift register is composed of M registers connected step by step, i.e., N shift registers are N register groups, in each shift register, an output end of a register 1 is connected with an input end of a subtractor corresponding to the shift register, an input end is connected with an output end of a register 2, an input end of the register 2 is connected with an output end of a register 3, and so on, an input end of a register M-1 is connected with an output end of a register M, an input end of the register M is connected with an output end of a data storage selector, a subtracted number of the subtractor when the subtractor performs subtraction operation is from the 1 st register, and a subtracted number of the subtractor is from any one of the M registers.
The comparison decision device comprises a decision device and a threshold value register, wherein the input end of the decision device is connected with the output ends of the N subtractors, and the threshold value register stores N preset threshold values which are matched with the N touch key signals respectively and provides the N preset threshold values for the decision device.
The working principle of the invention is as follows:
(1) The analog processing circuit provides reference current and reference voltage for the whole system, provides a reset signal for the digital system, provides a clock signal for the counter, and the clock signal is matched with the frequency of the touch key signal, receives the touch key signal accessed by the gating circuit and converts the touch key signal into a pulse signal to be output to the counter;
(2) Counting the number of the received pulse signals in the matched clock signal length by a counter, recording the counted value as a converted pulse value, and sending the converted pulse value into a shift data difference subtracter, wherein the matched clock signal lengths of different touch key signals are different;
(3) The shift data difference subtracter divides the received conversion pulse value and stores the divided value into a shift register corresponding to the touch key signal, and performs subtraction operation on the value and a certain subtraction number to generate a difference result, the difference result is sent into a comparison decision device, and a certain subtraction number in the subtraction operation is selected from the stored values in the shift register;
(4) The comparison decision device receives the difference result, selects a preset threshold value matched with the touch key signal for comparison, generates a decision result and sends the decision result to the digital main control circuit;
(5) The digital main control circuit is responsible for controlling the operation of the whole system, the gating circuit is controlled by the data latch to gate N touch keys, the analog processing circuit is controlled by the data latch to output clock signals matched with the frequency of the touch key signals, the length of the clock signals matched with the counter is controlled, the shift register selection and the reduction selection of the shift data difference subtracter are controlled, the preset threshold selection of the comparison decision device is controlled, the decision result output by the comparison decision device is received and compared with the continuous triggering condition corresponding to the touch keys, and the key triggering result is output to the upper computer;
(6) The one-time programmable memory is used for writing the clock signal frequency, the reduction selection condition, the clock signal length selection condition, the preset threshold information and the touch key continuous triggering condition required by the system and providing the conditions to the digital main control circuit.
The workflow of the present system is described in detail below in conjunction with fig. 7-16:
1. Before system supply, initializing the system, and writing clock signal frequency, a reduction selection condition, a clock signal length selection condition, preset threshold information and key triggering conditions required by a writing system required by a system application occasion into a one-time programming memory through an I2C serial port, wherein the specific steps are as follows:
(1) Clock signal frequency: different matching capacitors are configured for different keys, so that the frequencies of clock and capacitor key conversion pulses are close to each other when no touch occurs; and the clock matching capacitors corresponding to different keys are burnt in the OTP registers corresponding to the keys, and when the keys are selected, the corresponding matching capacitor connection modes are read out.
(2) The reduction selection conditions: selecting a reduction number from the register 2 to the register m according to the requirement of the detected key triggering speed; and selecting which is burnt in the OTP, reading the set value from the OTP after the power-on reset is completed, and writing the set value into a control register of the corresponding digital main control circuit.
(3) Clock signal length selection condition: the pulse width increment of the induction pulse is closely related to the clock length when the key is touched, and the larger the pulse width increment is, the shorter the clock signal statistical length is; conversely, the smaller the pulse width increment, the longer the clock signal statistical length; the length of the clock signal is burnt in the OTP, and after the power-on reset is completed, the set value is read out from the OTP and written into a control register of the corresponding digital master control circuit.
(4) Predetermined threshold information: the preset threshold value is used as a basis for triggering pre-judgment, and the pre-judgment can be triggered only when the pulse difference value obtained by the subtracter is larger than the preset threshold value; the preset threshold information is burnt in the OTP, and after the power-on reset is completed, the set value is read out from the OTP and written into a control register of the corresponding digital main control circuit.
(5) Key triggering condition: when the continuous triggering times of the keys reach the set times of the pressing triggering conditions, the keys are judged to be triggered, and the keys are not judged to be interfered and are ignored; the key triggering condition is that the continuous triggering number is burnt in the OTP, and after the power-on reset is completed, the set value is read out from the OTP and written into a control register of the corresponding digital main control circuit.
2. System application
Step 1: as shown in fig. 7 and 8, the system is powered on for resetting, reading OTP content, and configuring a register judgment threshold value, a scan sequence number, a trigger number judgment value, a counter count length setting value, and the like.
Step 2: as shown in fig. 8, keys K1 to Kn are selected according to the number of keys written in the OTP and the sequence by the sensing channel gate line, and the keys to be detected are selected to the analog processing circuit, and bus_sel0 to bus_sel7 in fig. 8 can respectively correspond to the values to be determined in each link in the system and the setting of the number of times required for judging continuous triggering. In the step, after the system delivers the client, the client mainly formulates the judging index required by the system according to the application requirement of the client, and the system can be directly used after simple OTP programming is performed without secondary development.
Step 3: as shown in fig. 9 and 10, the conversion from capacitance to pulse corresponding to the touch key is completed by an analog processing circuit, and the capacitance conversion output pulse is sent to a counter of the digital system, the counter takes an analog system sending clock (which is generated by a clock circuit of the analog system) as a time reference, and records the number of conversion pulses within the set time length (set clock number) of the OTP, in this process, ADC is not needed to participate in conversion detection, and the system power consumption is significantly reduced.
The working principle of the capacitor pulse conversion circuit and the clock circuit in the step is as follows: as shown in fig. 6, the capacitor is charged and discharged by a fixed current, and the charge and discharge switch is controlled by cascading feedback with a plurality of inverters to form a positive feedback circuit, so that the capacitor is periodically charged and discharged by the circuit, and the conversion from the tested capacitor to periodic pulse is completed.
In the circuit structure shown in fig. 6, the gating capacitor group includes m+1 capacitors (i.e., the capacitors Cr0, cr1, cr2, … …, crm-1, crm) and m+1 switches (i.e., the switches SW4, SW5, SW6, … …, swm+3, swm+4), and the m+1 switches control the m+1 capacitors, thereby forming the gating capacitor group compared with the capacitance Csc to be measured of the touch key connected in the circuit shown in fig. 5.
The waveforms of the signal Vrf and the signal CLK of the branch where the gate capacitor group is located are shown in fig. 11, and the waveforms of the signal Vsc and the signal sc_bits of the branch where the capacitor Csc to be measured is located are shown in fig. 12, if the following conditions exist:
Condition 1: when the capacitance value of the capacitor Csc to be measured is equal to the sum of the capacitance values of the gating capacitor groups Cr 0-Crm, the pulse width of the signal CLK is the same as that of the signal SC_bits, namely the frequency of the signal CLK is the same as that of the signal SC_bits;
Condition 2: when the capacitance value of the capacitor Csc to be detected is larger than the sum of the capacitance values of the gating capacitor groups Cr 0-Crm, the pulse width of the signal CLK is smaller than that of the signal SC_bits, namely the frequency of the signal CLK is larger than that of the signal SC_bits;
Condition 3: when the capacitance Csc of the capacitor to be measured is smaller than the sum of the capacitance Cr 0-Crm of the gating capacitor group, the pulse width of the signal CLK is larger than that of the signal SC_bits and is the same, i.e. the frequency of the signal CLK is smaller than that of the signal SC_bits.
Therefore, a capacitive sensing detection scheme of an analog system is set based on the above conditions, and is specifically as follows: by adopting the condition 3, according to the capacitance increment on the capacitance Csc to be detected during touching, selecting a determined gating capacitance from the gating capacitance groups Cr0 to Crm, when the capacitance Csc to be detected is not pressed, making the sum of the gating capacitances Cr0 to Crm be larger than the capacitance Csc to be detected by a certain proportion (1%, 2%, 4%, 8%, 16%, etc.), wherein the frequency of the signal CLK is lower than the frequency of the signal SC_bits; when the capacitor Csc to be measured is pressed, the capacitance sum value of the gating capacitors Cr 0-Crm is smaller than the capacitance value of the capacitor Csc to be measured after the capacitance value of the capacitor Csc to be measured is overlapped with the pressing induction value, and the frequency of the signal CLK is higher than the frequency of the signal SC_bits. In the above, when a specific gate capacitor is selected, a part or all of the gate capacitors are selected according to the capacitance values of the capacitors to be measured, so long as the sum of all the capacitance values satisfies the above-mentioned determination condition.
Step 4: as shown in fig. 13, after the counter sets the recording time to be full, the value of the recording conversion pulse is sent to the corresponding shift register RegGrup-RegGrupn of the selected touch key through the data storage selector;
It should be noted that in the above process, the key selected by the system is a circular scan, so that the corresponding data in the register set is moved in parallel outwards once every time the circular scan is completed. As the number of cycles increases, all registers in the N register sets will be full, and as the cycle scan continues, the earliest arriving record data will be discarded first, and so on, all the most current data is left in the register sets.
Step 5: the difference value calculation of each selected key is completed through a subtracter 1-a subtracter n, certain data in a shift register is selected according to a reduced number X register in a register group, the touch result of each selected touch key is obtained through R1-Rx, and the difference value DeltaD 1-DeltaDn is obtained and is sent into a decision device; fig. 14 is a schematic diagram showing the operation of one set of registers and subtractors.
In the above process, since the cyclic scan is performed all the time, the subsequent Delta value is fed into the determiner DETERMINE without interruption.
In this step, since the output value is a relative difference, when the environment changes slowly, the output DeltaDx changes, which is considered to be automatically adaptive to the environment change, can be ignored.
Step 6: as shown in fig. 15, the decider compares the difference values obtained by the subtractors 1 to n with the incoming values (the set threshold values for the incoming OTP) in the threshold registers (1 to n). If the difference value is larger than or equal to the set threshold value, judging that the trigger exists, outputting 1 to the digital main control circuit, and outputting 0 if the trigger does not exist; the key set is scanned circularly all the time, so that the judging result is continuously sent to the digital main control circuit all the time;
In this step: a fixed threshold is not required to be set, and a threshold environment self-adaptive algorithm is adopted; the threshold value is judged not to drift, and since DeltaDx is the difference value of the front and rear data, when the external environment changes slowly, the front and rear data are consistent in environmental change, so the data difference value of the front and rear data is almost unchanged when the finger is pressed, and the judgment threshold value is not required to be changed.
Step 7: as shown in fig. 16, the digital master control circuit controls the entire system to run in a loop and makes a final decision on the result. The method comprises the following steps: (1) The device is responsible for circularly controlling operation and is used for fixing work after power-on; (2) final arbitration: the digital main control circuit compares the number of times of continuous triggering of the corresponding key received from the judgment output of the comparison judgment device with the set value of the OTP, and if the effective number of times of continuous triggering judgment of the key reaches the configuration number of times read out from the OTP, the key is judged to be triggered; if the corresponding times are not reached, the method is judged to be false triggering or interference and does not respond. When the key is judged to be triggered, the INT signal is pulled up to inform the upper computer to read the information of the trigger key, and when the upper computer issues a read command through the I2C, the information of the trigger key is uploaded to the upper computer.
In summary, the invention has the following advantages:
1. In the system detection process, ADC is not needed to participate in conversion detection, so that the system power consumption is obviously reduced;
2. The system does not need to set a fixed threshold, but is used as a threshold environment self-adaptive algorithm, and the required threshold is written into a one-time programming memory according to the algorithm;
3. When the environment changes slowly, the difference result output by the subtracter is not influenced by the environment change, and when the difference result is compared with the threshold value of the comparison decision device, the threshold value is used as a judgment standard without changing, so that the judgment threshold value of the system is accurate and drift does not occur;
4. the system subtracter outputs a relative difference value, when the environment changes slowly, the change of the output result of the comparison decision device is negligible, and the system can automatically adapt to the environment change;
5. When the system is delivered to a customer, the customer can directly use the system after only performing simple OTP programming, does not need to develop again, and is convenient to use.
It is to be understood that the foregoing detailed description of the invention is merely illustrative of the invention and is not limited to the embodiments of the invention. It will be understood by those of ordinary skill in the art that the present invention may be modified or substituted for elements thereof to achieve the same technical effects; as long as the use requirement is met, the invention is within the protection scope of the invention.
Claims (7)
1. An environment slowly-varying self-adaptive capacitance sensing detection system is characterized in that: including analog systems and digital systems;
the analog system comprises a gating circuit and an analog processing circuit;
The digital system comprises a counter, a shift data difference subtracter, a comparison decision device, a one-time programming memory, a data latch and a digital main control circuit;
the analog processing circuit provides reference current and reference voltage for the whole system, provides a reset signal for the digital system, provides a clock signal for the counter, and is matched with the frequency of the touch key signal, receives the touch key signal accessed by the gating circuit and converts the touch key signal into a pulse signal to be output to the counter;
The counter counts the number of the received pulse signals in the length of the matched clock signals, the counted value is recorded as a converted pulse value and is sent into a shift data difference subtracter, and the lengths of the clock signals matched with different touch key signals are different;
The shift data difference subtracter divides the received conversion pulse value and stores the divided value into a shift register corresponding to the touch key signal, and performs subtraction operation on the value and a certain subtraction number to generate a difference result, the difference result is sent into a comparison decision device, and the certain subtraction number in the subtraction operation is selected from the stored values in the shift register;
the comparison decision device receives the difference result, selects a preset threshold value matched with the touch key signal for comparison, generates a decision result and sends the decision result to the digital main control circuit;
The digital main control circuit is responsible for controlling the operation of the whole system, the gating circuit is controlled by the data latch to gate N touch keys, the analog processing circuit is controlled by the data latch to output clock signals matched with the frequency of the touch key signals, the length of the clock signals matched with the counter is controlled, the shift register selection and the reduction selection of the shift data difference subtracter are controlled, the preset threshold selection of the comparison decision device is controlled, the decision result output by the comparison decision device is received and compared with the continuous triggering condition corresponding to the touch keys, and the key triggering result is output to the upper computer;
The one-time programmable memory is used for writing the clock signal frequency, the reduction selection condition, the clock signal length selection condition, the preset threshold information and the touch key continuous triggering condition required by the system and providing the conditions for the digital main control circuit.
2. The environmentally-friendly adaptive capacitive sensing detection system of claim 1, wherein:
the gating circuit comprises a switch decoding circuit and N communication switches, and the analog processing circuit comprises a capacitance pulse conversion circuit, a clock circuit, a reference voltage circuit, a reference current circuit and a reset circuit;
n input ends of the switch decoding circuit are respectively connected with N touch keys through N communication switches, and an output end of the switch decoding circuit is connected with the digital main control circuit through a data latch;
The input end of the capacitance pulse conversion circuit receives N touch key signals in a time sharing way, and the output end of the capacitance pulse conversion circuit is connected with the input end of the counter;
the reference current circuit provides reference currents for the capacitor pulse conversion circuit, the clock circuit, the reference voltage circuit and the reset circuit respectively;
The reference voltage circuit provides reference voltage for the reset circuit;
the clock circuit receives the control signal from the digital main control circuit and outputs a clock signal to the counter;
the reset circuit provides a reset signal to the digital system.
3. The environmentally-friendly adaptive capacitive sensing detection system of claim 2, wherein:
The capacitance pulse conversion circuit comprises a first current source Idcp, a second current source Idcn, a switch SW0, a switch SW1, an inverter Inv2 and a buffer Buf1;
One end of the switch SW0, one end of the switch SW1 and the input end of the inverter Inv1 are connected as the input ends of the capacitance pulse conversion circuit;
the output end of the inverter Inv1 is connected with the input end of the inverter Inv 2;
The output end of the inverter Inv2 is connected with the input end of the buffer Buf 1;
The output end of the buffer Buf1 is used as the output end of the capacitor pulse conversion circuit;
one end of the current source Idcp is taken as a VDD end, the other end of the current source Idcp is respectively connected with the other end of the switch SW0, one end of the current source Idcn is taken as ground, and the other end of the current source Idcp is connected with the other end of the switch SW 1.
4. The environmentally-friendly adaptive capacitive sensing detection system of claim 3, wherein: the clock circuit comprises a switch SW10, a switch SW11, an inverter Inv3, an inverter Inv4, a buffer Buf2 and a gating capacitor bank;
The gating capacitor group comprises M+1 capacitors and M+1 switches, each capacitor is matched with one switch, one end of each M+1 capacitor is grounded, and the other end of each M+1 capacitor is connected with one end of a switch SW10, one end of a switch SW11 and the input end of an inverter Inv3 after passing through the matched switches;
the output end of the inverter Inv3 is connected with the input end of the inverter Inv 4;
the output end of the inverter Inv4 is connected with the input end of the buffer Buf 2;
the output end of the buffer Buf2 is used as the output end of the clock circuit;
The other end of the switch SW10 is connected with the VDD terminal;
The other end of the switch SW11 is grounded.
5. The environmentally-friendly adaptive capacitive sensing detection system of claim 4, wherein: the shift data difference subtracter comprises a data storage selector, N shift registers and N subtractors, wherein the input end of the data storage selector is connected with the output end of the counter, the enabling end of the data storage selector is connected with the digital main control circuit, the N output ends of the shift data difference subtracter are respectively connected with the input ends of the N shift registers, the output ends of the N shift registers are respectively connected with the input ends of the N subtractors, and the output ends of the N subtractors are connected with the input end of the comparison decision device.
6. The environmentally-friendly adaptive capacitive sensing detection system of claim 5, wherein: each shift register is composed of M registers which are connected step by step, the output end of the 1 st register is connected with the input end of a subtracter corresponding to the shift register, the input end of the 1 st register is connected with the output end of the 2 nd register, the input end of the 2 nd register is connected with the output end of the 3 rd register, and the like, the input end of the M-1 st register is connected with the output end of the M th register, the input end of the M th register is connected with the output end of a data storage selector, the subtracter is subjected to subtraction when the subtracter performs subtraction operation, the subtracted number is from the 1 st register, and the subtracted number is from any one of the M registers.
7. The environmentally-friendly adaptive capacitive sensing detection system of claim 6, wherein: the comparison decision device comprises a decision device and a threshold value register, wherein the input end of the decision device is connected with the output ends of the N subtractors, and the threshold value register stores N preset threshold values which are matched with the N touch key signals respectively and provides the N preset threshold values for the decision device.
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