CN212305298U - Environment slowly-varying self-adaptive capacitance induction detection system - Google Patents
Environment slowly-varying self-adaptive capacitance induction detection system Download PDFInfo
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Abstract
The utility model relates to the technical field of capacitance induction detection, in particular to an environment gradual change self-adaptive capacitance induction detection system, which comprises an analog system and a digital system; the analog system comprises a gating circuit and an analog processing circuit; the digital system comprises a counter, a shift data difference subtracter, a comparison decision device, a one-time programming memory, a data latch and a digital master control circuit. In the detection process of the system, ADC is not required to participate in conversion detection, so that the power consumption of the system is obviously reduced; the threshold environment self-adaptive algorithm is executed, the threshold value can not drift, when the system is delivered to a client, the client can directly use the system only after simple OTP programming, secondary development is not needed, and the use is convenient.
Description
Technical Field
The utility model relates to a capacitance sensing detects technical field, especially relates to an environment slowly changes self-adaptation capacitance sensing detecting system.
Background
The principle of the existing capacitive sensing detection system is generally as follows: the circuit is provided with an emitting electrode TX and a receiving electrode RX, the capacitance sub-capacitance or mutual capacitance is firstly converted into an electric signal, the voltage signal is subjected to digital processing through an ADC circuit to obtain a specific digital quantization value, and then a decision logic judges and gives a conclusion according to the digital quantization value. As shown in fig. 1, the invention patent with chinese patent publication No. CN107247529A discloses a capacitance sensing detection scheme, in which a capacitance sensing circuit has an emitter TX and a receiver RX, and first converts the capacitance of a capacitor or a mutual capacitance into an electrical signal, and then converts the electrical signal into a digital signal by a processing circuit ADC, and then digitizes the electrical signal to obtain a specific digital quantization value; and finally, the decision logic judges and gives a conclusion according to the numerical value quantization value. In the above circuit structure, as shown in fig. 2, the judgment threshold is given according to the application environment: 1) and the finger threshold value and the upper and lower hysteresis ranges are used for judging the finger touch and the finger off. The upper hysteresis determines touch and the lower hysteresis determines off. 2) A noise threshold is given for baseline updating. The reason is that the slow change of the environment can cause the drift of the output result (the value changes slowly), and the change caused by the environment change is slow change and the noise introduced by the interference changes rapidly, so a noise threshold needs to be set, noise judgment and baseline updating need to be carried out, and the judgment is based on an absolute value, and then a threshold, a hysteresis range, a baseline, a noise threshold and the like are set on the basis of the absolute value, so that the data needing to be processed is huge and complex, and the MCU + algorithm matching processing is needed to complete the final judgment, thereby increasing the requirement of the system on resources. In summary, the conventional capacitive sensing detection system is not only complex in circuit structure and needs to undergo AD conversion, but also the conversion structure from the capacitor to the voltage (i.e., C2V) is susceptible to external interference, and the determination process needs an MCU or a filter for processing, which finally results in high system complexity, large area, high cost and high energy consumption, and is not beneficial to popularization and application of the system.
SUMMERY OF THE UTILITY MODEL
To the problem among the prior art, the utility model provides an environmental slow change self-adaptation capacitance induction detecting system.
In order to realize the technical purpose, the technical proposal of the utility model is that:
an environment slowly-varying self-adaptive capacitance induction detection system comprises an analog system and a digital system;
the analog system comprises a gating circuit and an analog processing circuit;
the digital system comprises a counter, a shift data difference subtracter, a comparison decision device, a one-time programming memory, a data latch and a digital master control circuit;
the analog processing circuit provides reference current and reference voltage for the whole system, provides a reset signal for the digital system, provides a clock signal for the counter, the clock signal is matched with the frequency of the touch key signal, receives the touch key signal accessed by the gating circuit, converts the touch key signal into a pulse signal and outputs the pulse signal to the counter;
the counter counts the number of the received pulse signals within the matched clock signal length, the counted value is recorded as a conversion pulse value and is sent to the shift data difference value subtracter, and the clock signal lengths matched with different touch key signals are different;
the shift data difference subtracter divides the received conversion pulse value, stores the divided value into a shift register corresponding to the touch key signal, performs subtraction operation on the value and a certain subtraction number to generate a difference result, and sends the difference result to a comparison decision device, wherein the certain subtraction number in the subtraction operation is selected from the stored values in the shift register;
the comparison decision device receives the difference result, selects a preset threshold value matched with the touch key signal for comparison, and generates a decision result to be sent to the digital main control circuit;
the digital main control circuit is responsible for controlling the operation of the whole system, the data latch is used for controlling the gating circuit to gate the N touch keys, the data latch is used for controlling the analog processing circuit to output a clock signal matched with the frequency of the touch key signal, the length of the clock signal matched with the counter is controlled, the selection and the subtraction selection of a shift register of the shift data difference subtracter are controlled, the selection of a preset threshold value of the comparison decision device is controlled, the decision result output by the comparison decision device is received and compared with the continuous trigger condition corresponding to the touch keys, and the key trigger result is output to the upper computer;
the one-time programming memory is used for writing the clock signal frequency, the decrement selection condition, the clock signal length selection condition, the preset threshold information and the touch key continuous triggering condition required by the system and providing the clock signal frequency, the decrement selection condition, the clock signal length selection condition, the preset threshold information and the touch key continuous triggering condition to the digital main control circuit.
Preferably, the gating circuit comprises a switch decoding circuit and N communicating switches, and the analog processing circuit comprises a capacitance pulse conversion circuit, a clock circuit, a reference voltage circuit, a reference current circuit and a reset circuit; n input ends of the switch decoding circuit are respectively connected with N touch keys through N communicating switches, and an output end of the switch decoding circuit is connected with the digital main control circuit through a data latch; the input end of the capacitance pulse conversion circuit receives N touch key signals in a time-sharing manner, and the output end of the capacitance pulse conversion circuit is connected with the input end of the counter; the reference current circuit provides reference currents for the capacitance pulse conversion circuit, the clock circuit, the reference voltage circuit and the reset circuit respectively; the reference voltage circuit provides reference voltage for the reset circuit; the clock circuit receives the control signal from the digital main control circuit and outputs a clock signal to the counter; the reset circuit provides a reset signal for the digital system.
Preferably, the capacitance pulse converting circuit includes a first current source Idcp, a second current source Idcn, a switch SW0, a switch SW1, an inverter Inv1, an inverter Inv2, and a buffer Buf 1; one end of the switch SW0 and one end of the switch SW1 are connected with the input end of the inverter Inv1 to serve as the input end of the capacitance pulse conversion circuit; the output end of the inverter Inv1 is connected to the input end of the inverter Inv 2; the output end of the inverter Inv2 is connected to the input end of the buffer Buf 1; the output end of the Buf1 buffer is used as the output end of the capacitance pulse conversion circuit; one end of the current source Idcp serves as a VDD terminal, the other end of the current source Idcp is connected with the other end of the switch SW0, one end of the current source Idcn serves as a ground, and the other end of the current source Idcp is connected with the other end of the switch SW 1.
Preferably, the clock circuit includes a switch SW10, a switch SW11, an inverter Inv3, an inverter Inv4, a buffer Buf2, and a gating capacitor bank; the gating capacitor group comprises M +1 capacitors and M +1 switches, each capacitor is matched with one switch, one end of each of the M +1 capacitors is grounded, and the other end of each capacitor is connected with one end of the switch SW10, one end of the switch SW11 and the input end of the inverter Inv3 after passing through the matched switches; the output end of the inverter Inv3 is connected to the input end of the inverter Inv 4; the output end of the inverter Inv4 is connected to the input end of the buffer Buf 2; the output end of the Buf2 buffer is used as the output end of the clock circuit; the other end of the switch SW10 is connected with a VDD end; the other end of the switch SW11 is grounded.
Preferably, the shift data difference subtracter comprises a data storage selector, N shift registers and N subtracters, wherein an input end of the data storage selector is connected with an output end of the counter, an enabling end of the data storage selector is connected with the digital main control circuit, N output ends of the data storage selector are respectively connected with input ends of the N shift registers, output ends of the N shift registers are respectively connected with input ends of the N subtracters, and output ends of the N subtracters are connected with input ends of the comparison decision device.
Preferably, each of the shift registers is composed of M registers connected in a stepwise manner, an output terminal of a 1 st register is connected to an input terminal of a subtractor corresponding to the shift register, an input terminal of the subtractor is connected to an output terminal of a 2 nd register, an input terminal of a 2 nd register is connected to an output terminal of a 3 rd register, and so on, an input terminal of an M-1 th register is connected to an output terminal of an M th register, an input terminal of an M th register is connected to an output terminal of a data storage selector, and a subtracted number when the subtractor performs subtraction operation is from the 1 st register, and the subtracted number is from any one of the M registers.
Preferably, the comparison decider comprises a decider and a threshold register, an input end of the decider is connected with output ends of the N subtractors, and the threshold register stores N predetermined thresholds respectively matched with the N touch key signals and provides the N predetermined thresholds to the decider.
As can be seen from the above description, the present invention has the following advantages:
1. in the system detection process, an ADC (analog to digital converter) is not required to participate in conversion detection, so that the power consumption of the system is obviously reduced;
2. the system does not need to set a fixed threshold value, but does a threshold value environment self-adaptive algorithm, and writes the required threshold value into a one-time programming memory (OTP for short) according to the algorithm;
3. when the environment changes slowly, the difference result output by the subtracter is not influenced by the environment change, and when the difference result is compared with the threshold of the comparison decision device, the threshold is taken as a judgment standard and does not need to be changed, so that the judgment threshold of the system is accurate and does not drift;
4. the output of the subtracter of the system is a relative difference value, when the environment changes slowly, the change of the output result of the comparison decision device can be ignored, and the system can automatically adapt to the environment change;
5. when the system is delivered to a client, the client can directly use the system only after simple OTP programming, and secondary development is not needed.
Drawings
FIG. 1 is a schematic circuit diagram of a conventional capacitive sensing circuit;
FIG. 2 is a schematic diagram illustrating the circuit structure of FIG. 1;
fig. 3 is a block diagram of the system of the present invention;
fig. 4 is a block diagram of the simulation system of the present invention;
fig. 5 is a schematic diagram of the capacitance pulse conversion circuit of the present invention;
fig. 6 is a schematic diagram of the clock circuit of the present invention;
fig. 7 is a timing diagram of the system initialization signal of the present invention;
FIG. 8 is a schematic diagram of OTP programming of the present invention;
FIG. 9 is a schematic view of the working principle of the counter of the present invention;
FIG. 10 is a schematic view of the working principle of the counter of the present invention;
FIG. 11 is a timing diagram of the clock circuit of the present invention;
fig. 12 is a schematic diagram of the signal timing sequence of the capacitor pulse converting circuit according to the present invention;
FIG. 13 is a schematic diagram of the operation of the data storage selector of the present invention;
fig. 14 is a schematic diagram of the operation principle of the displacement data difference subtracter of the present invention;
fig. 15 is a schematic diagram of the operation principle of the decision device of the present invention;
fig. 16 is a schematic diagram of the operation principle of the digital main control circuit of the present invention.
Detailed Description
With reference to fig. 3 to 16, a specific embodiment of the present invention is described in detail, but the present invention is not limited to the claims.
As shown in fig. 3, an environmental-gradient adaptive capacitance sensing detection system includes an analog system and a digital system;
(1) as shown in fig. 4, the analog system includes a gating circuit and an analog processing circuit; wherein:
the gating circuit comprises a switch decoding circuit and N communicating switches;
the analog processing circuit comprises a capacitance pulse conversion circuit, a clock circuit, a reference voltage circuit, a reference current circuit and a reset circuit;
n input ends (K1, K2 … … Kn) of the switch decoding circuit are respectively connected with N touch keys through N communicating switches (K1, K2 … … Kn), an output end of the switch decoding circuit is connected with the digital master control circuit through a data latch, the input end of the capacitance pulse conversion circuit receives N touch key signals in a time-sharing mode, the output end of the capacitance pulse conversion circuit is connected with the input end of the counter, the reference current circuit respectively provides reference currents for the capacitance pulse conversion circuit, the clock circuit, the reference voltage circuit and the reset circuit, the reference voltage circuit provides reference voltage for the reset circuit, the clock circuit receives control signals from the digital master control circuit and outputs clock signals to the counter; the reset circuit provides a reset signal for the digital system.
As shown in fig. 5, the preferred scheme of the capacitance pulse converting circuit is as follows: comprises a first current source Idcp, a second current source Idcn, a switch SW0, a switch SW1, an inverter Inv1, an inverter Inv2 and a buffer Buf 1; one end of the switch SW0 and one end of the switch SW1 are connected to the input end of the inverter Inv1, and serve as the input end of the capacitance pulse conversion circuit; the output end of the inverter Inv1 is connected to the input end of the inverter Inv 2; the output end of the inverter Inv2 is connected to the input end of the buffer Buf 1; the output end of the buffer Buf1 is used as the output end of the capacitance pulse conversion circuit; one end of the current source Idcp serves as a VDD terminal, the other end thereof is connected to the other end of the switch SW0, one end of the current source Idcn serves as a ground, and the other end thereof is connected to the other end of the switch SW 1.
As shown in fig. 6, the preferred scheme of the clock circuit is: the inverter comprises a switch SW10, a switch SW11, an inverter Inv3, an inverter Inv4, a buffer Buf2 and a gating capacitor group; the gating capacitor group comprises M +1 capacitors and M +1 switches, each capacitor is matched with one switch, one end of each capacitor M +1 is grounded, and the other end of each capacitor M +1 is connected with one end of the switch SW10, one end of the switch SW11 and the input end of the inverter Inv3 after passing through the matched switches; the output end of the inverter Inv3 is connected to the input end of the inverter Inv 4; the output end of the inverter Inv4 is connected to the input end of the buffer Buf 2; the output end of the Buf2 buffer is used as the output end of the clock circuit; the other end of the switch SW10 is connected with a VDD end; the other end of switch SW11 is connected to ground.
(2) As shown in fig. 3, the digital system includes a counter, a shifted data difference subtracter, a comparison decision device, a one-time programming memory, a data latch and a digital master control circuit;
the shift data difference subtracter comprises a data storage selector, N shift registers and N subtracters, wherein the input end of the data storage selector is connected with the output end of the counter, the enabling end of the data storage selector is connected with the digital main control circuit, the N output ends of the data storage selector are respectively connected with the input ends of the N shift registers, the output ends of the N shift registers are respectively connected with the input ends of the N subtracters, and the output ends of the N subtracters are connected with the input end of the comparison decision device;
each shift register is composed of M registers connected step by step, namely N shift registers are N register groups, in each shift register, the output end of a register 1 is connected with the input end of a subtracter corresponding to the shift register, the input end of the register 2 is connected with the output end of a register 3, and so on, the input end of a register M-1 is connected with the output end of a register M, the input end of the register M is connected with the output end of a data storage selector, the subtracted number of the subtracter in subtraction operation is from the 1 st register, and the subtracted number is from any one of the M registers.
The comparison decision device comprises a decision device and a threshold value register, wherein the input end of the decision device is connected with the output ends of the N subtracters, the threshold value register stores N preset threshold values which are respectively matched with the N touch key signals, and the N preset threshold values are provided for the decision device.
The utility model discloses a theory of operation does:
(1) the analog processing circuit provides reference current and reference voltage for the whole system, provides a reset signal for the digital system, provides a clock signal for the counter, the clock signal is matched with the frequency of the touch key signal, receives the touch key signal accessed by the gating circuit, converts the touch key signal into a pulse signal and outputs the pulse signal to the counter;
(2) the counter counts the number of the received pulse signals within the matched clock signal length, the counted value is recorded as a conversion pulse value and is sent to the shift data difference value subtracter, and the clock signal lengths matched with different touch key signals are different;
(3) the shift data difference subtracter divides the received conversion pulse value, stores the divided value into a shift register corresponding to the touch key signal, performs subtraction operation on the value and a certain subtraction number to generate a difference result, and sends the difference result to the comparison decision device, wherein the certain subtraction number in the subtraction operation is selected from the stored values in the shift register;
(4) the comparison decision device receives the difference result, selects a preset threshold value matched with the touch key signal for comparison, generates a decision result and sends the decision result to the digital main control circuit;
(5) the digital main control circuit is responsible for controlling the operation of the whole system, controls the gating circuit to gate the N touch keys through the data latch, controls the analog processing circuit to output a clock signal matched with the frequency of the touch key signal through the data latch, controls the length of the clock signal matched with the counter, controls the selection and the subtraction selection of a shift register of the shift data difference subtracter, controls the selection of a preset threshold of the comparison decision device, receives a decision result output by the comparison decision device, compares the decision result with a continuous trigger condition corresponding to the touch key, and outputs a key trigger result to the upper computer;
(6) the one-time programming memory is used for writing the clock signal frequency, the decrement selection condition, the clock signal length selection condition, the preset threshold information and the touch key continuous triggering condition required by the system and providing the clock signal frequency, the decrement selection condition, the clock signal length selection condition, the preset threshold information and the touch key continuous triggering condition to the digital main control circuit.
The operation of the present system is described in detail below with reference to FIGS. 7-16:
1. before the system supplies goods, the system is initialized, and the clock signal frequency, the decrement selection condition, the clock signal length selection condition, the preset threshold information and the key triggering condition which are required by the write-in system and are required by the write-in system application occasion of the one-time programming memory are written into the one-time programming memory through an I2C serial port, and the method specifically comprises the following steps:
(1) clock signal frequency: configuring different matching capacitors for different keys to enable the frequency of conversion pulses of the clock and the capacitor keys to be close to that of the conversion pulses of the capacitor keys when no touch occurs; and the clock matching capacitors corresponding to different keys are burnt in the corresponding OTP registers, and when the keys are selected, the corresponding matching capacitor connection modes are read out.
(2) The number of subtraction selection conditions: selecting a decrement from the registers 2 to m according to the requirement of the trigger speed of the detected key; and selecting which one is burnt in the OTP, reading the set value from the OTP after the power-on reset is completed, and writing the set value into a control register of the corresponding digital main control circuit.
(3) Clock signal length selection conditions: the induction pulse width increment of the key when being touched is closely related to the clock length, and the larger the pulse width increment is, the shorter the statistical length of the clock signal is; conversely, the smaller the pulse width increment, the longer the statistical length of the clock signal; the length of the clock signal is burnt in the OTP, and after the power-on reset is completed, the set value is read out from the OTP and is written into a control register of the corresponding digital main control circuit.
(4) Predetermined threshold information: the predetermined threshold is used as the basis for triggering pre-judgment, and the pulse difference obtained by the subtracter is larger than the predetermined threshold, so that the pulse difference can be judged to be triggered; and after the power-on reset is completed, reading the set value from the OTP and writing the value into a control register of the corresponding digital main control circuit.
(5) The key triggering conditions are as follows: when the continuous triggering times of the keys reach the set times of the pressing triggering conditions, judging to be triggered, and neglecting when the judgment result is not reached; and (3) reading the set value from the OTP after the power-on reset is completed and writing the set value into a control register of the corresponding digital main control circuit.
2. System applications
Step 1: as shown in fig. 7 and 8, the system is powered on and reset, the OTP content is read, and the register determination threshold value, the scan number, the trigger determination value, the counter count length setting value, and the like are configured.
Step 2: as shown in fig. 8, according to the key serial number written in the OTP and the sequence of gating the keys K1-Kn through the sensing channel, the key to be detected is selected to the analog processing circuit, and Bus _ sel 0-Bus _ sel7 in fig. 8 can be respectively set corresponding to the value required to be determined by each link in the system and the value of the number of times required to determine the continuous triggering. In the step, after the system delivers the client, the client mainly makes a judgment index required by the system according to the application requirement of the client, and the system can be directly used without secondary development after simple OTP programming.
And step 3: as shown in fig. 9 and 10, the capacitance-to-pulse conversion of the corresponding touch key is completed through the analog processing circuit, and the capacitance conversion output pulse is sent to the counter of the digital system, the counter takes the analog system sending clock (the clock is generated by the clock circuit of the analog system) as the time reference, and records the number of conversion pulses in the set time length (the set clock number) of the OTP, during the process, the ADC is not needed to participate in the conversion detection, and the system power consumption is reduced remarkably.
The working principle of the capacitance pulse conversion circuit and the clock circuit in the step is as follows: as shown in fig. 6, the capacitor is charged and discharged by a fixed current, and is cascaded with a plurality of inverters to feedback control the charge and discharge switches, so as to form a positive feedback circuit, thereby realizing the periodic charge and discharge of the capacitor by the circuit, and completing the conversion from the tested capacitor to the periodic pulse.
In the circuit structure shown in fig. 6, the gated capacitor group includes M +1 capacitors (i.e., capacitors Cr0, Cr1, Cr2, … …, Crm-1, and Crm) and M +1 switches (i.e., switches SW4, SW5, SW6, … …, SWm +3, and SWm +4), and the M +1 switches control the M +1 capacitors, thereby forming a gated capacitor group that is compared with the capacitor Csc to be tested of the touch key connected in the circuit shown in fig. 5.
Waveforms of the Vrf signal and the CLK signal of the branch where the gating capacitor bank is located are shown in fig. 11, waveforms of the Vsc signal and the SC _ Bits signal of the branch where the capacitor to be measured Csc is located are shown in fig. 12, and if the following conditions exist:
condition 1: when the capacitance value of the capacitor Csc to be measured is equal to the sum of the capacitance values of the gating capacitor groups Cr 0-Crm, the pulse width of the signal CLK is the same as that of the signal SC _ Bits, namely the frequency of the signal CLK is the same as that of the signal SC _ Bits;
condition 2: when the capacitance value of the capacitor Csc to be measured is larger than the sum of the capacitance values of the gating capacitor groups Cr 0-Crm, the signal CLK is smaller than the signal SC _ Bits and has the same pulse width, namely the frequency of the signal CLK is larger than the frequency of the signal SC _ Bits;
condition 3: when the capacitance value of the capacitor Csc to be measured is smaller than the sum of the capacitance values of the gating capacitor groups Cr 0-Crm, the signal CLK is larger than the signal SC _ Bits and has the same pulse width, namely the frequency of the signal CLK is smaller than the frequency of the signal SC _ Bits.
Therefore, a capacitance sensing detection scheme of the analog system is set based on the above conditions, which specifically includes: by adopting the condition 3, according to the capacitance increment on the capacitance Csc to be detected during touch, selecting the determined gating capacitance from the gating capacitance groups Cr 0-Crm, and when the capacitance Csc to be detected is not pressed, enabling the sum of the gating capacitances Cr 0-Crm to be larger than the capacitance Csc to be detected by a certain proportion (1%, 2%, 4%, 8%, 16% and the like), wherein the frequency of the signal CLK is lower than the frequency of the signal SC _ Bits at the moment; when the capacitor Csc to be detected is pressed, the capacity sum value of the gating capacitors Cr 0-Crm is smaller than the capacity value of the capacitor Csc to be detected after the pressing induction value is superposed on the capacity value of the capacitor Csc to be detected, and the frequency of the signal CLK is higher than the frequency of the signal SC _ Bits. In the above, when a specific gating capacitor is selected, a part or all of the gating capacitors are selected according to the capacitance value of the capacitor to be measured, and the sum of all capacitance values of the gating capacitors is only required to meet the determination condition.
And 4, step 4: as shown in fig. 13, after the counter is full of record in the set recording time, the counter sends the record conversion pulse value to the corresponding shift register RegGrup 1-RegGrupn of the selected touch key through the data storage selector;
it should be noted that, in the above process, the system selects the key as the circular scanning, so that the corresponding data in the register set moves out in parallel once after each circular scanning. As the number of cycles increases, all registers in the N register banks will be full, and as the cycle scan continues, the oldest recorded data will be lost first, and so on, leaving the newest data in the register banks.
And 5: finishing the calculation of the difference value of each selected key through a subtracter 1-a subtracter n, selecting certain data in a shift register according to a subtracted number X register in a register group, obtaining the touch result of each selected touch key through R1-Rx to obtain the difference value DeltaD 1-DeltaDn, and sending the difference value into a decision device; fig. 14 is a schematic diagram of the operation of one set of registers and subtractors.
In the above process, since the circular scanning is always performed, the subsequent Delta value will be sent to the decimeter without interruption.
In this step, since the output value is a relative difference value, when the environment changes slowly, the change of the output DeltaDx can be ignored and is considered to be automatically adaptive to the environment change.
Step 6: as shown in fig. 15, the decision device compares the difference values obtained by the subtractors 1 to n with the incoming values (the set threshold values from the OTP) in the threshold registers (1 to n). If the difference value is larger than or equal to the set threshold value, judging that the trigger exists, outputting 1 to the digital main control circuit, and judging that the trigger does not exist, outputting 0; because the key group is in cyclic scanning all the time, the judgment result is sent to the digital main control circuit all the time;
in this step: a fixed threshold value is not required to be set, and a threshold value environment self-adaptive algorithm is carried out; the threshold value is judged not to drift, and because DeltaDx is the difference value of the front data and the rear data, when the external environment slowly changes, the front data and the rear data are consistent due to the change of the environment, so that the data difference value of the front data and the rear data when a finger presses the front data and the rear data is almost unchanged, and the judged threshold value does not need to be changed.
And 7: as shown in fig. 16, the digital master control circuit controls the whole system to operate circularly and makes final arbitration on the generated result. The method specifically comprises the following steps: (1) the power supply is in charge of circulating control operation and is used for fixing work after power is on; (2) and (5) final judgment: the digital main control circuit compares the received continuous triggering times of the corresponding keys output by the judgment of the comparison judger with the set numerical value of the OTP, and if the effective continuous triggering times of the keys reach the configuration times read out from the OTP, the keys are judged to be triggered; if the corresponding times are not reached, the trigger is judged to be false trigger or interference, and no response is made. When a key is judged to be triggered, the INT signal is pulled high to inform an upper computer to read the information of the trigger key, and when a reading command is issued by the upper computer through I2C, the information of the trigger key is uploaded to the upper computer.
To sum up, the utility model has the advantages of it is following:
1. in the system detection process, an ADC (analog to digital converter) is not required to participate in conversion detection, so that the power consumption of the system is obviously reduced;
2. the system does not need to set a fixed threshold value, but does a threshold value environment self-adaptive algorithm, and writes the required threshold value into a one-time programming memory according to the algorithm;
3. when the environment changes slowly, the difference result output by the subtracter is not influenced by the environment change, and when the difference result is compared with the threshold of the comparison decision device, the threshold is taken as a judgment standard and does not need to be changed, so that the judgment threshold of the system is accurate and does not drift;
4. the output of the subtracter of the system is a relative difference value, when the environment changes slowly, the change of the output result of the comparison decision device can be ignored, and the system can automatically adapt to the environment change;
5. when the system is delivered to a client, the client can directly use the system only after simple OTP programming, secondary development is not needed, and the use is convenient.
It should be understood that the above detailed description of the present invention is only for illustrative purposes and is not limited to the technical solutions described in the embodiments of the present invention. It will be understood by those skilled in the art that the present invention may be modified and equivalents may be substituted to achieve the same technical effects; as long as the use requirement is satisfied, the utility model is within the protection scope.
Claims (7)
1. The utility model provides an environmental slowly change self-adaptation electric capacity response detecting system which characterized in that: comprises an analog system and a digital system;
the analog system comprises a gating circuit and an analog processing circuit;
the digital system comprises a counter, a shift data difference subtracter, a comparison decision device, a one-time programming memory, a data latch and a digital master control circuit;
the analog processing circuit provides reference current and reference voltage for the whole system, provides a reset signal for the digital system, provides a clock signal for the counter, the clock signal is matched with the frequency of the touch key signal, receives the touch key signal accessed by the gating circuit, converts the touch key signal into a pulse signal and outputs the pulse signal to the counter;
the counter counts the number of the received pulse signals within the matched clock signal length, the counted value is recorded as a conversion pulse value and is sent to the shift data difference value subtracter, and the clock signal lengths matched with different touch key signals are different;
the shift data difference subtracter divides the received conversion pulse value, stores the divided value into a shift register corresponding to the touch key signal, performs subtraction operation on the value and a certain subtraction number to generate a difference result, and sends the difference result to a comparison decision device, wherein the certain subtraction number in the subtraction operation is selected from the stored values in the shift register;
the comparison decision device receives the difference result, selects a preset threshold value matched with the touch key signal for comparison, and generates a decision result to be sent to the digital main control circuit;
the digital main control circuit is responsible for controlling the operation of the whole system, the data latch is used for controlling the gating circuit to gate the N touch keys, the data latch is used for controlling the analog processing circuit to output a clock signal matched with the frequency of the touch key signal, the length of the clock signal matched with the counter is controlled, the selection and the subtraction selection of a shift register of the shift data difference subtracter are controlled, the selection of a preset threshold value of the comparison decision device is controlled, the decision result output by the comparison decision device is received and compared with the continuous trigger condition corresponding to the touch keys, and the key trigger result is output to the upper computer;
the one-time programming memory is used for writing the clock signal frequency, the decrement selection condition, the clock signal length selection condition, the preset threshold information and the touch key continuous triggering condition required by the system and providing the clock signal frequency, the decrement selection condition, the clock signal length selection condition, the preset threshold information and the touch key continuous triggering condition to the digital main control circuit.
2. The environmentally graded adaptive capacitance sensing detection system according to claim 1, wherein:
the gating circuit comprises a switch decoding circuit and N communicating switches, and the analog processing circuit comprises a capacitance pulse conversion circuit, a clock circuit, a reference voltage circuit, a reference current circuit and a reset circuit;
n input ends of the switch decoding circuit are respectively connected with N touch keys through N communicating switches, and an output end of the switch decoding circuit is connected with the digital main control circuit through a data latch;
the input end of the capacitance pulse conversion circuit receives N touch key signals in a time-sharing manner, and the output end of the capacitance pulse conversion circuit is connected with the input end of the counter;
the reference current circuit provides reference currents for the capacitance pulse conversion circuit, the clock circuit, the reference voltage circuit and the reset circuit respectively;
the reference voltage circuit provides reference voltage for the reset circuit;
the clock circuit receives the control signal from the digital main control circuit and outputs a clock signal to the counter;
the reset circuit provides a reset signal for the digital system.
3. The environmentally graded adaptive capacitance sensing detection system according to claim 2, wherein:
the capacitance pulse conversion circuit comprises a first current source Idcp, a second current source Idcn, a switch SW0, a switch SW1, an inverter Inv1, an inverter Inv2 and a buffer Buf 1;
one end of the switch SW0 and one end of the switch SW1 are connected with the input end of the inverter Inv1 to serve as the input end of the capacitance pulse conversion circuit;
the output end of the inverter Inv1 is connected to the input end of the inverter Inv 2;
the output end of the inverter Inv2 is connected to the input end of the buffer Buf 1;
the output end of the Buf1 buffer is used as the output end of the capacitance pulse conversion circuit;
one end of the current source Idcp is used as a VDD end, and the other end is respectively connected with the other end of the switch SW0
One terminal of the current source Idcn serves as a ground, and the other terminal is connected to the other terminal of the switch SW 1.
4. The environmentally graded adaptive capacitance sensing detection system according to claim 3, wherein: the clock circuit comprises a switch SW10, a switch SW11, an inverter Inv3, an inverter Inv4, a buffer Buf2 and a gating capacitor bank;
the gating capacitor group comprises M +1 capacitors and M +1 switches, each capacitor is matched with one switch, one end of each of the M +1 capacitors is grounded, and the other end of each capacitor is connected with one end of the switch SW10, one end of the switch SW11 and the input end of the inverter Inv3 after passing through the matched switches;
the output end of the inverter Inv3 is connected to the input end of the inverter Inv 4;
the output end of the inverter Inv4 is connected to the input end of the buffer Buf 2;
the output end of the Buf2 buffer is used as the output end of the clock circuit;
the other end of the switch SW10 is connected with a VDD end;
the other end of the switch SW11 is grounded.
5. The environmentally graded adaptive capacitance sensing detection system according to claim 4, wherein: the shift data difference subtracter comprises a data storage selector, N shift registers and N subtracters, wherein the input end of the data storage selector is connected with the output end of a counter, an enabling end is connected with a digital main control circuit, N output ends are respectively connected with the input ends of the N shift registers, the output ends of the N shift registers are respectively connected with the input ends of the N subtracters, and the output ends of the N subtracters are connected with the input end of a comparison decision device.
6. The environmentally graded adaptive capacitance sensing detection system according to claim 5, wherein: each shift register is composed of M registers connected step by step, the output end of the 1 st register is connected with the input end of a subtracter corresponding to the shift register, the input end of the 1 st register is connected with the output end of the 2 nd register, the input end of the 2 nd register is connected with the output end of the 3 rd register, and so on, the input end of the M-1 st register is connected with the output end of the M-th register, the input end of the M-th register is connected with the output end of a data storage selector, the subtracted number of the subtracter in subtraction operation is from the 1 st register, and the subtracted number is from any one of the M registers.
7. The environmentally graded adaptive capacitance sensing detection system according to claim 6, wherein: the comparison decision device comprises a decision device and a threshold value register, wherein the input end of the decision device is connected with the output ends of the N subtractors, the threshold value register stores N preset threshold values which are respectively matched with the N touch key signals, and the N preset threshold values are provided for the decision device.
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| CN202021807737.1U CN212305298U (en) | 2020-08-26 | 2020-08-26 | Environment slowly-varying self-adaptive capacitance induction detection system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113489497A (en) * | 2021-06-21 | 2021-10-08 | 苏州聚元微电子股份有限公司 | Realization circuit and chip for TCK or ADC |
| CN114124066A (en) * | 2020-08-26 | 2022-03-01 | 浙江智识电子科技有限公司 | Environment slowly-varying self-adaptive capacitance induction detection system |
| CN114217705A (en) * | 2021-11-09 | 2022-03-22 | 深圳市芯生半导体有限公司 | Touch detection circuit and detection method |
| CN114124066B (en) * | 2020-08-26 | 2024-07-02 | 浙江智识电子科技有限公司 | Environment slowly-changing self-adaptive capacitance induction detection system |
-
2020
- 2020-08-26 CN CN202021807737.1U patent/CN212305298U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114124066A (en) * | 2020-08-26 | 2022-03-01 | 浙江智识电子科技有限公司 | Environment slowly-varying self-adaptive capacitance induction detection system |
| CN114124066B (en) * | 2020-08-26 | 2024-07-02 | 浙江智识电子科技有限公司 | Environment slowly-changing self-adaptive capacitance induction detection system |
| CN113489497A (en) * | 2021-06-21 | 2021-10-08 | 苏州聚元微电子股份有限公司 | Realization circuit and chip for TCK or ADC |
| CN113489497B (en) * | 2021-06-21 | 2024-04-26 | 苏州聚元微电子股份有限公司 | Implementation circuit and chip for TKC or ADC |
| CN114217705A (en) * | 2021-11-09 | 2022-03-22 | 深圳市芯生半导体有限公司 | Touch detection circuit and detection method |
| CN114217705B (en) * | 2021-11-09 | 2024-05-24 | 深圳市芯生半导体有限公司 | Touch detection circuit and detection method |
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