CN114122105A - Trench gate IGBT device - Google Patents

Trench gate IGBT device Download PDF

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Publication number
CN114122105A
CN114122105A CN202010879830.1A CN202010879830A CN114122105A CN 114122105 A CN114122105 A CN 114122105A CN 202010879830 A CN202010879830 A CN 202010879830A CN 114122105 A CN114122105 A CN 114122105A
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Prior art keywords
well region
trench gate
region
deep
igbt device
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CN202010879830.1A
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CN114122105B (en
Inventor
朱利恒
肖强
覃荣震
罗海辉
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Zhuzhou CRRC Times Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

The invention discloses a trench gate IGBT device, which comprises an anode region, a buffer region, a drift region, an N well region and a P well region which are sequentially arranged from bottom to top, a trench gate which penetrates through the N well region and the P well region from top to bottom and extends into the drift region, and a deep P well region which is arranged at the top of the drift region and is connected with the N well region. The deep P well region connected with the N well region is arranged in the drift region of the IGBT device, and the deep P well region is located in the non-channel region of the trench gate IGBT, so that the electric field peak value at the bottom of the trench gate oxide layer can be transferred to the deep P well region, the avalanche breakdown point is far away from a parasitic thyristor current path, the safe working region of the trench gate IGBT is further improved, the performance of the IGBT device is improved, and the structure is simple.

Description

Trench gate IGBT device
Technical Field
The invention relates to the field of IGBT devices, in particular to a trench gate IGBT device.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device consisting of a Bipolar Junction Transistor (BJT) and an insulated Gate field effect transistor (MOS), and has the advantages of high input impedance of the MOSFET and low conduction voltage drop of the GTR. The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is large; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current carrying density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. The method is very suitable for being applied to the fields of current transformation systems with direct-current voltage of 600V or more, such as alternating-current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like.
The electric field concentration in the drift region during the switching process of an Insulated Gate Bipolar Transistor (IGBT) is easily modulated by high-concentration carriers, so dynamic avalanche is easily generated at a high off-current density, and extra hole and electron currents are generated, so that the RBSOA (reverse bias safe operating area) capability of the IGBT is reduced, and particularly under the condition of high DC voltage, the situation is easily worsened. Particularly, in the trench gate IGBT, since the trench gate is deep into the drift region, the peak value of the electric field at the bottom of the trench gate is high, so that dynamic avalanche tends to occur at the position first, making the high-voltage IGBT highly susceptible to dynamic avalanche and thus causing weak safe operation capability.
To improve the SOA for safe operation of Insulated Gate Bipolar Transistors (IGBTs), increasing their latch-up resistance, a deep, highly doped p + base region is typically introduced at their cathode. The deep p + base region mainly functions as: first, holes are efficiently collected during turn-off, reducing the number of holes entering the cathode via the IGBT channel region, preventing early parasitic thyristor latch-up; and the P + base region is laterally extended, so that the resistance of the P base region under the n + source region is reduced, and the latch-up effect of a parasitic thyristor is reduced.
In the prior art, the hole current flowing out of the cathode of the IGBT can be increased mainly by increasing the P + region, so that the latch-up resistance of the IGBT is enhanced, and the safe working region of the IGBT is further enhanced. However, increasing the P + region also actually impairs the IGBT cathode electron injection capability, obviously leading to an increase in IGBT turn-on voltage drop.
Disclosure of Invention
The invention provides a trench gate IGBT device, which improves the safe working area of the trench gate IGBT.
In order to solve the technical problem, the invention provides a trench gate IGBT device which comprises an anode region, a buffer region, a drift region, an N well region, a P well region, a trench gate and a deep P well region, wherein the anode region, the buffer region, the drift region, the N well region and the P well region are sequentially arranged from bottom to top, the trench gate penetrates through the N well region and the P well region from top to bottom and extends into the drift region, and the deep P well region is arranged at the top of the drift region and connected with the N well region.
And the junction depth of the deep P well region is greater than that of the trench gate.
And the difference value between the junction depth of the deep P well region and the junction depth of the trench gate is 7-8 um.
Wherein the depth of the deep P well region and the junction is greater than or equal to the junction width.
Wherein, the longitudinal section of the deep P well region is semi-elliptical or trapezoidal.
And the lateral distance between the deep P well region and the two adjacent trench gates is equal.
The anode region is formed by transversely and alternately arranging an N + contact partition and a P-type contact partition.
The doping concentration of the N + contact subarea is 1e19 cm-3-1 e21 cm-3.
The plurality of deep P well regions are arranged at intervals along the transverse extending direction of the trench gate.
The trench gate structure further comprises a dummy gate deep P well region which is arranged in the drift region, surrounds the bottom of the dummy gate of the trench gate and is connected with the N well region at the top.
Compared with the prior art, the trench gate IGBT device provided by the embodiment of the invention has the following beneficial effects:
the trench gate IGBT device is provided with the deep P well region connected with the N well region in the drift region, and the deep P well region is located in the non-channel region of the trench gate IGBT, so that the electric field peak value at the bottom of the gate oxide layer of the trench gate can be transferred to the deep P well region, an avalanche breakdown point is far away from a parasitic thyristor current path, the safe working region of the trench gate IGBT is further improved, the performance of the IGBT device is improved, the structure is simple, and the cost is increased less.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an embodiment of a trench gate IGBT device provided herein;
fig. 2 is a schematic structural diagram of another embodiment of a trench gate IGBT device provided herein;
fig. 3 is a schematic top view structural diagram of a trench gate IGBT device according to yet another embodiment provided in the present application;
fig. 4 is a schematic structural diagram of another embodiment of a trench gate IGBT device provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 to 4, fig. 1 is a schematic structural diagram of an embodiment of a trench gate IGBT device provided in the present application; fig. 2 is a schematic structural diagram of another embodiment of a trench gate IGBT device provided herein; fig. 3 is a schematic top view structural diagram of a trench gate IGBT device according to yet another embodiment provided in the present application; fig. 4 is a schematic structural diagram of another embodiment of a trench gate IGBT device provided in the present application.
In a specific embodiment, the trench gate IGBT device provided by the present invention includes an anode region 10, a buffer region 20, a drift region 30, an N-well region 40, and a P-well region 50, which are sequentially arranged from bottom to top, and further includes a trench gate 60 penetrating through the N-well region 40 and the P-well region 50 from top to bottom and extending into the drift region 30, and a deep P-well region 70 disposed on the top of the drift region 30 and connected to the N-well region 40.
The deep P well region 70 connected with the N well region 40 is arranged in the drift region 30 of the IGBT device, and the deep P well region 70 is located in the non-channel region of the trench gate 60IGBT, so that the electric field peak value at the bottom of the oxidation layer of the trench gate 60 can be transferred to the deep P well region 70, an avalanche breakdown point is far away from a parasitic thyristor current path, the safe working area of the trench gate 60IGBT is further improved, the performance of the IGBT device is improved, the structure is simple, and the increase cost is low.
According to the invention, a deep P well region 70 structure is introduced into a non-channel region of the trench gate 60IGBT, and the electric field peak value at the bottom of the oxidation layer of the trench gate 60 is transferred to the bottom of the deep P well region 70 structure by means of the deeper junction depth and the smaller curvature radius, so that an avalanche breakdown point is far away from a parasitic thyristor current path, and the safe working region of the trench gate 60IGBT is further improved.
In order to further improve the effect of raising the safe operating area of the trench gate 60IGBT, the junction depth of the deep P well region 70 is generally greater than the junction depth of the trench gate 60.
The junction depth of the deep P well region 70 and the junction depth of the trench gate 60 are not limited in the present invention, and can be set according to different sizes and functions of IGBT devices, and generally, the difference between the junction depth of the deep P well region 70 and the junction depth of the trench gate 60 is 7um to 8 um.
In order to reduce the influence on the normal conduction of the device, generally, the depth of the deep P-well region 70 and the junction depth is greater than or equal to the junction width, that is, the formed deep P-well region 70 is a vertically oblong structure, the specific shape and size of the deep P-well region are not limited in the present invention, and the longitudinal section of the deep P-well region 70 may be a semi-ellipse, a trapezoid, or other shapes.
Since the IGBT device is manufactured in a large scale in the process flow, and the number of gates in a single IGBT device is also multiple, in order to reduce the process difficulty and improve the device performance, the lateral distance between the deep P well region 70 and the two adjacent trench gates 60 is generally equal.
If the lateral spacing between the deep P well region 70 and the two adjacent trench gates 60 is not equal, it is necessarily biased toward one of them, and if the structure is designed, it is easy to fuse the deep P well region 70 and the adjacent gates, even if no fusion occurs, the electric field distribution difference between the two sides of the deep P well region 70 will be large, the current distribution uniformity will be poor, the maximum current will be small, and some other negative effects will be caused.
Furthermore, in order to improve the performance of the device, in one embodiment, the anode region 10 is preferably an anode region 10 in which N + contact partitions 21 and P-type contact partitions 22 are laterally arranged alternately, and the doping concentration of the N + contact partitions is 1e19cm-3 to 1e21 cm-3.
The invention does not limit the transverse size of the N + contact subarea 21 and the P-type contact subarea 22, does not limit the junction depth of the N + contact subarea and the P-type contact subarea, can integrate a diode which is connected in anti-parallel into an IGBT cell to form a novel reverse conducting type IGBT, and can set the transverse size of the N + contact subarea and the P-type contact subarea according to the performance requirement of a device, preferably, the junction depths of the N + contact subarea and the P-type contact subarea are equal.
The doping concentration and doping method of the N + contact partition 21 are not limited in the present invention.
In the present invention, since the junction depth of the floating deep P-well region 70 is deep and the curvature radius is small, the electric field peak will be concentrated at the bottom of the floating deep P-well region 70 during the reverse blocking or switching process of the IGBT, and by this means, the electric field peak at the bottom of the N-well and the trench can be reduced, so that the avalanche breakdown point is transferred from the bottom of the trench to the lower side of the floating deep P-well region 70. Therefore, when the IGBT generates dynamic avalanche, holes generated by avalanche flow out through the cathode metal near the floating P region and are far away from the parasitic thyristor, so that the dynamic avalanche resistance of the IGBT is improved; in practice this structure causes the IGBT cell region breakdown voltage to be slightly reduced by introducing the floating deep P-well region 70, thereby transferring the breakdown point from the bottom of the trench to the bottom of the floating deep P-well region 70.
Furthermore, in order to further optimize the structure and further stably control the breakdown voltage of the floating deep P-well region 70, in one embodiment, a plurality of the deep P-well regions 70 are periodically spaced along the lateral extension direction of the trench gate 60.
Through carrying out periodic discontinuity setting to floating deep P well region 70 in the slot extending direction for deep P well region 70 becomes cylindrical knot with the spherical knot that adds both ends by the cylindrical knot of continuous type with the PN junction of N drift region 30, because spherical knot curvature radius is littleer, thereby make the breakdown voltage of floating P well region 50 when reducing, control more easily, through adjusting the interval between two floating P well regions 50, can conveniently adjust this IGBT cellular breakdown voltage. As described above, the floating deep P-well region 70 protects the trench bottom oxide layer when its breakdown voltage is slightly lower than the trench bottom breakdown voltage.
The floating deep P well region 70 is not limited to be periodically spaced along the lateral extension direction of the trench gate 60, but is generally disposed at equal intervals, and the intervals are set according to the performance requirements of the working personnel on the device.
In the trench gate 60IGBT, the trench gate 60 may be divided into two types, one is an actual gate (true gate) that controls generation and disappearance of an electron channel; the other is a dummy gate (dummy gate) which can be floating or grounded and does not directly participate in electron channel generation and extinction.
In order to further improve the performance of the device, in order to reduce the probability of dynamic avalanche at the bottom of the trench gate 60, floating P-type regions are added at the bottoms of all dummy gates in the IGBT body of the trench gate 60, and the floating P-type regions are not arranged at the bottoms of the true gates, so as to prevent an electron channel from being pinched off by the floating P-type regions. That is, in one embodiment, the trench gate 60IGBT device further includes a dummy gate deep P-well region 80 disposed in the drift region 30, surrounding the dummy gate bottom of the trench gate 60, and having a top connected to the N-well region 40.
By the method, on one hand, the bottom oxide layer of the dummy gate is well protected by the medium-sized P region, and avalanche breakdown cannot occur; on the other hand, by reasonably controlling the distance d between the dummy gate and the real gate, the electric field peak value at the bottom of the oxidation layer of the real gate can be reduced through the floating P-type area, so that when the IGBT is in a blocking state or a switching state, an avalanche breakdown point is transferred from the bottom of the real gate to the bottom of the floating P-type area, the danger of latch locking of the IGBT due to dynamic avalanche is further reduced, and the safety working area of the IGBT is improved.
In summary, in the trench gate IGBT device provided in the embodiments of the present invention, the deep P well region connected to the N well region is disposed in the drift region of the IGBT device, and since the deep P well region is located in the trench gate IGBT non-channel region, the peak value of the electric field at the bottom of the trench gate oxide layer can be transferred to the deep P well region, so that the avalanche breakdown point is far away from the current path of the parasitic thyristor, thereby improving the safe working region of the trench gate IGBT, improving the performance of the IGBT device, and having a simple structure and a low cost increase.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. The utility model provides a trench gate IGBT device, its characterized in that includes positive pole district, buffer area, drift region, N well region and the P well region that from the bottom up set gradually, still includes from the top down and runs through N well region and P well region just stretch into the trench gate and the setting in drift region are in drift region top with the dark P well region that N well region is connected.
2. The trench gate IGBT device of claim 1, wherein the deep P-well region has a junction depth greater than a junction depth of the trench gate.
3. The trench gate IGBT device of claim 2, wherein the junction depth of the deep P-well region differs from the junction depth of the trench gate by between 7um and 8 um.
4. The trench gate IGBT device of claim 3, wherein the deep P-well region and the junction depth are greater than or equal to a junction width.
5. The trench gate IGBT device of claim 4, wherein the deep P-well region has a semi-elliptical or trapezoidal longitudinal cross-section.
6. The trench gate IGBT device of claim 5, wherein the deep P-well region has equal lateral spacing from two adjacent trench gates.
7. The trench gate IGBT device of claim 6, wherein the anode regions are anode regions with N + contact partitions alternating with P-type contact partitions laterally.
8. The trench gate IGBT device of claim 7, wherein the doping concentration of the N + contact partition is 1e19 cm-3-1 e21 cm-3.
9. The trench gate IGBT device of claim 8, wherein a plurality of the deep P-well regions are periodically spaced along a lateral extension direction of the trench gate.
10. The trench gate IGBT device of claim 9, further comprising a dummy gate deep P-well region disposed in the drift region, surrounding a bottom portion of the dummy gate of the trench gate, and connected to the N-well region at a top portion thereof.
CN202010879830.1A 2020-08-27 2020-08-27 Trench gate IGBT device Active CN114122105B (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101964361A (en) * 2009-07-24 2011-02-02 新唐科技股份有限公司 Metal oxide semiconductor transistor and manufacturing method thereof
US20120104555A1 (en) * 2010-10-31 2012-05-03 Alpha And Omega Semiconductor Incorporated Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances
US20140264433A1 (en) * 2013-03-14 2014-09-18 Jun Hu Dual-gate trench igbt with buried floating p-type shield
CN105789269A (en) * 2016-03-04 2016-07-20 上海源翌吉电子科技有限公司 Trench insulated gate bipolar transistor and preparation method therefor
CN107359201A (en) * 2017-08-31 2017-11-17 上海华虹宏力半导体制造有限公司 Groove grid super node MOSFET
WO2018034818A1 (en) * 2016-08-18 2018-02-22 Maxpower Semiconductor Inc. Power mosfet having planar channel, vertical current path, and top drain electrode

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101964361A (en) * 2009-07-24 2011-02-02 新唐科技股份有限公司 Metal oxide semiconductor transistor and manufacturing method thereof
US20120104555A1 (en) * 2010-10-31 2012-05-03 Alpha And Omega Semiconductor Incorporated Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances
US20140264433A1 (en) * 2013-03-14 2014-09-18 Jun Hu Dual-gate trench igbt with buried floating p-type shield
CN105789269A (en) * 2016-03-04 2016-07-20 上海源翌吉电子科技有限公司 Trench insulated gate bipolar transistor and preparation method therefor
WO2018034818A1 (en) * 2016-08-18 2018-02-22 Maxpower Semiconductor Inc. Power mosfet having planar channel, vertical current path, and top drain electrode
CN107359201A (en) * 2017-08-31 2017-11-17 上海华虹宏力半导体制造有限公司 Groove grid super node MOSFET

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