CN114122007A - Array substrate - Google Patents
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- CN114122007A CN114122007A CN202111281984.1A CN202111281984A CN114122007A CN 114122007 A CN114122007 A CN 114122007A CN 202111281984 A CN202111281984 A CN 202111281984A CN 114122007 A CN114122007 A CN 114122007A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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Abstract
The embodiment of the application provides an array substrate, which comprises a first TFT device and a second TFT device, wherein the first TFT device at least comprises a first grid electrode, a first source electrode and a first drain electrode, the second TFT device at least comprises a second grid electrode, a second source electrode and a second drain electrode, and at least one of the first grid electrode, the first source electrode and the first drain electrode and at least one of the second grid electrode, the second source electrode and the second drain electrode are arranged in the same layer; the film layers between different TFT devices are arranged on the same layer, so that at least one photomask can be reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate.
Background
In the LTPO technology, the first gate and the first source/drain of the low-temperature polysilicon TFT device are separately manufactured, and the second gate and the second source/drain of the oxide TFT device are also separately manufactured, so that the number of the whole photo-masks is large, and the whole manufacturing cost is relatively high.
Therefore, the existing array substrate has the technical problems of more light shades and higher cost caused by the independent preparation of the grid electrode and the source/drain electrode of different TFT devices.
Disclosure of Invention
The embodiment of the application provides an array substrate, which can solve the technical problems of more light shades and higher cost caused by independent preparation of grid electrodes and source/drain electrodes of different TFT devices in the conventional array substrate.
An embodiment of the present application provides an array substrate, including:
the first TFT device at least comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, and the first TFT device is a driving transistor;
a second TFT device including at least a second active layer, a second gate, a second source, and a second drain, the second TFT device being a switching transistor;
wherein at least one of the first gate, the first source, and the first drain is disposed in the same layer as at least another one of the second gate, the second source, and the second drain.
Optionally, in some embodiments of the present application, the first TFT device is a low temperature polysilicon TFT device, and the second TFT device is an oxide TFT device.
Optionally, in some embodiments of the present application, the first source, the first drain, the second source, and the second drain are disposed on the same layer.
Optionally, in some embodiments of the present application, the first gate, the first source, the first drain, the second gate, the second source, and the second drain are disposed in the same layer.
Optionally, in some embodiments of the present application, the low temperature polysilicon TFT device further includes a first electrode disposed corresponding to the first gate, the oxide TFT device further includes a second electrode disposed corresponding to the second gate, the first electrode and the first gate are disposed on different film layers to form a first capacitor, and the second electrode and the second gate are disposed on different film layers to form a second capacitor.
Optionally, in some embodiments of the present application, the second electrode is disposed below the second active layer, and a material of the second electrode is a light shielding material.
Optionally, in some embodiments of the present application, the first gate and the second gate are disposed at the same layer, and the first electrode and the second electrode are disposed at the same layer.
Optionally, in some embodiments of the present application, the low temperature polysilicon TFT device is a top gate structure, the oxide TFT device is a top gate structure, the first gate is disposed above the first active layer, the second gate is disposed above the second active layer, wherein the first gate and the second electrode are disposed on the same layer, and the first electrode and the second gate are disposed on the same layer.
Optionally, in some embodiments of the present application, the low temperature polysilicon TFT device is a top gate structure, the oxide TFT device is a bottom gate structure, the first gate is disposed above the first active layer, and the second gate is disposed below the second active layer, where the first gate and the second electrode are disposed on the same layer, and the first electrode and the second gate are disposed on the same layer.
Optionally, in some embodiments of the present application, a material of the first source, the first drain, the second source, the second drain, the first gate, the second gate, the first electrode, and the second electrode is at least one of molybdenum, titanium, aluminum, copper, silver, and an alloy.
The array substrate provided by the embodiment of the application comprises a first TFT device and a second TFT device, wherein the first TFT device at least comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, the first TFT device is a driving transistor, the second TFT device at least comprises a second active layer, a second grid electrode, a second source electrode and a second drain electrode, the second TFT device is a switching transistor, and at least one of the first grid electrode, the first source electrode and the first drain electrode and at least one of the second grid electrode, the second source electrode and the second drain electrode are arranged in the same layer; the application can reduce at least one light shield by arranging the film layers between different TFT devices at the same layer, and has wider application in display panels with two different TFT devices, such as an LTPO display panel and the like.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a first schematic cross-sectional view of an array substrate provided in the present application;
FIG. 2 is a second schematic cross-sectional view of an array substrate provided herein;
FIG. 3 is a third schematic cross-sectional view of an array substrate provided herein;
fig. 4a to 4f are schematic structural views illustrating a method for manufacturing the array substrate provided in fig. 2 of the present application.
Description of reference numerals:
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
Referring to fig. 1 to 3 and 4a to 4f, the present application provides an array substrate including a first TFT device 10 and a second TFT device 20, where the first TFT device 10 at least includes a first active layer 601, a first gate 101, a first source 401 and a first drain 402, the first TFT device 10 is a driving transistor, the second TFT device 20 at least includes a second active layer 602, a second gate 201, a second source 501 and a second drain 502, the second TFT device 20 is a switching transistor, and at least one of the first gate 101, the first source 401 and the first drain 402 and at least one of the second gate 201, the second source 501 and the second drain 502 are disposed in the same layer.
In this embodiment, the film layers between different TFT devices are arranged on the same layer, so that at least one photomask can be reduced, and the method can be widely applied to display panels with two different TFT devices, such as LTPO display panels.
In the LTPO display panel, the first TFT device 10 is a driving transistor, the first TFT device 10 is a low-temperature polysilicon TFT device, the second TFT device 20 is a switching transistor, and the second TFT device 20 is an oxide TFT device.
The technical solution of the present application will now be described with reference to specific embodiments.
The first TFT device 10 of the present application may be a top gate structure or a bottom gate structure, and similarly, the second TFT device 20 may also be a top gate structure or a bottom gate structure.
Meanwhile, the first TFT device 10 of the present application may have a single-gate structure or a dual-gate structure, and the second TFT device 20 may also have a single-gate structure or a dual-gate structure.
The array substrate further includes a substrate 70, a light shielding layer 80 located above the substrate 70, a buffer layer 90, a first gate insulating layer 100, an interlayer insulating layer 110, a second gate insulating layer 120, and a flat layer 130.
It is understood that the first gate insulating layer 100 is used to insulate the first active layer 601 from a first metal layer, and the second gate insulating layer 120 is used to insulate the second active layer 602 from a second metal layer; the first metal layer may include the first gate 101/the first electrode 102, and the second gate 201/the second electrode 202, and the second metal layer may include the first electrode 102/the first gate 101, and the second electrode 202/the second gate 201, and the source drain layer.
When determining the structure types of the first TFT device 10 and the second TFT device 20, there are various technical solutions for layer arrangement, which will be described below by way of example;
referring to fig. 1 to fig. 2, in an embodiment, the first TFT device 10 is a low temperature polysilicon TFT device, and the second TFT device 20 is an oxide TFT device; the low-temperature polysilicon has high carrier migration rate and can be used as a driving transistor, and the oxide TFT device has small leakage current and can be used as a switching transistor.
It is understood that, in an embodiment, when the second TFT device 20 has a double-gate structure, the second TFT device 20 includes the second gate 201/second electrode 202 under the second active layer 602, and the second gate 201/second electrode 202 may be made of a light-shielding material to block ambient light from the lower side from affecting the active layer.
In one embodiment, the first source 401, the first drain 402, the second source 501, and the second drain 502 are disposed on the same layer.
The first gate 101, the first source 401, the first drain 402, the second gate 201, the second source 501, and the second drain 502 are disposed in the same layer.
In the embodiment, the first gate 101 and the second gate 201 are separately fabricated, and the first source 401/the first drain 402 and the second source 501/the second drain 502 are also separately fabricated, which saves two masks compared to the prior art.
It should be noted that the two saving masks include: a photomask for preparing the first gate 101 and a photomask for preparing the second gate 201 are also saved, and the first gate 101, the second gate 201 and the source drain layer (including the first source 401, the first drain 402, the second source 501 and the second drain 502) are directly arranged in the same layer.
Referring to fig. 2, in an embodiment, the array substrate provided by the present application includes a TFT device region Z2 and a capacitor region Z1, when the first TFT device 10 and the second TFT device 20 are of a dual-gate structure, the capacitor region Z1 is provided with a third capacitor 30, the third capacitor 30 includes an upper plate 301 and a lower plate 302, and a third electrode 303 is further provided on a side of the lower plate 302 away from the upper plate 301.
The first TFT device 10 is a low-temperature polysilicon TFT device, the first TFT device 10 is an oxide TFT device, the low-temperature polysilicon TFT device further includes a first electrode 102 disposed corresponding to the first gate 101, the oxide TFT device further includes a second electrode 202 disposed corresponding to the second gate 201, the first electrode 102 and the first gate 101 are located in different film layers to form a first capacitor, and the second electrode 202 and the second gate 201 are located in different film layers to form a second capacitor.
The second electrode 202 is disposed below the second active layer 602, and the second electrode 202 is made of a light-shielding material.
The first gate 101 and the second gate 201 are disposed at the same layer, and the first electrode 102 and the second electrode 202 are disposed at the same layer.
Further, the first gate 101, the second gate 201, the first source 401, the first drain 402, the second source 501, and the second drain 502 are disposed in the same layer.
Further, the first electrode 102 and the second electrode 202 are disposed in the same layer, and are also disposed in the same layer as the third electrode 303.
It should be noted that the source/drain layer includes a first source 401, a first drain 402, a second source 501, and a second drain 502, the lower plate 302 and the second active layer 602 are disposed in the same layer, and the upper plate 301 and the source/drain layer are disposed in the same layer; when the upper plate 301 is connected in parallel with the third electrode 303, the facing area of the upper plate 301 and the lower plate 302 is increased, so that the capacitance value is increased.
Referring to fig. 3, in an embodiment, the array substrate provided in the present application includes a TFT device region Z2 and a capacitor region Z1, and when the first TFT device 10 and the second TFT device 20 are in a dual-gate structure, the first electrode 102, the second electrode 202, the source drain layer, and the upper electrode plate are disposed in the same layer.
In this embodiment, the first TFT device 10 has a top gate structure, the second TFT device 20 has a bottom gate structure, the first gate 101 is disposed below the first active layer 601, the first electrode 102 is disposed on a side of the first gate 101 away from the first active layer 601, and the second electrode 202 is disposed above the second active layer 602.
It is understood that the second gate electrode 201 is disposed under the second active layer 602, and the material for preparing the second gate electrode 201 may be a light shielding material to prevent ambient light from the substrate 70 side from affecting the performance of the second TFT device 20.
It should be noted that, in the present application, the first electrode 102, the second electrode 202 and the source/drain layer are disposed in the same layer, and meanwhile, the first gate 101 and the second gate 201 are also disposed in the same layer below the source/drain layer, which can also achieve the technical effect of reducing two photomasks.
It should be noted that, in the present embodiment, it is not limited that the first gate 101 and the second gate 201 are only at the same layer, and the first electrode 102 and the second electrode 202 are only at the same layer; other aspects are also included, and are not limited herein; examples further include: the first gate 101 and the second electrode 202 are in the same layer, and the first electrode 102 and the second gate 201 are in the same layer.
The first gate 101 and the first electrode 102 need to form a first capacitance in a direction perpendicular to the substrate 70, and the second gate 201 and the second electrode 202 need to form a first capacitance in a direction perpendicular to the substrate 70, so that the first gate 101, the first electrode 102, the second electrode 202, and the second gate 201 cannot be all disposed in the same layer, the first gate 101 and the first electrode 102 are disposed in different layers, and the second gate 201 and the second electrode 202 are disposed in different layers.
Referring to fig. 1 to fig. 3, in some embodiments, the low temperature polysilicon TFT device may also be a bottom gate structure, and the oxide TFT device is a bottom gate structure.
In this embodiment, the first electrode 102 is on the same layer as the second gate 201/the second electrode 202, the first gate 101 is on the same layer as the second electrode 202/the second gate 201, and the first source 401/the first drain 402 is on the same layer as the second source 501/the second drain 502.
In this embodiment, compared with the prior art, the present application saves a light shield, and the second electrode 202 and the second gate 201 are disposed below the second active layer 602, so that the blocking of the ambient light on one side of the substrate 70 is enhanced, and the oxide TFT device is prevented from being influenced by the ambient light to cause threshold shift, which causes abnormal display.
In one embodiment, the upper plate 301 is connected in parallel with the third electrode 303 in the third capacitor 30, which also can be used to form the third capacitor 30 with the lower plate 302 when one of the upper plate 301 or the third electrode 303 fails.
It is understood that similar schemes can be adopted for the gate trace, the source trace and the drain trace in the present application, for example, in one embodiment, the gate trace is configured to include at least two signal paths.
It can be understood that the two signal paths may be formed by connecting multiple layers of gate traces in parallel, or one gate trace includes a trunk portion and at least two trunk portions, and two ends of any one of the trunk portions are respectively connected to the trunk portion to implement signal conduction.
In some embodiments of the present application, a material of the first source 401, the first drain 402, the second source 501, the second drain 502, the first gate 101, the second gate 201, the first electrode 102, and the second electrode 202 is at least one of molybdenum, titanium, aluminum, copper, silver, and an alloy.
In this embodiment, the first source 401, the first drain 402, the second source 501, the second drain 502, the first gate 101, the second gate 201, the first electrode 102, and the second electrode 202 may all be made of the same material, and therefore, it can be understood that at least two of the first source 401, the first drain 402, the second source 501, the second drain 502, the first gate 101, the second gate 201, the first electrode 102, and the second electrode 202 are disposed in the same layer without affecting the display effect.
The present application further provides an LTPO display panel, including the array substrate, specifically, in the LTPO display panel, the low temperature polysilicon TFT device at least includes a first active layer 601, a first gate 101, a first source 401, and a first drain 402, the low temperature polysilicon TFT device is a driving transistor, the oxide TFT device at least includes a second active layer 602, a second gate 201, a second source 501, and a second drain 502, and the oxide TFT device is a switching transistor, wherein at least one of the first gate 101, the first source 401, and the first drain 402 is disposed in the same layer as at least another one of the second gate 201, the second source 501, and the second drain 502.
By sharing the grid electrode, the source electrode, the drain electrode and the like among different TFT devices in the LTPO display panel, the use of a photomask is further reduced, the cost is reduced, and meanwhile, the preparation process is simplified.
Referring to fig. 4a to 4f, an embodiment of the present invention further provides a method for manufacturing an array substrate, including:
s1: as shown in fig. 4a, providing a substrate 70, and preparing a light shielding layer 80 on the substrate 70;
s2: as shown in fig. 4b, a buffer layer 90 is formed on the substrate 70 and the light-shielding layer 80, and a first active layer 601 is formed on the buffer layer 90;
s3: as shown in fig. 4c, a first gate insulating layer 100 is prepared on the active layer, and a first metal layer is prepared on the first gate insulating layer 100;
s4: as shown in fig. 4d, an interlayer insulating layer 110 is formed on the first gate insulating layer 100 and the first metal layer, and a second active layer 602 is formed on the interlayer insulating layer 110;
s5: as shown in fig. 4e, a second gate insulating layer 120 is formed on the interlayer insulating layer 110 and the second active layer 602, and a second metal layer is formed on the second gate insulating layer 120;
s6: as shown in fig. 4f, a planarization layer 130 is prepared on the second gate insulating layer 120 and the second metal layer.
In step S1, the material for forming the light shielding layer 80 may be at least one of molybdenum, aluminum, copper, titanium or an alloy.
In step S2, the first active layer 601 is prepared from a-si, the buffer layer 90 is a silicon oxide film or a silicon nitride film or a multi-layer film, the thickness of the buffer layer 90 is in a range of 1000 angstroms to 5000 angstroms, and when the first active layer 601 is prepared, a layer of a-si is deposited, and laser thermal annealing is performed to form a polysilicon layer, followed by patterning, thereby obtaining the first active layer 601.
In step S3, the first metal layer includes a first gate 101 or a first electrode 102, and further includes a second gate 201 or a second electrode 202, the first gate 101 insulating layer is a silicon oxide film or a silicon nitride film or a multilayer film, and the thickness of the first gate 101 insulating layer is 1000 angstroms to 5000 angstroms.
In step S4, the material for preparing the interlayer insulating layer 110 is not limited to at least one of silicon nitride, silicon oxide, silicon oxynitride, and metal oxide; the preparation material of the second active layer 602 includes, but is not limited to, at least one of indium gallium zinc oxide, indium gallium tritium oxide, and indium gallium zinc tritium oxide.
In step S5, the material for preparing the second gate 201 insulating layer is not limited to at least one of silicon nitride, silicon oxide, silicon oxynitride, and metal oxide, the second gate 201 insulating layer is a silicon oxide film or a silicon nitride film or a multilayer film, and the thickness of the second gate 201 insulating layer ranges from 1000 angstroms to 5000 angstroms; performing an opening process to partially expose the first active layer 601 and the second active layer 602;
depositing a first material on the second gate 201 insulating layer by using physical vapor deposition, and patterning to obtain a second metal layer, wherein the second metal layer is made of a material including but not limited to molybdenum, aluminum, copper, titanium, silver or an alloy composition.
The application also provides a method for preparing the LTPO display panel, wherein after the steps from S1 to S6, the method for preparing the LTPO display panel comprises the method for preparing the array substrate.
The application provides an array substrate and a preparation method thereof, an LTPO display panel and a preparation method thereof, wherein the array substrate comprises a first TFT device and a second TFT device, the first TFT device at least comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, the first TFT device is a driving transistor, the second TFT device at least comprises a second active layer, a second grid electrode, a second source electrode and a second drain electrode, the second TFT device is a switching transistor, and at least one of the first grid electrode, the first source electrode and the first drain electrode and at least one of the second grid electrode, the second source electrode and the second drain electrode are arranged in the same layer; the film layers among different TFT devices are arranged on the same layer, and the film layers are prepared by sharing one photomask, so that at least one photomask can be reduced.
It should be noted that, in an embodiment, when the first gate, the first source, the first drain, the second gate, the second source, and the second drain are all disposed at the same layer, two masks may be reduced; in another embodiment, when the first electrode, the first source, the first drain, the second electrode, the second source, and the second drain are all disposed in the same layer, the technical effect of reducing two masks can be achieved.
The design is different from the design of sharing the same layer of the inner film layer of the TFT device, and the method is used for arranging part of the film layers between different TFT devices in the same layer in the same array substrate or display panel, so that the number of light shades used in the preparation process is reduced, and the preparation cost is greatly reduced; it is to be appreciated that in one embodiment, the inventive concepts of the present application may be used in an LTPO display panel.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing detailed description is directed to an array substrate provided in an embodiment of the present application, and specific examples are applied herein to illustrate the principles and embodiments of the present application, and the description of the foregoing embodiments is only used to help understand the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An array substrate, comprising:
the first TFT device at least comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, and the first TFT device is a driving transistor;
a second TFT device including at least a second active layer, a second gate, a second source, and a second drain, the second TFT device being a switching transistor;
wherein at least one of the first gate, the first source, and the first drain is disposed in the same layer as at least another one of the second gate, the second source, and the second drain.
2. The array substrate of claim 1, wherein the first TFT device is a low temperature polysilicon TFT device and the second TFT device is an oxide TFT device.
3. The array substrate of claim 2, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the same layer.
4. The array substrate of claim 3, wherein the first gate, the first source, the first drain, the second gate, the second source, and the second drain are disposed on a same layer.
5. The array substrate of claim 2, wherein the low temperature poly-Si TFT device further comprises a first electrode disposed corresponding to a first gate, the oxide TFT device further comprises a second electrode disposed corresponding to a second gate, the first electrode and the first gate being disposed in different layers to form a first capacitor, the second electrode and the second gate being disposed in different layers to form a second capacitor.
6. The array substrate of claim 5, wherein the second electrode is disposed under the second active layer, and the second electrode is made of a light-shielding material.
7. The array substrate of claim 5, wherein the first gate and the second gate are disposed on a same layer, and the first electrode and the second electrode are disposed on a same layer.
8. The array substrate of claim 5, wherein the low temperature poly-Si TFT device is a top gate structure, the oxide TFT device is a top gate structure, the first gate is disposed over the first active layer, the second gate is disposed over the second active layer, wherein the first gate and the second electrode are disposed at the same layer, and the first electrode and the second gate are disposed at the same layer.
9. The array substrate of claim 5, wherein the low temperature poly-Si TFT device is a top gate structure, the oxide TFT device is a bottom gate structure, the first gate is disposed above the first active layer, the second gate is disposed below the second active layer, and wherein the first gate and the second electrode are disposed on the same layer and the first electrode and the second gate are disposed on the same layer.
10. The array substrate of claim 1, wherein the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the first gate electrode, the second gate electrode, the first electrode, and the second electrode are made of at least one of molybdenum, titanium, aluminum, copper, silver, and an alloy.
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| CN104282769A (en) * | 2014-09-16 | 2015-01-14 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor, array substrate, manufacturing method of array substrate and display device |
| CN108231795A (en) * | 2018-01-02 | 2018-06-29 | 京东方科技集团股份有限公司 | Array substrate, production method, display panel and display device |
| CN109300915A (en) * | 2018-09-30 | 2019-02-01 | 厦门天马微电子有限公司 | A kind of array substrate, display panel and display device |
| CN111755464A (en) * | 2020-06-28 | 2020-10-09 | 合肥维信诺科技有限公司 | Array substrate and display panel |
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| CN108231795A (en) * | 2018-01-02 | 2018-06-29 | 京东方科技集团股份有限公司 | Array substrate, production method, display panel and display device |
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