CN114121888A - Fan-out type ultrathin packaging structure of chip and manufacturing method thereof - Google Patents

Fan-out type ultrathin packaging structure of chip and manufacturing method thereof Download PDF

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Publication number
CN114121888A
CN114121888A CN202111397923.1A CN202111397923A CN114121888A CN 114121888 A CN114121888 A CN 114121888A CN 202111397923 A CN202111397923 A CN 202111397923A CN 114121888 A CN114121888 A CN 114121888A
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Prior art keywords
chip
layer
carrier plate
insulating medium
fan
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马书英
刘苏
肖智轶
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Huatian Technology Kunshan Electronics Co Ltd
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Huatian Technology Kunshan Electronics Co Ltd
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Priority to CN202111397923.1A priority Critical patent/CN114121888A/en
Publication of CN114121888A publication Critical patent/CN114121888A/en
Priority to PCT/CN2022/116554 priority patent/WO2023087847A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a fan-out ultrathin packaging structure of a chip and a manufacturing method thereof, wherein the packaging structure comprises the following components: the carrier plate is provided with a first surface and a second surface opposite to the first surface, and the carrier plate is provided with at least one through groove penetrating through the carrier plate; the chip is embedded into the through groove of the carrier plate, and the front surface of the chip is flush with the first surface of the carrier plate; the plastic packaging layer is filled between the chip and the through groove of the carrier plate; the redistribution layer is stacked above the chip at intervals through an insulating medium layer, a welding pad on the front side of the chip is electrically connected with the redistribution layer, and the signal lead-out structure is electrically connected with the redistribution layer; and the protective layer is arranged below the chip. The packaging structure can effectively improve the warping problem caused by the single plastic packaging material restructuring of the wafer, can match the thickness of the chip to achieve the purpose that the packaging thickness of the chip can be freely changed as required, and can also achieve heterogeneous integration of active and passive devices.

Description

Fan-out type ultrathin packaging structure of chip and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor chip packaging, in particular to a fan-out ultrathin packaging structure of a chip and a manufacturing method thereof.
Background
Fan-out packaging is an advanced process of re-arraying and distributing I/O on the surface of a packaging by using a wafer-level re-wiring technology on a reconstituted wafer, and compared with the traditional fan-in packaging, the fan-out packaging breaks through the limitation of the size of a single chip and can meet the packaging requirement of high pin density. In recent years, with the improvement of fab process capability, the chip is developed toward smaller size and higher integration; the advent of fan-out packages has made it possible for advanced packaging to achieve the goals of high density interconnection, multi-chip integration.
At present, the mainstream fan-out packaging technology is mostly based on an eWLB fan-out packaging technology developed by the british flying company, and a plastic package material is adopted to carry out multi-surface encapsulation and fixation on an embedded chip; the scheme mainly has the following two problems: firstly, horizontally introducing a plastic packaging material into a pre-pasted chip in a plastic packaging process to cause chip offset caused by impact; secondly, the reconstituted wafer composed of the plastic packaging material has a large degree of warping. In addition, in order to maintain the strength of the reconstituted wafer, the plastic package material needs to ensure a certain thickness, so that the package thickness of the chip is limited to a certain extent by adopting the scheme.
Unlike eWLB fan-out packaging technology, huatian scientific and technological companies have developed an eSiFO fan-out process in which a recess (blind trench) slightly larger than the size of a chip is formed in a silicon carrier, and a redistribution process is performed on the surface of the chip after the chip is embedded in the recess. The method is limited by a silicon carrier plate, heterogeneous integration of an active chip and a passive chip cannot be carried out by an eSIFO fan-out process, and the packaging thickness of the whole chip cannot be changed at will according to actual requirements; in addition, the groove etching of the silicon carrier plate also has the problems that the shape of the groove bottom is difficult to control and the like.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a fan-out type ultra-thin package structure of a chip and a method for manufacturing the same. The packaging structure formed by the manufacturing method can effectively solve the warping problem caused by the single plastic packaging material reconstituted wafer, can match the thickness of the chip to achieve the purpose that the packaging thickness of the chip can be freely changed as required, and can also achieve heterogeneous integration of active and passive devices.
In order to achieve the technical purpose and achieve the technical effect, the invention is realized by the following technical scheme:
a fan-out ultra-thin package structure for a chip, comprising:
the carrier plate is provided with a first surface and a second surface opposite to the first surface, and the carrier plate is provided with at least one through groove penetrating through the carrier plate;
the chip is embedded into the through groove of the carrier plate, and the front surface of the chip is flush with the first surface of the carrier plate;
the plastic packaging layer is filled between the chip and the groove wall of the through groove of the carrier plate;
at least one rewiring layer which is stacked above the chip at intervals through an insulating medium layer, and a welding pad on the front surface of the chip is electrically connected with the rewiring layer,
a signal derivation structure electrically connected to the redistribution layer;
and the protective layer is arranged below the chip.
As a preferred technical solution of the present invention, the plastic package layer covers the front surface of the chip and the first surface of the carrier plate, and the protection layer is disposed on the back surface of the chip and the second surface of the carrier plate.
Further, in the above technical solution, the package structure includes two insulating dielectric layers and two redistribution layers; the first rewiring layer is arranged on the plastic package layer, the first insulating medium layer covers the first rewiring layer, the second rewiring layer is arranged on the first insulating medium layer, the second insulating medium layer covers the second rewiring layer, and the signal leading-out structure is arranged on the second insulating medium layer.
As another preferred technical solution of the present invention, the plastic package layer covers the back surface of the chip and the second surface of the carrier plate downward, and the protective layer is disposed on the plastic package layer.
Further, in the above technical solution, the package structure includes three insulating dielectric layers and two redistribution layers; the first insulating medium layer covers the front face of the chip and the first surface of the carrier plate, the first rewiring layer is arranged on the first insulating medium layer, the second insulating medium layer covers the first rewiring layer, the second rewiring layer is arranged on the second insulating medium layer, the third insulating medium layer covers the second rewiring layer, and the signal leading-out structure is arranged on the third insulating medium layer.
Furthermore, the signal derivation structure is a solder ball, a metal bump or a metal column.
Furthermore, the protective layer is a back adhesive film or a heat sink.
The invention further provides a manufacturing method of the fan-out ultrathin packaging structure of the chip, which comprises the following steps:
s01, bonding a supporting base body and a carrying plate together;
s02, forming a through groove on the carrier plate;
s03, embedding the chip in the through groove of the carrier plate, wherein the welding pad on the front surface of the chip is upward;
s04, plastic packaging the chip and the carrier plate by using a plastic packaging material to form a plastic packaging layer, wherein the height of the plastic packaging layer is higher than the front surface of the chip and the surface of the carrier plate;
s05, manufacturing a conduction opening at the position of the plastic package layer corresponding to the welding pad of the chip, manufacturing at least one rewiring layer above the conduction opening of the plastic package layer, and covering an insulating medium layer with a conduction opening on each rewiring layer;
s06, forming a signal leading-out structure at the conducting opening of the outermost insulating medium layer;
s07, separating the support substrate from the carrier plate to remove the support substrate and expose the back of the chip, and manufacturing a protective layer on the back of the chip;
s08, dicing and cutting to form single package structures;
in the steps, the sequence of S01 and S02 is not divided.
The invention further provides another manufacturing method of the fan-out ultrathin packaging structure of the chip, which comprises the following steps:
s11, bonding a supporting base body and a carrying plate together;
s12, forming a through groove on the carrier plate;
s13, embedding the chip in the through groove of the carrier plate, wherein the welding pad on the front surface of the chip is downward;
s14, plastic packaging the chip and the carrier plate by using a plastic packaging material to form a plastic packaging layer, wherein the height of the plastic packaging layer is higher than the back surface of the chip and the surface of the carrier plate;
s15, reversing the structure formed in the step S14 to make the bonding pad on the front surface of the chip upward, and separating the support substrate from the carrier plate to remove the support matrix and expose the front surface of the chip and the bonding pad;
s16, manufacturing an insulating medium layer on the chip, manufacturing a conduction opening at the position of the insulating medium layer corresponding to the welding pad, manufacturing at least one rewiring layer above the conduction opening of the insulating medium layer, and covering an insulating medium layer with a conduction opening on each rewiring layer;
s17, forming a signal leading-out structure at the conducting opening of the outermost insulating medium layer;
s18, manufacturing a protective layer on the back of the plastic packaging layer;
s19, dicing and cutting to form single package structures;
in the steps, the sequence of S11 and S12 is not divided.
Further, in the above method, the method of forming the redistribution layer may be one of a sputtering method, a chemical deposition method, and an electroplating method.
The invention has the beneficial effects that:
the packaging structure of the invention has a composite structure consisting of a carrier plate with a through groove structure, a plastic packaging layer and a protective layer positioned on the back of a chip; compared with the traditional eSIFO packaging technology, the carrier plate with the through groove structure can better match the thickness of the chip, so that the final packaging thickness of the chip can be changed as required to realize ultra-thin structure packaging, and meanwhile, the through groove structure can also avoid the problems of footing, salient points and the like caused by traditional blind groove etching; compared with the traditional eWLB packaging technology, the through groove structure of the carrier plate enables the chip position to be fixed, and the plastic packaging layer packages the chip in the vertical direction and cannot cause the chip to deviate; the reconstituted wafer formed by the composite structure consisting of the support plate with the through groove structure, the plastic packaging layer and the protective layer positioned on the back of the chip can effectively improve the warping problem caused by the reconstituted wafer formed by adopting a single plastic packaging material.
For the packaging process with the front side of the chip upward, after the supporting substrate and the carrier plate are separated, a back adhesive film or a radiating fin can be directly manufactured on the back side of the chip, so that the back side packaging and protection of the chip are realized; for the packaging process with the front surface of the chip facing downwards, the thickness of the plastic packaging layer and the thickness of the carrier plate on the back surface of the chip can be better matched with the thickness of the chip, the purpose that the packaging thickness of the chip can be freely changed as required is achieved, and heterogeneous integration of active and passive devices in different areas of the through groove can be conveniently achieved.
Drawings
Fig. 1 is a schematic structural diagram of a fan-out ultrathin package structure of a chip in embodiment 1 of the present invention.
Fig. 2 is a flowchart illustrating a manufacturing process of a fan-out ultra-thin package structure of a chip according to embodiment 1 of the present invention.
Fig. 3 is a schematic structural diagram of a fan-out ultrathin package structure of a chip according to embodiment 2 of the present invention.
Fig. 4 is a flowchart illustrating a manufacturing process of a fan-out ultra-thin package structure of a chip according to embodiment 2 of the present invention.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
As shown in fig. 1 and 3, the present invention provides a fan-out ultra-thin package structure of a chip, including:
a carrier plate 300, wherein the carrier plate 300 has a first surface and a second surface opposite to the first surface, and the carrier plate is provided with at least one through groove 310 penetrating through the carrier plate 300;
at least one chip 400, wherein the chip 400 is embedded in the through groove 310 of the carrier plate 300, and the front surface of the chip 400 is flush with the first surface of the carrier plate 300;
a plastic sealing layer 500 filled between the chip 400 and the through groove of the carrier plate 300;
at least one redistribution layer stacked above the chip 400 at intervals through an insulating dielectric layer, and a pad 410 on the front surface of the chip is electrically connected with the redistribution layer,
a signal derivation structure 800 electrically connected to the redistribution layer;
and a protection layer 900 disposed below the chip 400.
The material of the carrier 300 is a single material or a composite material with supporting strength, such as a silicon substrate, glass, or the like; the carrier plate 300 can be thinned to a required thickness by grinding, CMP, etching, and the like; the through groove 310 on the carrier plate 300 is formed by dry etching, wet etching or laser drilling;
the insulating medium layer is formed by pressing a photosensitive dry film or a non-photosensitive dry film, hot-pressing plastic package material and the like.
The redistribution layer is formed by sputtering, chemical deposition or electroplating.
The plastic sealing layer is made of powdery EMC or dry films such as ABF and the like, and can also be made of other materials capable of being solidified and molded.
The signal deriving structure 800 is a solder ball, a metal bump or a metal pillar.
The protection layer 900 is a material with a certain thickness, such as a back adhesive film or a heat sink.
The plurality of chips 400 embedded in the carrier 300 may be the same type of chip having the same thickness or different types of chips having different thicknesses.
Example 1
As shown in fig. 1, a fan-out ultra-thin package structure of a chip includes:
a carrier plate 300, wherein the carrier plate 300 has a first surface and a second surface opposite to the first surface, and the carrier plate 300 is provided with at least one through groove 310 penetrating through the carrier plate;
at least one chip 400, wherein the chip 400 is embedded in the through groove 310 of the carrier plate 300, and the front surface of the chip 400 is flush with the surface of the carrier plate 300;
a plastic sealing layer 500 filled between the chip 400 and the wall of the through groove of the carrier 300; the plastic package layer 500 covers the front surface of the chip 400 and the surface of the carrier plate 300 upward, that is, the filling height of the plastic package layer 500 is higher than the front surface of the chip 400 and the surface of the carrier plate 300;
two rewiring layers which are stacked above the chip 400 at intervals through two insulating medium layers, and a welding pad 410 on the front surface of the chip 400 is electrically connected with the rewiring layer; specifically, a first redistribution layer 700 is arranged on the plastic package layer 500, a first insulating dielectric layer 600 covers the first redistribution layer 700, a second redistribution layer 710 is arranged on the first insulating dielectric layer 600, and a second insulating dielectric layer 610 covers the second redistribution layer 710;
the signal leading-out structure 800 is arranged on the second insulating medium layer 610 and is electrically connected with the rewiring layer;
and a protective layer 900 disposed on the back surface of the chip 400 and the surface of the carrier 300.
As shown in fig. 2, the method for manufacturing a fan-out type ultra-thin package structure of a chip in embodiment 1 includes the following steps:
s01, providing a supporting substrate 100 and a carrier 300, laying the adhesive layer 200 on the supporting substrate 100 by coating or printing, and bonding the supporting substrate 100 and the carrier 300 together by using the adhesive layer 200; the carrier plate 300 is thinned to a required thickness;
s02, forming a through groove 310 longitudinally penetrating the entire carrier plate on the carrier plate 300; the steps S02 and S01 are not in sequence, and the through groove 310 may be formed on the carrier plate 300 first, and then the carrier plate 300 and the supporting substrate 100 are bonded together;
s03, embedding the chip 400 in the through-slot 310 of the carrier 300, wherein the front surface of the chip 400 has a pad 410, the pad 410 on the front surface of the chip is disposed upward, and the front surface of the chip 400 is flush with the surface of the carrier 300;
s04, plastic packaging the chip 400 and the carrier plate 300 by using a plastic packaging material to form a plastic packaging layer 500 with the thickness variable as required, wherein the height of the plastic packaging layer 500 is higher than the front surface of the chip 400 and the surface of the carrier plate 300;
s05, forming a via opening in the plastic package layer 500 at a position corresponding to the pad 410 of the chip 400, forming a first redistribution layer 700 above the via opening of the plastic package layer 500, covering the first redistribution layer 700 with a first insulating dielectric layer 600, forming a via opening in the first insulating dielectric layer 600 at a position corresponding to the first redistribution layer 700, forming a second redistribution layer 710 above the via opening of the first insulating dielectric layer 600, covering the second redistribution layer 710 with a second insulating dielectric layer 610, and forming a via opening in the second insulating dielectric layer 610 at a position corresponding to the second redistribution layer 710;
s06, forming a signal deriving structure 8 at the opening of the second insulating dielectric layer 610, where in this embodiment 1, the signal deriving structure 8 is a solder ball;
s07, separating the support substrate 100 from the carrier 300 to remove the support substrate 100 and expose the backside of the chip 400, and forming a protection layer 900 on the backside of the chip;
and S08, dicing and cutting to form single package structures.
Example 2
As shown in fig. 3, a fan-out ultra-thin package structure of a chip includes:
a carrier plate 300, wherein the carrier plate 300 has a first surface and a second surface opposite to the first surface, and at least one through groove 310 penetrating through the carrier plate 300 is formed on the carrier plate 300;
at least one chip 400, wherein the chip 400 is embedded in the through groove 310 of the carrier plate 300, and the front surface of the chip 400 is flush with the first surface of the carrier plate 300;
a plastic sealing layer 500 filled between the chip 400 and the through groove of the carrier plate 300; and the plastic sealing layer 500 covers the back surface of the chip 400 and the second surface of the carrier plate 300 downward;
two rewiring layers which are stacked above the chip 400 at intervals through three insulating medium layers, and a welding pad 410 on the front surface of the chip 400 is electrically connected with the rewiring layer; specifically, a first insulating medium layer 600 covers the front surface of the chip 400 and the first surface of the carrier plate 300, a first redistribution layer 700 is arranged on the first insulating medium layer 600, a second insulating medium layer 610 covers the first redistribution layer 700, a second redistribution layer 710 is arranged on the second insulating medium layer 610, and a third insulating medium layer 620 covers the second redistribution layer 710;
the signal leading-out structure 800 is arranged on the third insulating medium layer 620 and is electrically connected with the redistribution layer;
the protection layer 900 is disposed on the plastic package layer 500.
As shown in fig. 4, the method for manufacturing a fan-out type ultra-thin package structure of a chip in embodiment 2 includes the following steps:
s11, providing a supporting substrate 100 and a carrier 300, laying the adhesive layer 200 on the supporting substrate 100 by coating or printing, and bonding the supporting substrate 100 and the carrier 300 together by using the adhesive layer 200; the carrier plate 300 is thinned to a required thickness;
s12, forming a through groove 310 longitudinally penetrating the entire carrier plate on the carrier plate 300; the steps S02 and S01 are not in sequence, and the through groove 310 may be formed on the carrier plate 300 first, and then the carrier plate 300 and the supporting substrate 100 are bonded together;
s13, embedding the chip 400 in the through-slot 310 of the carrier 300, wherein the front surface of the chip 400 has a pad 410, and the pad 410 on the front surface of the chip is placed downward;
s14, plastic packaging the chip 400 and the carrier plate 300 by using a plastic packaging material to form a plastic packaging layer 500 with the thickness variable as required, wherein the height of the plastic packaging layer 500 is higher than the back surface of the chip 400 and the surface of the carrier plate;
s15, reversing the structure formed in step S14 to make the bonding pads 410 on the front surface of the chip 400 upward, and separating the supporting substrate 100 from the carrier 300 to remove the supporting substrate 100 and expose the front surface of the chip 400 and the bonding pads 410;
s16, forming a first insulating dielectric layer 600 on the chip 400, forming a via opening at a position of the first insulating dielectric layer 600 corresponding to the pad 410, forming a first redistribution layer 700 above the via opening of the first insulating dielectric layer 600, covering the first redistribution layer 700 with a second insulating dielectric layer 610, forming a via opening at a position of the second insulating dielectric layer 610 corresponding to the first redistribution layer 700, forming a second redistribution layer 710 above the via opening of the second insulating dielectric layer 610, covering the second redistribution layer 710 with a third insulating dielectric layer 620, and forming a via opening at a position of the third insulating dielectric layer 620 corresponding to the second redistribution layer 710;
s17, forming a signal deriving structure 800 at the opening of the third insulating dielectric layer 620, where in this embodiment 2, the signal deriving structure 800 is a solder ball;
s18, manufacturing a protective layer 900 on the back of the plastic packaging layer 500; in this step, the protective layer 900 may be manufactured after the plastic package layer is ground to the chip, so as to ensure maximum heat dissipation;
and S19, dicing and cutting to form single package structures.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (10)

1. A fan-out ultra-thin package structure of a chip, comprising:
the carrier plate is provided with a first surface and a second surface opposite to the first surface, and the carrier plate is provided with at least one through groove penetrating through the carrier plate;
the chip is embedded into the through groove of the carrier plate, and the front surface of the chip is flush with the first surface of the carrier plate;
the plastic packaging layer is filled between the chip and the through groove of the carrier plate;
at least one rewiring layer which is stacked above the chip at intervals through an insulating medium layer, and a welding pad on the front surface of the chip is electrically connected with the rewiring layer,
a signal derivation structure electrically connected to the redistribution layer;
and the protective layer is arranged below the chip.
2. The fan-out ultra-thin package structure of chips of claim 1, wherein the molding compound layer covers the front surface of the chip and the first surface of the carrier plate, and the protection layer is disposed on the back surface of the chip and the second surface of the carrier plate.
3. The fan-out ultrathin packaging structure of the chip is characterized by comprising two insulating dielectric layers and two rewiring layers; the first rewiring layer is arranged on the plastic package layer, the first insulating medium layer covers the first rewiring layer, the second rewiring layer is arranged on the first insulating medium layer, the second insulating medium layer covers the second rewiring layer, and the signal leading-out structure is arranged on the second insulating medium layer.
4. The fan-out ultra-thin package structure of chips of claim 1, wherein the molding compound layer covers the back surface of the chip and the second surface of the carrier plate, and the protection layer is disposed on the molding compound layer.
5. The fan-out ultrathin packaging structure of the chip is characterized by comprising three insulating medium layers and two rewiring layers; the first insulating medium layer covers the front face of the chip and the first surface of the carrier plate, the first rewiring layer is arranged on the first insulating medium layer, the second insulating medium layer covers the first rewiring layer, the second rewiring layer is arranged on the second insulating medium layer, the third insulating medium layer covers the second rewiring layer, and the signal leading-out structure is arranged on the third insulating medium layer.
6. The ultra-thin fan-out package structure of chip of claim 1, wherein said signal deriving structure is a solder ball, a metal bump or a metal pillar.
7. The fan-out ultrathin package structure of chips of claim 1, wherein the protective layer is an adhesive-backed film or a heat sink.
8. A manufacturing method of a fan-out ultrathin packaging structure of a chip is characterized by comprising the following steps:
s01, bonding a supporting base body and a carrying plate together;
s02, forming a through groove on the carrier plate;
s03, embedding the chip in the through groove of the carrier plate, wherein the welding pad on the front surface of the chip is upward;
s04, plastic packaging the chip and the carrier plate by using a plastic packaging material to form a plastic packaging layer, wherein the height of the plastic packaging layer is higher than the front surface of the chip and the surface of the carrier plate;
s05, manufacturing a conduction opening at the position of the plastic package layer corresponding to the welding pad of the chip, manufacturing at least one rewiring layer above the conduction opening of the plastic package layer, and covering an insulating medium layer with a conduction opening on each rewiring layer;
s06, forming a signal leading-out structure at the conducting opening of the outermost insulating medium layer;
s07, separating the support substrate from the carrier plate to remove the support substrate and expose the back of the chip, and manufacturing a protective layer on the back of the chip;
s08, dicing and cutting to form single package structures;
in the steps, the sequence of S01 and S02 is not divided.
9. A manufacturing method of a fan-out ultrathin packaging structure of a chip is characterized by comprising the following steps:
s11, bonding a supporting base body and a carrying plate together;
s12, forming a through groove on the carrier plate;
s13, embedding the chip in the through groove of the carrier plate, wherein the welding pad on the front surface of the chip is downward;
s14, plastic packaging the chip and the carrier plate by using a plastic packaging material to form a plastic packaging layer, wherein the height of the plastic packaging layer is higher than the back surface of the chip and the surface of the carrier plate;
s15, reversing the structure formed in the step S14 to make the bonding pad on the front surface of the chip upward, and separating the support substrate from the carrier plate to remove the support matrix and expose the front surface of the chip and the bonding pad;
s16, manufacturing an insulating medium layer on the chip, manufacturing a conduction opening at the position of the insulating medium layer corresponding to the welding pad, manufacturing at least one rewiring layer above the conduction opening of the insulating medium layer, and covering an insulating medium layer with a conduction opening on each rewiring layer;
s17, forming a signal leading-out structure at the conducting opening of the outermost insulating medium layer;
s18, manufacturing a protective layer on the back of the plastic packaging layer;
s19, dicing and cutting to form single package structures;
in the steps, the sequence of S11 and S12 is not divided.
10. The method for manufacturing the fan-out ultrathin packaging structure of the chip as claimed in claim 9, wherein the method for manufacturing the redistribution layer is one of a sputtering method, a chemical deposition method and an electroplating method.
CN202111397923.1A 2021-11-19 2021-11-19 Fan-out type ultrathin packaging structure of chip and manufacturing method thereof Pending CN114121888A (en)

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