CN114121875A - Laminated three-dimensional multi-chip module packaging structure and packaging method thereof - Google Patents

Laminated three-dimensional multi-chip module packaging structure and packaging method thereof Download PDF

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Publication number
CN114121875A
CN114121875A CN202111304376.8A CN202111304376A CN114121875A CN 114121875 A CN114121875 A CN 114121875A CN 202111304376 A CN202111304376 A CN 202111304376A CN 114121875 A CN114121875 A CN 114121875A
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China
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substrate
back surface
bga
front surface
dimensional multi
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CN202111304376.8A
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Inventor
胡红光
周冬莲
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China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
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China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
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Priority to CN202111304376.8A priority Critical patent/CN114121875A/en
Publication of CN114121875A publication Critical patent/CN114121875A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The invention discloses a laminated three-dimensional multi-chip module packaging structure and a packaging method thereof, wherein the packaging structure comprises at least one layer of first substrate, a first front surface and a first back surface of the body are provided with components and routing lines as required; the cavity part is formed by enclosing the inner side surface of the bending part and the first front surface of the body; the BGA welding spot array is arranged on the end part of the bending part far away from the body; the second substrate and the first substrate are vertically arranged, the second front surface of the second substrate faces the cavity part of the first substrate, and the second front surface is provided with area array I/O terminal pads; the BGA welding spot terminal is arranged on the area array I/O terminal welding pad and is matched and connected with the BGA welding spot array; the outer lead is arranged on the second back surface of the second substrate and extends outwards along the direction departing from the second back surface, and the second back surface is arranged opposite to one surface of the cavity part. The packaging density of the packaging structure is improved, so that the packaging density of the packaging structure can reach 100%.

Description

Laminated three-dimensional multi-chip module packaging structure and packaging method thereof
Technical Field
The invention relates to the technical field of 3D (three-dimensional) packaging, in particular to a stacked three-dimensional multi-chip module packaging structure and a packaging method thereof, which are realized based on vertical stacking of two-dimensional multi-chip modules.
Background
The packaging technology of electronic devices is a key link that restricts the development of integrated circuits. The electronic packaging is to protect chips, components and bearing substrates with various functions, ensure input and output of signals and power, and simultaneously transmit heat generated in the operation of the device to the external environment to ensure stable and normal operation of the device.
The conventional MCM technology is a two-dimensional planar technology, which is formed by closely arranging a plurality of IC bare chips, plastic packaged devices, or chip devices on a planar substrate. This packaging technology is currently approaching its theoretical maximum packing density. Generally, the packaging density of the MCM integrated circuit packaged by the metal shell processed by the conventional process is between 18 and 42 percent; the packaging density of the MCM integrated circuit with epoxy coating and double-sided mixed loading is between 30 and 50 percent; the flip-chip bonding process, the BGA device and the LTCC cavity process technology can improve the assembly density of the circuit, and can only achieve 70-80% of the assembly density.
The packaging density of the packaging structure of the conventional process is low, and needs to be further improved. In order to further increase the packing density and reduce the volume, the packaging technology must be developed from two dimensions to three dimensions, i.e. a multilayer structure in the Z-axis direction is realized. This close packing in the Z-axis direction can be a stack of chips (i.e. 3D silicon, either bare or packaged), or an MCM stack (constituting a so-called 3D-MCM).
Disclosure of Invention
In view of the above technical problems, the present invention aims to: the utility model provides a three-dimensional multi-chip module packaging structure of stromatolite formula and packaging method thereof, solves the low problem of packaging density of the packaging structure that adopts conventional technology among the prior art.
The technical scheme of the invention is as follows:
an object of the present invention is to provide a stacked three-dimensional multi-chip module package structure, comprising:
the first substrate comprises a body and bending parts arranged on the periphery of the body, and components and wiring are designed on the first front surface and the first back surface of the body as required;
the cavity part is formed by enclosing the inner side surface of the bent part and the first front surface of the body and is used for accommodating components arranged on the first front surface of the body;
the BGA welding spot array is arranged on the end part of the bent part far away from the body;
the second substrate and the first substrate are vertically arranged, the second front surface of the second substrate faces the cavity part of the first substrate, and area array I/O terminal pads are arranged on the second front surface;
the BGA welding spot terminal is arranged on the area array I/O terminal welding pad and is matched and connected with the BGA welding spot array;
and the outer lead is arranged on the second back surface of the second substrate and extends outwards along the direction departing from the second back surface, and the second back surface is arranged on the side, facing away from the cavity part, of the first substrate.
Optionally, the first substrate includes two layers, and the two layers of the first substrate are vertically arranged; and is
The cavity part of the upper layer first substrate is arranged towards the first back surface of the lower layer first substrate, so that the cavity part of the upper layer first substrate can accommodate components on the first back surface of the lower layer first substrate;
the cavity part of the lower first substrate is arranged towards the second front surface of the second substrate, so that the cavity part of the lower first substrate can accommodate the electronic component on the second front surface of the second substrate;
the first back of the lower layer first substrate is provided with a BGA welding spot array matched with the BGA welding spot array on the upper layer first substrate.
Optionally, the BGA solder joint terminal is a BGA solder ball bump terminal protruding from the second front surface toward the direction away from the second back surface.
Optionally, the first substrate is an LTCC substrate.
Optionally, the second substrate is an integrated PGA substrate.
Optionally, the number of the external leads is multiple, and the multiple external leads are arranged in an array.
Another object of the present invention is to provide a packaging method of a stacked three-dimensional multi-chip module package structure, comprising the following steps:
a cavity portion recessed toward the first back surface is formed on the first front surface of the first substrate, and a bent portion is formed on the outer periphery of the cavity portion;
forming a BGA welding spot array at the end part of the bending part;
manufacturing BGA welding spot terminals on the area array I/O terminal welding pads on the second front surface of the second substrate;
manufacturing an outer lead on the second back surface of the second substrate;
and the BGA welding spot array on the first substrate and the BGA welding spot terminal on the second substrate are pressed and connected into a whole up and down to realize vertical interconnection.
Optionally, the SMT surface assembly process is used to achieve physical and electrical interconnection of the surface mount component with the first substrate and the second substrate.
Optionally, the BGA solder joint terminal is fabricated on the second substrate by a ball-placing process.
Optionally, the outer lead is formed on the second back surface of the second substrate by using a soldering process.
Compared with the prior art, the invention has the advantages that:
according to the laminated three-dimensional multi-chip module packaging structure, the cavity part is arranged on the first substrate, so that components can be assembled on the front surface and the back surface of the substrate when the packaging is carried out in the three-dimensional vertical direction, the packaging density of the packaging structure can be improved, the packaging density of the packaging structure can reach 100%, and the problem that the packaging density is low due to the adoption of a conventional process in the prior art is solved.
Drawings
The invention is further described with reference to the following figures and examples:
fig. 1 is a schematic structural diagram of a first substrate of a stacked three-dimensional multi-chip module package structure according to an embodiment of the invention;
FIG. 2 is a diagram illustrating a second substrate of a stacked three-dimensional multi-chip module package structure according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of a stacked three-dimensional multi-chip module package structure according to an embodiment of the invention.
Wherein: 1. a first substrate; 11. a body; 12. a bending section; 13. a cavity portion; 14. a first front surface; 15. a first back surface; 16. BGA solder joint array; 2. a second substrate; 21. BGA solder joint terminals; 22. an outer lead; 23. a second front surface; 24. a second back surface; 3. and (6) a component.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
Example (b):
referring to fig. 1 to 3, the stacked three-dimensional multi-chip module package structure according to the embodiment of the invention includes two layers of the first substrate 1 and the second substrate 2, and the two layers of the first substrate 1 and the second substrate 2 are stacked in sequence in a vertical direction, i.e., in an up-down direction as shown in fig. 3. Wherein the first substrate 1 includes a body 11 and a bending portion 12, the body 11 is a flat plate, the upper and lower surfaces of the body 11 are respectively expressed by a first back surface 15 and a first front surface 14, the first front surface 14 and a second back surface 24 are both flat surfaces, components 3 and routing can be designed and arranged as required, the bending portion 12 is formed by bending and extending the periphery of the body 11 or a second front surface 23 of the body 11 downwards, the first front surface 14 of the body 11 and the inner side surface of the bending portion 12 together enclose a cavity portion 13, that is, the first substrate 1 is in a substantially Jiong-shaped structure, the cavity portion 13 can accommodate the components 3 arranged on the substrate, so that when the first substrate 1 is assembled with other first substrates 1 and/or second substrates 2 in a vertical direction, the components 3 on the first back surface 15 of the first substrate 1 at a lower layer and the components 3 on the first front surface 14 of the first substrate 1 at the layer can be accommodated in the cavity portion 13 of the first substrate 1, that is to say, the components 3 can be assembled on both the front surface and the back surface of the substrate, so that the assembly density of the packaging structure can be increased to 100%, and the problem of low assembly density caused by the conventional process in the prior art is solved.
In order to realize electrical and mechanical interconnection between vertically interconnected substrates, BGA pad arrays 16 are disposed on the end portions of the bent portions 12 of the upper first substrate 1, the end portions of the bent portions 12 of the lower first substrate 1, and the first back surface 15 of the lower first substrate 1, and BGA pad terminals 21 are disposed on the second front surface 23 of the second substrate 2. The BGA solder terminal 21 extends from the second front surface 23 of the second substrate 2 to a direction away from the second back surface 24, i.e. to extend upwards as shown in fig. 3, the upper and lower layers of the first substrate 1 are connected by soldering through the BGA solder array 16, and the lower layers of the first substrate 1 and the second substrate 2 are connected by soldering through the BGA solder array 16 and the BGA solder terminal 21. Specifically, soldering flux is printed on the solder pads of the BGA solder joint array 16 of the first substrate 1, then the first substrate 1 is placed in a reflow oven to reflow, and ball-planting is completed on the solder pads to form a GBA solder joint array, similarly, the soldering flux is printed on the solder pads of the BGA solder joint terminals 21 of the second substrate 2, then the second substrate 2 is placed in the reflow oven to reflow, and ball-planting is completed on the solder pads to form GBA solder bump terminals. The BGA welding spot array 16 and the BGA welding spot terminal 21 not only serve as mechanical support for interlayer stacking, but also serve as channels for interlayer signal interconnection, and can also serve as alignment points for alignment in assembling, so that the assembling difficulty is reduced. It should be noted that the traces on the first substrate 1 are connected to the BGA pad array 16 thereon.
In order to electrically connect the whole package structure to the outside, an outer lead 22 extending outward away from the second back surface 24, i.e., protruding downward as shown in fig. 3, is provided on the second back surface 24 of the second substrate 2, i.e., the lower surface of the second substrate 2 as shown in fig. 3. The traces on the second substrate 2 are connected to the BGA pad terminals 21 thereon, and the outer leads 22 are also connected to the BGA pad terminals 21 thereon. Therefore, signal interconnection among layers is realized after the substrates of the layers are assembled.
In some embodiments, the number of the first substrates 1 may also be other, such as one layer, three layers, and the like.
In some embodiments, BGA pad terminals 21 in the present embodiment are BGA ball bump terminals.
In some embodiments, the first substrate 1 in the present embodiment is an LTCC substrate, that is, a low temperature co-fired ceramic substrate.
In some embodiments, the second substrate 2 in the present embodiment is an integrated PGA substrate.
In some embodiments, the number of the outer leads 22 in this embodiment is multiple, and the multiple outer leads 22 are arranged on the second back surface 24 of the second substrate 2 in an array. As shown in fig. 3, the plurality of outer leads 22 are arranged at regular intervals along the length direction of the second substrate 2, that is, the left-right direction shown in fig. 3.
The height and width parameters of the BGA ball bump terminals and BGA pad array 16 will not be described in detail. For example, the width may be selected to be 0.4-0.5mm and the height may be selected to be 0.3-0.35 mm.
The implementation also includes a packaging method, comprising the steps of:
a cavity 13 recessed toward the first back surface 15 is formed on the first front surface 14 of the first substrate 1, and the outer periphery of the cavity 13 is formed as a bent portion 12;
forming a BGA solder joint array 16 at the end of the bending part 12;
the BGA solder joint terminal 21 is manufactured on the area array I/O terminal pad on the second front surface 23 of the second substrate 2;
fabricating external leads 22 on a second back surface 24 of the second substrate 2;
the BGA solder joint array 16 on the first substrate 1 and the BGA solder joint terminal 21 on the second substrate 2 are pressed up and down to be integrated, so that vertical interconnection is realized.
In some embodiments, the surface mount components 3 are physically and electrically interconnected to the first substrate 1 and the second substrate 2 using an smt (surface mount technology) surface assembly process. The specific process and process parameters are not described or limited in detail, and are conventional SMT processes.
In some embodiments, the BGA solder joint terminals 21 are fabricated on the second substrate 2 using a ball-placing process. Specifically, the LTCC substrate is selected as a carrier substrate, BGA solder ball bump terminals are formed on the planar array I/O terminal pads on the bottom surface of the LTCC substrate, and the outer leads 22 are formed on the second back surface 24, i.e., the lower surface as shown in fig. 3, by a soldering process, thereby forming an integrated PGA substrate. The brazing process and the specific process parameters are not described in detail herein, and are conventional brazing processes.
In some embodiments, the outer leads 22 are formed on the second back surface 24 of the second substrate 2 using a brazing process. The specific process and process parameters are not described or limited in detail, and are conventional brazing processes.
Compared with the traditional packaging mode, the packaging structure has the advantages that the interlayer electrical and mechanical interconnection of the packaging structure is formed at one time, the welding gradient and difficulty are reduced, and the interlayer signal interconnection transmission welding and the packaging welding process are not required to be separated and welded for multiple times.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.

Claims (10)

1. A stacked three-dimensional multi-chip module package structure, comprising:
the structure comprises at least one layer of first substrate (1), wherein the first substrate (1) comprises a body (11) and bending parts (12) arranged on the periphery of the body (11), and components (3) and routing are designed on a first front surface (14) and a first back surface (15) of the body (11) as required;
a cavity (13) which is formed by enclosing the inner side surface of the bent part (12) and the first front surface (14) of the body (11) and is used for accommodating the component (3) arranged on the first front surface (14) of the body (11);
the BGA welding spot array (16) is arranged on the end part of the bent part (12) far away from the body (11);
the second substrate (2) and the first substrate (1) are vertically arranged, a second front surface (23) of the second substrate (2) faces the cavity part (13) of the first substrate (1), and area array I/O terminal pads are arranged on the second front surface (23);
the BGA welding spot terminal (21) is arranged on the area array I/O terminal welding disc and is matched and connected with the BGA welding spot array (16);
and the outer lead (22) is arranged on the second back surface (24) of the second substrate (2) and extends outwards along the direction departing from the second back surface (24), and the second back surface (24) is arranged on the surface, facing away from the cavity part (13), of the first substrate (1).
2. The stacked three-dimensional multi-chip module package structure according to claim 1, wherein the first substrate (1) comprises two layers, the two layers of the first substrate (1) being arranged vertically above each other; and is
The cavity part (13) of the upper layer first substrate (1) is arranged towards the first back surface (15) of the lower layer first substrate (1), so that the cavity part (13) of the upper layer first substrate (1) can accommodate the component (3) on the first back surface (15) of the lower layer first substrate (1);
the cavity part (13) of the lower first substrate (1) is arranged towards the second front surface (23) of the second substrate (2), so that the cavity part (13) of the lower first substrate (1) can accommodate the electronic component (3) on the second front surface (23) of the second substrate (2);
and a BGA welding spot array (16) matched with the BGA welding spot array (16) on the upper layer first substrate (1) is arranged on the first back surface (15) of the lower layer first substrate (1).
3. A stacked three-dimensional multi-chip module package structure according to claim 1, wherein the BGA solder joint terminals (21) are BGA ball bump terminals that project from the second front surface (23) in a direction away from the second back surface (24).
4. A stacked three-dimensional multi-chip assembly package structure according to claim 1, wherein the first substrate (1) is an LTCC substrate.
5. The stacked three-dimensional multi-chip module package structure according to claim 1, wherein the second substrate (2) is an integrated PGA substrate.
6. The stacked three-dimensional multi-chip module package structure according to claim 1, wherein the number of the outer leads (22) is plural, and the plural outer leads (22) are arranged in an array.
7. A packaging method of a laminated three-dimensional multi-chip assembly packaging structure is characterized by comprising the following steps:
a cavity (13) recessed toward the first back surface (15) is formed on the first front surface (14) of the first substrate (1), and the outer periphery of the cavity (13) is formed as a bent portion (12);
forming a BGA solder joint array (16) at the end of the bending part (12);
BGA welding spot terminals (21) are manufactured on the area array I/O terminal welding pads on the second front surface (23) of the second substrate (2);
manufacturing an outer lead (22) on a second back surface (24) of the second substrate (2);
the BGA welding spot array (16) on the first substrate (1) and the BGA welding spot terminal (21) on the second substrate (2) are pressed and connected into a whole up and down to realize vertical interconnection.
8. The packaging method of the stacked three-dimensional multi-chip module packaging structure according to claim 7, wherein the surface mount device (3) is physically and electrically interconnected with the first substrate (1) and the second substrate (2) by using SMT surface assembly process.
9. The packaging method of the stacked three-dimensional multi-chip module packaging structure according to claim 7, wherein the BGA solder joint terminals (21) are formed on the second substrate (2) by a ball-placing process.
10. The packaging method of the stacked three-dimensional multi-chip module package structure according to claim 7, wherein the outer leads (22) are formed on the second back surface (24) of the second substrate (2) by a soldering process.
CN202111304376.8A 2021-11-05 2021-11-05 Laminated three-dimensional multi-chip module packaging structure and packaging method thereof Pending CN114121875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111304376.8A CN114121875A (en) 2021-11-05 2021-11-05 Laminated three-dimensional multi-chip module packaging structure and packaging method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111304376.8A CN114121875A (en) 2021-11-05 2021-11-05 Laminated three-dimensional multi-chip module packaging structure and packaging method thereof

Publications (1)

Publication Number Publication Date
CN114121875A true CN114121875A (en) 2022-03-01

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Country Status (1)

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