CN114121858A - Packaging structure, manufacturing method and semiconductor device - Google Patents

Packaging structure, manufacturing method and semiconductor device Download PDF

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Publication number
CN114121858A
CN114121858A CN202111338328.0A CN202111338328A CN114121858A CN 114121858 A CN114121858 A CN 114121858A CN 202111338328 A CN202111338328 A CN 202111338328A CN 114121858 A CN114121858 A CN 114121858A
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Prior art keywords
metal
metal part
substrate
package structure
seed layer
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CN202111338328.0A
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Chinese (zh)
Inventor
王矿伟
杨清华
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Suzhou Huntersun Electronics Co Ltd
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Suzhou Huntersun Electronics Co Ltd
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Priority to CN202111338328.0A priority Critical patent/CN114121858A/en
Publication of CN114121858A publication Critical patent/CN114121858A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezo-electric or electrostrictive material

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Acoustics & Sound (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a packaging structure, a manufacturing method and a semiconductor device, wherein the packaging structure comprises a silicon chip assembly and a substrate, the silicon chip assembly at least comprises a functional device and a protective shell for accommodating the functional device, the protective shell is provided with a first surface, at least one raised first metal part is arranged on the first surface, and a second metal part is coated outside all or part of each first metal part; the substrate is provided with a second surface opposite to the first surface, and grooves corresponding to the at least one raised first metal part in a one-to-one mode are formed in one side of the second surface of the substrate. The invention can avoid the problem that the packaging structure is easy to have bad products due to the influence of surface oxidation, impurities, particles and foreign matters.

Description

Packaging structure, manufacturing method and semiconductor device
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure, a manufacturing method and a semiconductor device.
Background
The substrate is a carrier for packaging a semiconductor device, and a process for packaging a device on the substrate is shown in fig. 1 at present, in the conventional technical scheme for packaging a wafer-level silicon chip assembly 101 after packaging on a substrate 102, the silicon chip assembly 101 is generally combined with the substrate 102 through the thermal melting of tin-silver balls 114, but under the condition that the tin-silver balls 114 contain impurities, particles, foreign matters 112 and small soldering tin amount, holes 113 and cracks 114 are generated while the silicon chip assembly 101 is combined with the substrate 102, so that the circuit contact failure and the circuit breaking are caused, and the product failure is caused.
Disclosure of Invention
The invention provides a packaging structure, a manufacturing method and a semiconductor device, which are used for solving the problem that holes and cracks are generated when the device is bonded with a substrate wire due to the influence of surface oxidation, impurities, particles and foreign matters in the traditional packaging structure.
In a first aspect, an embodiment of the present invention provides a package structure, including:
the silicon chip assembly at least comprises a functional device and a protective shell for accommodating the functional device, wherein the protective shell is provided with a first surface, at least one raised first metal part is arranged on the first surface, and a second metal part is coated outside all or part of each first metal part;
a substrate having a second surface opposite the first surface, the substrate having grooves on one side of the second surface in one-to-one correspondence with the at least one raised first metal component;
wherein each of the first metal members is embedded in the corresponding groove, and the second metal member externally coated with each of the first metal members fills a part or all of the corresponding groove.
In an embodiment of the invention, a pad is disposed at the bottom of each groove, and the pad is in contact with the second metal part in the groove to electrically connect the silicon chip assembly with the substrate.
In an embodiment of the invention, the width of each groove is larger than the sum of the widths of the corresponding first metal part and the second metal part.
In an embodiment of the present invention, each of the first metal members includes a bottom portion and at least one metal protrusion on the bottom portion, and an outer portion of each of the metal protrusions is clad with the second metal member.
In an embodiment of the present invention, the bottom is located on a surface of the protection housing or embedded inside the protection housing.
In an embodiment of the present invention, a cross-sectional shape of each of the metal protrusions is any one of: triangular, rectangular, circular, trapezoidal, T-shaped.
In an embodiment of the present invention, an outer portion of each of the metal protrusions is clad with a third metal member, and the second metal member is clad with the third metal member.
In an embodiment of the invention, the silicon chip assembly further includes a metal seed layer, and the first metal part is in communication with the metal seed layer.
In an embodiment of the invention, the first metal part is made of copper, the second metal part is made of tin-silver, the third metal part is made of nickel, and the metal seed layer is made of copper.
In an embodiment of the present invention, the package structure further includes an insulator filling a gap between the first surface and the second surface to achieve sealing.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a package structure, including:
providing a silicon chip assembly with a first surface and a substrate with a second surface;
forming at least one raised first metal feature on the first surface of the silicon chip assembly;
coating a second metal part outside all or a part of each first metal part;
forming a groove corresponding to the at least one raised first metal part one to one on one side of the second surface of the substrate;
embedding each first metal part in a corresponding groove in a flip-chip manner, and heating the second metal part to make the second metal part flow from the outside of the first metal part to the bottom of the corresponding groove in a hot melting state and fill a part or all of the groove.
In an embodiment of the invention, the forming of the at least one raised first metal part on the first surface of the silicon chip assembly comprises:
sputtering a metal layer on the first surface, and taking the metal layer as a metal seed layer;
coating a layer of photoresist on the surface of the metal seed layer, and carrying out predetermined exposure and development operations on the photoresist to form at least one through hole on the photoresist;
performing a plating operation for the at least one through-hole to form the first metal part in each through-hole;
and removing the photoresist.
In an embodiment of the present invention, the cladding of the second metal part outside all or a part of each of the first metal parts includes:
coating a layer of photoresist on the surface of the metal seed layer on which the first metal parts are formed, and performing predetermined exposure and development operations on the photoresist to expose each of the first metal parts and form cavities respectively surrounding each of the first metal parts;
performing an electroplating operation for each of the first metal members to form a third metal member covering the first metal member on an outer portion of each of the first metal members;
performing an electroplating operation for each of the first metal members to form the second metal member covering the first metal member outside a third metal member covering each of the first metal members;
removing the photoresist;
etching the metal seed layer to leave the metal seed layer under each of the first metal features.
In an embodiment of the present invention, the forming, on one side of the second surface of the substrate, a groove corresponding to the at least one raised first metal part one to one further includes:
a pad is disposed at the bottom of each recess.
In an embodiment of the present invention, the method further includes:
cooling the second metal part after the second metal part has filled a portion or all of the corresponding recess;
and an insulator is filled between the first surface and the second surface.
In an embodiment of the invention, the melting point of the first metal part is greater than the melting point of the second metal part.
In an embodiment of the present invention, a cross-sectional shape of each of the metal protrusions is any one of: triangular, rectangular, circular, trapezoidal, T-shaped.
In an embodiment of the invention, the first metal part is made of copper, the second metal part is made of tin-silver, the third metal part is made of nickel, and the metal seed layer is made of copper.
In a third aspect, an embodiment of the present invention further provides a semiconductor device, where the package structure of any one of the first aspect is adopted in the semiconductor device.
In an embodiment of the invention, the semiconductor device is a bulk acoustic wave filter, the protective casing is a micro-cap wafer, and the substrate is a package substrate.
According to the packaging structure, the manufacturing method and the semiconductor device, the second metal part is coated outside the first metal part on the device and is correspondingly embedded into the groove formed in the substrate in an inverted mode, and the second metal part falls off from the outside of the first metal part and is filled into the bottom of the groove in a hot melting state so that the device is electrically connected with the substrate.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other embodiments according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional packaging technology process;
FIG. 2 is a schematic diagram of a package structure provided by an embodiment of the invention;
FIG. 3 is a schematic structural diagram of a single first metal part and a single second metal part provided in accordance with an embodiment of the present invention;
FIG. 4 is a schematic structural view of a single first metal part and a single second metal part provided in accordance with another embodiment of the present invention;
fig. 5A is a schematic structural diagram of a plurality of first metal parts and second metal parts according to an embodiment of the present invention;
fig. 5B is a schematic structural diagram of a plurality of first metal parts and second metal parts according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a package structure according to another embodiment of the present invention;
fig. 7 is a flowchart of a method for manufacturing a package structure according to an embodiment of the invention;
FIG. 8 is a schematic view of forming a metal seed layer according to an embodiment of the present invention;
FIGS. 9A-9D are schematic illustrations of the formation of a first metal part according to an embodiment of the present invention;
FIG. 10 is a schematic illustration of forming a second metal part according to an embodiment of the present invention;
FIG. 11 is a schematic view of a etched metal seed layer according to an embodiment of the present invention;
FIG. 12 is a schematic view of forming a groove on a substrate according to an embodiment of the present invention;
fig. 13 is a schematic diagram of a flip-chip mounting of a device to a substrate in accordance with an embodiment of the present invention.
Reference numerals:
101: a device; 102: a substrate; 103: a first metal member;
104: a second metal member; 105: a metal seed layer; 106: a groove;
107: a third metal member; 108: a pad; 109: an insulator;
110: a bottom; 111: a metal projection; 112: impurities/particles/foreign matter;
113: a hole; 114: cracking; 115: a silicon base;
116: a functional device; 117: a protective housing; 118: photoresist;
119: a first surface; 120: a second surface.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," and the like in the description and in the claims, and in the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein.
In the prior art, the bonding of device and base plate is realized being connected through the hot melting of tin silver ball, but has impurity, granule, foreign matter and the condition that tin silver volume is few at the tin silver ball, installs the device upside down and goes up the base plate after through heating tin silver ball recooling, can make device and base plate wire combine have hole and crackle production simultaneously, lead to circuit contact failure and open circuit to cause the product to be bad.
Therefore, the invention provides a packaging structure, a manufacturing method and a semiconductor device, which aim to solve the problem that the packaging structure is easily poor due to the influence of surface oxidation, impurities, particles and foreign matters.
The package structure, the manufacturing method and the semiconductor device according to the present invention are described below with reference to fig. 2 to 13.
Referring to fig. 2, fig. 2 is a schematic diagram of a package structure according to an embodiment of the invention. The invention provides a packaging structure, which comprises a silicon chip assembly 101 and a substrate 102.
Illustratively, the silicon chip assembly 101 at least comprises a functional device and a protective shell for accommodating the functional device, the protective shell has a first surface 119, the first surface 119 is provided with at least one raised first metal part 103, the exterior of all or a part of each first metal part 103 is coated with a second metal part 104, and the silicon chip assembly 101 can be a chip or other semiconductor component.
The first metal part 103 may be directly located on the first surface 119, or may be partially located in the protective shell.
Illustratively, the substrate 102 has a second surface 120 opposite the first surface 119, the substrate being provided with grooves 106 on one side of the second surface 120 in one-to-one correspondence with the at least one raised first metal part 103.
Wherein each of the first metal members 103 is embedded in the corresponding groove 106, and the second metal member 104 coated outside each of the first metal members 103 fills a part or all of the corresponding groove 106.
Illustratively, the bottom of each of the grooves 106 is provided with a pad 108, and the pad 108 is in contact with the second metal part 104 in the groove 106 to electrically connect the silicon chip assembly 101 with the substrate 102.
Illustratively, the first metal part 103 coated with the second metal part 104 is embedded into the groove 106 in a flip-chip manner, and the second metal part 104 is peeled off from the outside of the first metal part 103 in a thermally fused state and filled into the bottom of the groove 106 along the first metal part 103 to electrically connect the silicon chip assembly 101 with the pad 108 of the substrate 102, wherein the melting point of the first metal part 103 is greater than that of the second metal part 104. The width of the groove 106 is larger than the sum of the widths of the first metal part 103 and the second metal part 104, so that the second metal part 104 can flow into the groove 106 by gravity when dissolved, and the first metal part 103 can also flow into the groove 106 by gravity, for example, into the groove 106 so that the second metal part 104 can flood a portion of the first metal part 103, thus achieving electrical connection after the second metal part 104 cools. The invention is not limited to the design of the groove 106.
The flip chip packaging technology is to directly interconnect a component downwards to a substrate, a carrier or a circuit board through bumps on a chip. The flip chip packaging technology uses solder bumps to electrically connect the substrate and the chip, and the electrical connection in this manner is relatively small in size, reduces delay, and enables better isolation of input and output pins.
Illustratively, the silicon chip assembly 101 further comprises a metal seed layer, and the first metal part 103 is in communication with the metal seed layer. The metal seed layer may be made of one or more metals, such as copper, and is disposed between the first metal part 103 and the surface of the silicon chip assembly 101, so that the first metal part 103 and the silicon chip assembly 101 have good adhesion. In one embodiment, the material of the outermost layer of the metal seed layer is the same as the material of the first metal feature 103.
It should be noted that the silicon chip assembly 101 may not include a metal seed layer, and the invention is not limited to whether the silicon chip assembly 101 includes the metal seed layer.
Illustratively, the height and shape of the first metal part 103 are determined by the design requirements of the silicon chip assembly 101, and the invention is not limited to the shape and height of the first metal part 103. For example, the first metal member 103 has at least one metal protrusion 111, and the cross-sectional shape of each metal protrusion 111 is any one of the following: triangular, rectangular, circular, trapezoidal, T-shaped.
In addition, the thickness of the second metal part 104 is not limited in the present invention, and the thickness of the second metal part 104 is determined by the amount of metal melted from the second metal part, that is, the amount of metal of the second metal part 104 can fill most of the space of the groove 106 of the substrate 102.
For example, the material of the first metal part 103 may be copper, and the material of the second metal part 104 may be tin-silver. Wherein the melting point of tin-silver is about 221 deg.C and the melting point of copper is about 1088 deg.C.
Specifically, after the silicon chip module 101 is flip-chip mounted on the substrate 102, the substrate 102 is heated to a temperature higher than the melting point of tin and silver, the tin and silver are dissolved in the groove 106 in the substrate 102 under the influence of gravity, and the substrate 102 and the silicon chip module 101 are connected and conducted by the tin and silver after cooling.
Illustratively, the package structure further comprises an insulator 109, and the insulator 109 fills a gap between the first surface of the silicon chip assembly 101 and the second surface of the substrate 102 to achieve sealing.
The shape of the first metal member 103 will be described below with reference to fig. 3 to 5B.
Fig. 3 is a schematic structural diagram of a single first metal part and a single second metal part according to an embodiment of the present invention, as shown in fig. 3. Fig. 3 shows a silicon chip assembly 101 and a first metal part 103 and a second metal part 104 on the silicon chip assembly 101.
Wherein, the outside of the first metal part 103 is completely covered with the second metal part 104, and the cross-sectional shapes of the first metal part 103 and the second metal part 104 are isosceles trapezoids. Fig. 3 is only an example of the sectional shapes of the first metal member and the second metal member according to the present invention, and the present invention is not limited to the sectional shapes of the first metal member and the second metal member.
Fig. 4 is a schematic structural diagram of a single first metal part and a single second metal part according to another embodiment of the present invention, as shown in fig. 4. Fig. 4 shows a silicon chip assembly 101 and a first metal part 103 and a second metal part 104 on the silicon chip assembly 101.
Wherein each first metal part 103 comprises a bottom 110 and at least one metal protrusion 111 on the bottom 110, and the exterior of each metal protrusion 111 is wrapped with the second metal part 104. The exterior of the bottom 110 may or may not be clad with the second metal part 104. Fig. 4 shows that each metal part 103 includes a bottom portion 110 and three metal protrusions 111 provided on the bottom portion 110, but the number of the metal protrusions 111 is not limited in the present invention.
Here, the shape of the metal protrusion 111 of the first metal member 103 may be a rectangular parallelepiped or a cylindrical shape, the shape of the metal protrusion 111 in a plan view shown on the right side of fig. 4 is a rectangle, and the shape of the metal protrusion 111 in a plan view shown on the lower side of fig. 4 is a circle. The shape of the metal protrusion 111 is not limited in the present invention.
It should be noted that the bottom 110 of the present invention may be located on the surface of the protective shell (as shown in fig. 5A), or may be embedded inside the protective shell (as shown in fig. 5B). Increasing the number of protruding first metal features 103 increases the contact area of first metal features 103 and second metal features 104, as size and process allow.
Fig. 5A is a schematic structural diagram of a plurality of first metal parts and second metal parts according to an embodiment of the present invention, as shown in fig. 5A. Fig. 5A shows two first metal parts 103, wherein one first metal part 103 is disposed on the surface of the silicon chip assembly 101, and comprises a bottom 110 and two metal protrusions 111 disposed on the bottom 110, and the exterior of the two metal protrusions 111 is entirely clad with the second metal part 104. The other first metal part 103 may not be provided with the bottom 110, but be directly provided on the surface of the silicon chip assembly 101, and the outside of the other first metal part 103 is entirely wrapped with the second metal part 104.
Fig. 5B is a schematic structural diagram of a plurality of first metal parts and second metal parts according to another embodiment of the present invention, as shown in fig. 5B. Fig. 5B shows two first metal parts 103, wherein one first metal part 103 is embedded inside the silicon chip assembly 101, which comprises a bottom 110 and two metal protrusions 111 arranged on the bottom 110, and the exterior of the two metal protrusions 111 is all coated with the second metal part 104. The other first metal part 103 may not be provided with the bottom 110, but be directly provided on the surface of the silicon chip assembly 101, and the outside of the other first metal part 103 is entirely wrapped with the second metal part 104.
Fig. 5A and 5B are only two examples of the embodiments of the present invention, and therefore, the present invention is not limited as to whether the first metal part 103 needs to be provided with the bottom portion 110 or how many metal protrusions 111 are provided to share one bottom portion 110, and is also not limited as to whether the first metal part 103 is provided on the surface of the silicon chip assembly 101 or embedded inside the silicon chip assembly 101. In addition, the size of the bottom 110 is not limited in the present invention, and the bottom 110 may have the same or different cross-sectional size as the protrusion 111.
Here, the shape of the first metal member 103 may be a rectangular parallelepiped or a cylindrical shape, and the shape of the first metal member 103 in the plan view shown in fig. 5A and 5B may be a rectangular shape or a circular shape. The present invention does not limit the shape of the first metal member 103.
Exemplarily, in fig. 4, 5A, and 5B, the first metal member 103 may be externally coated with the third metal member, and the third metal member may be externally coated with the second metal member 104. The material of the third metal part may be nickel.
It should be noted that the shape and thickness of the third metal part and/or the second metal part 104 coated outside the first metal part 103 are not limited in the present invention.
The package structure of the present invention is described below by taking a BAW filter as an example.
The BAW filter is a device based on bulk acoustic wave theory and using acoustic resonance to realize electric filtering, and filtering is performed through resonance of a piezoelectric layer between electrodes in a vertical direction. The cavity type BAW filter is the most successful BAW filter applied at present, the main structure of the BAW filter is a sandwich structure consisting of an upper electrode, a piezoelectric layer and a lower electrode, cavities are arranged on two sides of the upper electrode and two sides of the lower electrode, and when a sound wave signal travels to the top end of the upper electrode and the bottom end of the lower electrode, total reflection of the sound wave is caused due to great difference of acoustic impedance. The BAW filter has small acoustic leakage and can realize high Q value of the device.
Referring to fig. 6, fig. 6 is a schematic diagram of a package structure according to another embodiment of the invention, as shown in the drawing. The packaging structure provided by the embodiment of the invention comprises a silicon chip assembly 101 and a substrate 102.
Illustratively, the silicon chip component 101 may be a BAW filter. The BAW filter includes a silicon substrate (Sillcon)115, a functional Device (Device)116 over the silicon substrate, and a protective case (Cap)117 for protecting the functional Device 116.
Illustratively, the functional device 116 includes at least two thin film resonator elements. The thin film resonator unit may include, for example, a piezoelectric layer and two electrode layers disposed on upper and lower sides of the piezoelectric layer, and when an electric field is applied between the two electrodes, that is, there is a voltage drop between the two electrodes, resonance may be generated along a stacking direction of the electrodes and the piezoelectric layer, and a frequency of the resonance is related to thicknesses, materials, and the like of the piezoelectric layer and the electrode layers; at least two thin film resonator units can realize signal passing in a certain frequency band in a serial connection or parallel connection mode, and signals in the frequency band do not pass.
It should be noted that the package structure shown in fig. 6 and the package structure technology described above may be referred to each other, and repeated details are not repeated.
The following describes a method for manufacturing the package structure according to an embodiment of the invention.
Referring to fig. 7, fig. 7 is a flowchart illustrating a method for fabricating a package structure according to an embodiment of the invention. The invention provides a manufacturing method of a packaging structure, which comprises the following steps:
step 701, a silicon chip assembly having a first surface and a substrate having a second surface are provided.
Wherein the package structure may be a package structure of a device, which may be a chip or other semiconductor device, such as a BAW filter device. The substrate is a package substrate and is a carrier of the device.
At step 702, at least one raised first metal feature is formed on the first surface of the silicon chip assembly.
Optionally, a metal layer is first sputtered on the first surface, and the metal layer is used as a metal seed layer. Then, a layer of photoresist is coated on a surface of the metal seed layer, and predetermined exposure and development operations are performed with respect to the photoresist to form at least one through hole on the photoresist, and a plating operation is performed with respect to the at least one through hole to form the first metal feature in each through hole. And finally, removing the photoresist.
It should be noted that the first surface of the present invention may not be sputtered with the metal seed layer, and therefore, the present invention does not limit whether a metal layer needs to be sputtered.
And 703, coating a second metal part outside all or part of each first metal part.
Optionally, a layer of photoresist is first coated on a surface of the metal seed layer on which the first metal features are formed, and predetermined exposure and development operations are performed on the photoresist to expose each of the first metal features and form a cavity respectively surrounding each of the first metal features. Then, performing an electroplating operation for each of the first metal members to form a third metal member covering the first metal member on the outside of each of the first metal members; and performing an electroplating operation for each of the first metal members to form the second metal member covering the first metal member outside a third metal member covering each of the first metal members. Finally, the photoresist is removed, and the metal seed layer is etched to leave the metal seed layer under each of the first metal features.
It should be noted that, the present invention is not limited to whether the third metal part needs to be coated outside the first metal part.
Step 704, forming a groove corresponding to the at least one raised first metal part on one side of the second surface of the substrate.
Illustratively, forming a groove on one side of the second surface of the substrate in one-to-one correspondence with the at least one raised first metal part further comprises:
a pad is disposed at the bottom of each recess.
Step 705, embedding each first metal part into a corresponding groove in a flip-chip manner, and heating the second metal part to enable the second metal part to flow from the outside of the first metal part to the bottom of the corresponding groove in a hot melting state and fill a part or all of the groove.
Illustratively, the manufacturing method of the package structure further includes:
cooling the second metal part after the second metal part has filled a portion or all of the corresponding recess; and an insulator is filled between the first surface and the second surface.
It should be noted that the insulator may be a molding compound for encapsulating the device, and may be used not only to fill between the first surface and the second surface, but also to cover the outer surface of the entire chip assembly 101.
Illustratively, each of the first metal parts is made up of at least one metal projection, and the second metal part is clad on the outside of each of the metal projections.
Illustratively, the height and shape of the first metal features are determined by the design requirements of the device, and the invention is not limited to the shape and height of the first metal features. For example, each metal protrusion of the first metal member has a cross-sectional shape of any one of: triangular, rectangular, circular, trapezoidal, T-shaped.
In addition, the thickness of the second metal part is not limited, and the thickness of the second metal part is determined by the amount of metal of the second metal part after melting, and the amount of metal of the second metal part can fill most of the space of the groove of the substrate.
Illustratively, the melting point of the first metal part is greater than the melting point of the second metal part. The first metal feature may be copper, the second metal feature may be tin-silver, the third metal feature may be nickel, and the metal seed layer may be copper. Wherein the melting point of tin-silver is about 221 deg.C and the melting point of copper is about 1088 deg.C.
Specifically, after the device is inversely installed on the substrate, the substrate is heated to be higher than the melting point of tin and silver, the tin and silver are dissolved into the groove in the substrate under the influence of gravity, and the substrate and the device are connected and conducted through the tin and silver after cooling.
The method for manufacturing the package structure according to the present invention is specifically described below with reference to fig. 8 to 13.
Fig. 8 is a schematic diagram of forming a metal seed layer according to an embodiment of the invention, as shown in fig. 8. Firstly, a layer of copper is sputtered on the first surface of one side of the silicon chip assembly 101 as the metal seed layer 105 for copper electroplating, wherein the material of the metal seed layer 105 is not limited by the present invention. The metal seed layer 105 can reduce the probability of pores during the subsequent copper electroplating, thereby improving the product yield. It is understood that the present invention may not provide a metal seed layer.
In the sputtering process, particles (ions or neutral atoms, molecules) with certain energy bombard the surface of a solid, so that the atoms or molecules near the surface of the solid obtain enough energy to finally escape from the surface of the solid. Sputtering can only be performed under a certain vacuum condition.
Fig. 9A to 9D are schematic views of forming a first metal member according to an embodiment of the present invention, as shown in fig. 9A to 9D. Fig. 9A is a view showing the steps of the resist coating, the exposure and the development in fig. 8. Fig. 9B is a step of electroplating copper on the basis of fig. 9A to form a first metal part 103 (e.g., a copper pillar), wherein the height and shape of the first metal part 103 are specifically determined by the design requirements of the silicon chip assembly 101. Fig. 9C is a photoresist stripping process performed on the substrate of fig. 9B, resulting in a stripped first metal feature 103 (e.g., a copper pillar). Fig. 9D is a process of performing paste application, exposure, and development on the substrate of fig. 9C to expose the first metal member 103 (e.g., copper pillar).
The photoresist is generally formed by mixing different materials such as Resin (Resin), Sensitizer (Sensitizer) and Solvent (Solvent). The coating is to uniformly coat a layer of photoresist on the surface of the clean and dry wafer. Development is the process of removing the exposed photoresist.
FIG. 10 is a schematic illustration of the formation of a second metal part, as shown in FIG. 10, in accordance with an embodiment of the present invention. Fig. 10 is a view of forming the second metal member 104 on the basis of fig. 9D.
Illustratively, a layer of the third metal part 107 (not shown in the drawings, for example, nickel) may be electroplated on the outside of the first metal part 103 before forming the second metal part 104, because the function of electroplating nickel may be better combined with the first metal part 103 (for example, copper pillar), and the thickness of electroplating nickel is not limited by the invention, and may be determined according to practical requirements, for example, only a thin layer is needed.
In addition, the thickness of the second metal part 104 is not limited in the present invention, and the thickness of the second metal part 104 (e.g. tin-silver) is determined by the amount of metal, for example, the amount of metal can fill most of the space interface of the groove in the substrate under the condition of thermal melting, and the second metal part 104 can effectively cover a part of the first metal part 104 (e.g. copper pillar) or include the whole first metal part 104 (e.g. copper pillar).
FIG. 11 is a schematic diagram of etching a metal seed layer according to an embodiment of the invention, as shown in FIG. 11. Fig. 11 is a process of degelation and etching the metal seed layer 105 based on fig. 10, wherein the metal seed layer 105 (e.g., copper seed layer) is etched to leave the metal seed layer 105 under only the first metal features 103 and the second metal features 104.
Fig. 12 is a schematic view illustrating a substrate having a groove formed thereon according to an embodiment of the invention, as shown in fig. 12. Fig. 12 shows that a hole is opened in the substrate 102, forming a recess 106, and at the bottom of the recess 106 is a pad 108. The invention is not limited to the manner of forming the grooves by opening the holes. Since the first metal member coated with the second metal member needs to be inserted into the groove 106, the width of the groove 106 should be larger than the widths of the first metal member and the second metal member, that is, larger than the sum of the width of the first metal member and the width of the second metal member.
Fig. 13 is a schematic diagram of a flip-chip mounting device on a substrate according to an embodiment of the invention, as shown in fig. 13. The silicon chip assembly 101 including the first metal part 103 and the second metal part 104 formed in fig. 11 is flip-chip embedded in the groove 106 formed in fig. 12. The substrate 102 is then heated down to above the melting point of the second metal part 104, which is about 221 c or higher if the material of the second metal part 104 is tin-silver. After the second metal part 104 is melted thermally, it is dissolved into the groove 106 in the substrate 102 along the first metal part 103 under the influence of gravity, and then the second metal part 104 connects and conducts the pad 108 with the silicon chip assembly 101 after cooling. Wherein the first metal part 103 (e.g. copper, which has a melting point of about 1088 c) has a melting point which is higher than the melting point of the second metal part 104 (e.g. tin-silver, which has a melting point of about 221 c).
Illustratively, after the above-described silicon chip assembly 101 is packaged to the substrate 102, a gap between the silicon chip assembly 101 and the substrate 102 (i.e., between the first surface and the second surface) is blocked by an insulator 109 (e.g., resin). It is understood that the insulator may also be a molding compound for encapsulating the device, and may be used not only to fill between the first surface and the second surface, but also to cover the entire outer surface of the chip assembly 101.
In summary, the manufacturing method of the package structure and the package structure of the present invention are based on the same application concept, so the manufacturing method of the package structure and the package structure can be referred to each other, and repeated details are not repeated.
The embodiment of the invention also provides a semiconductor device, which adopts the packaging structure as described in any one of the above.
Illustratively, the semiconductor device is a bulk acoustic wave filter, the protective housing is a micro-cap wafer, and the substrate is a package substrate.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (19)

1. A package structure, comprising:
the silicon chip assembly at least comprises a functional device and a protective shell for accommodating the functional device, wherein the protective shell is provided with a first surface, at least one raised first metal part is arranged on the first surface, and a second metal part is coated outside all or part of each first metal part;
a substrate having a second surface opposite the first surface, the substrate having grooves on one side of the second surface in one-to-one correspondence with the at least one raised first metal component;
wherein each of the first metal members is embedded in the corresponding groove, and the second metal member externally coated with each of the first metal members fills a part or all of the corresponding groove.
2. The package structure of claim 1, wherein a bottom of each of the recesses is provided with a pad that contacts the second metal part in the recess to electrically connect the silicon chip assembly with the substrate.
3. The package structure of claim 2, wherein a width of each of the grooves is greater than a sum of widths of the corresponding first and second metal parts.
4. The package structure of claim 3, wherein each of the first metal members comprises a bottom portion and at least one metal protrusion on the bottom portion, an exterior of each of the metal protrusions being clad with the second metal member.
5. The encapsulation structure of claim 4, wherein the bottom is located on a surface of the protective shell or embedded inside the protective shell.
6. The package structure of claim 4, wherein a cross-sectional shape of each of the metal protrusions is any one of: triangular, rectangular, circular, trapezoidal, T-shaped.
7. The package structure according to claims 1-6, wherein an exterior of each of the metal protrusions is clad with a third metal member, and the second metal member is clad with the third metal member.
8. The package structure of any of claims 1-6, wherein the silicon chip assembly further comprises a metal seed layer, the first metal feature being in communication with the metal seed layer.
9. The package structure of claim 8, wherein the first metal feature is copper, the second metal feature is tin-silver, the third metal feature is nickel, and the metal seed layer is copper.
10. The package structure of claim 1, further comprising an insulator filling a void between the first surface and the second surface to effect a seal.
11. A method for manufacturing a package structure includes:
providing a silicon chip assembly with a first surface and a substrate with a second surface;
forming at least one raised first metal feature on the first surface of the silicon chip assembly;
coating a second metal part outside all or a part of each first metal part;
forming a groove corresponding to the at least one raised first metal part one to one on one side of the second surface of the substrate;
embedding each first metal part into a corresponding groove in a flip-chip manner, and heating the second metal part to make the second metal part flow from the outside of the first metal part to the bottom of the corresponding groove in a hot melting state and fill a part or all of the groove;
wherein the melting point of the first metal part is greater than the melting point of the second metal part.
12. The method of claim 11, wherein the forming at least one raised first metal feature on the first surface of the silicon chip assembly comprises:
sputtering a metal layer on the first surface, and taking the metal layer as a metal seed layer;
coating a layer of photoresist on the surface of the metal seed layer, and carrying out predetermined exposure and development operations on the photoresist to form at least one through hole on the photoresist;
performing a plating operation for the at least one through-hole to form the first metal part in each through-hole;
and removing the photoresist.
13. The method for manufacturing the package structure according to claim 12, wherein the step of coating all or a part of each of the first metal parts with the second metal part comprises:
coating a layer of photoresist on the surface of the metal seed layer on which the first metal parts are formed, and performing predetermined exposure and development operations on the photoresist to expose each of the first metal parts and form cavities respectively surrounding each of the first metal parts;
performing an electroplating operation for each of the first metal members to form a third metal member covering the first metal member on an outer portion of each of the first metal members;
performing an electroplating operation for each of the first metal members to form the second metal member covering the first metal member outside a third metal member covering each of the first metal members;
removing the photoresist;
etching the metal seed layer to leave the metal seed layer under each of the first metal features.
14. The method of claim 13, wherein forming a recess on one side of the second surface of the substrate in one-to-one correspondence with the at least one raised first metal feature further comprises:
a pad is disposed at the bottom of each recess.
15. The method for manufacturing the package structure according to claim 14, further comprising:
cooling the second metal part after the second metal part has filled a portion or all of the corresponding recess;
and an insulator is filled between the first surface and the second surface.
16. The method for manufacturing a package structure according to any one of claims 11 to 15, wherein a cross-sectional shape of each of the metal protrusions is any one of: triangular, rectangular, circular, trapezoidal, T-shaped.
17. The method of claim 16, wherein the first metal feature is made of copper, the second metal feature is made of tin-silver, the third metal feature is made of nickel, and the metal seed layer is made of copper.
18. A semiconductor device characterized in that the semiconductor device employs the package structure as claimed in any one of claims 1 to 10.
19. The semiconductor device according to claim 18, wherein the semiconductor device is a bulk acoustic wave filter, the protective case is a microcap wafer, and the substrate is a package substrate.
CN202111338328.0A 2021-11-12 2021-11-12 Packaging structure, manufacturing method and semiconductor device Pending CN114121858A (en)

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