CN112117242B - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN112117242B CN112117242B CN201910536027.5A CN201910536027A CN112117242B CN 112117242 B CN112117242 B CN 112117242B CN 201910536027 A CN201910536027 A CN 201910536027A CN 112117242 B CN112117242 B CN 112117242B
- Authority
- CN
- China
- Prior art keywords
- chip
- base island
- film layer
- base
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises a base island, packaging materials, a first chip attached to the upper surface of the base island and a second chip arranged far away from the upper surface of the base island compared with the first chip, and is characterized by further comprising a base film layer arranged on the lower surface of the second chip and a plurality of connecting columns, wherein the upper ends of the connecting columns are planted on the base film layer, the lower ends of the connecting columns are welded to the upper surface of the base island, and the packaging materials encapsulate the first chip and the second chip and are filled between the base island and the second chip. Through the arrangement of the substrate film layer and the planting of the connecting column, the packaging material can wrap around the connecting column and fill in a gap between the second chip and the base island, so that smooth discharge of gas in the wrapping process is facilitated, and the void phenomenon is avoided; and, the upper end of spliced pole is planted and is established in the basement rete and its lower extreme welds to the base island on for the spliced pole steadiness is strong, avoids the spliced pole to drop or shift.
Description
Technical Field
The invention belongs to the technical field of chip packaging, and relates to a chip packaging structure and a manufacturing method thereof.
Background
The rapid development of modern electronic information technology, and the development of electronic products towards miniaturization, portability and multi-functionalization, drive the miniaturization development trend of semiconductor packaging products, and thus the packaging design is required to utilize the packaging space to the maximum extent and reduce the size of the semiconductor packaging products.
Among the current packaging structure, when having a plurality of chips, can appear piling up the condition of another chip on a chip usually, for staggering routing route, avoid the lead wire to bump the line and cause unfavorable problem, partly unsettled phenomenon can appear in last chip usually, in order to avoid the unsettled region chip breakage, cracked problem appear when the routing, need set up the gasket in chip unsettled region below and support, put up high unsettled chip. Taking the package structure 200 shown in fig. 1 and fig. 2 with two chips (the chip 211 and the chip 212) as an example, the package structure 200 further includes a lead frame and a plurality of leads 230, the lead frame specifically includes a base island 221 and pins 222, and the base island 221 is used for fixedly supporting the chip 211 and the chip 212. The chip 211, the chip 212, and the pins 222 may be electrically connected to each other by wires 230. As mentioned above, the chip 212 is elevated by the spacer 250, and the chip 212 is broken and broken in the suspended area during wire bonding.
However, in the conventional package structure, as shown in the figure, after the chip 212 is raised by the spacer 250, a certain slit S is usually left between the spacer 250 and the chip 211 located at the lower layer, and during the encapsulation process in the manufacturing process, the encapsulant 240 needs to be wrapped back into the slit S from the two ends S1 and S2 of the slit S, which often causes gas residue in the slit S due to abnormal discharge of gas, and further causes a void problem, which affects the product quality.
Disclosure of Invention
In order to solve the problem of voids caused by gas residue during encapsulation after a chip rack is raised in the prior art, the invention aims to provide a chip packaging structure and a manufacturing method thereof, which can avoid the occurrence of the void phenomenon while the chip rack is raised.
In order to achieve one of the above objects, an embodiment of the present invention provides a chip package structure, which includes a base island, a package material, a first chip attached to an upper surface of the base island, and a second chip disposed on an upper surface of the base island away from the first chip, the chip package structure further includes a base film layer and a plurality of connection pillars, the base film layer is disposed on a lower surface of the second chip, upper ends of the connection pillars are implanted in the base film layer, and lower ends of the connection pillars are soldered to the upper surface of the base island, and the package material encapsulates the first chip and the second chip and is filled between the base island and the second chip.
As a further improvement of one embodiment of the present invention, any two of the connecting posts are separated from each other and do not contact each other.
As a further improvement of an embodiment of the present invention, the base film layer is provided by sputtering a metal film;
the connecting column comprises a metal column and a convex point implanted at the lower end of the metal column, and is welded on the upper surface of the base island through the convex point.
As a further improvement of an embodiment of the present invention, an upper surface of the second chip is an electrical signal functional surface; the upper surface of the first chip is an electrical signal functional surface;
the packaging structure further comprises a pin, and electrical connection is established among any two of the second chip, the pin and the first chip through a lead;
the encapsulant also encapsulates the leads and covers the upper surfaces of the pins.
As a further improvement of an embodiment of the present invention, the first chip is attached to the upper surface of the base island by a die bonding adhesive;
and one part of the second chip and one part of the first chip are arranged in an up-and-down overlapping manner, and a mounting adhesive is filled between the two parts.
In order to achieve one of the above objects, an embodiment of the present invention further provides a method for manufacturing a chip package structure, including:
forming a base film layer on the first surface of the second chip;
planting a plurality of connecting columns on the substrate film layer;
attaching a first chip to the upper surface of the base island;
bonding the connection post to an upper surface of the base island to secure the second chip to the base island;
and encapsulating by using an encapsulating material to obtain the chip encapsulating structure.
As a further improvement of an embodiment of the present invention, the step of "molding a base film layer on the first surface of the second chip" includes:
attaching a protective film to a second surface of a second chip, wherein the second surface is opposite to the first surface and is an electrical signal functional surface of the second chip;
grinding and ultrasonically cleaning the first surface of the second chip;
and sputtering and forming a base film layer on the first surface of the second chip.
As a further improvement of an embodiment of the present invention, the step of "implanting a plurality of connection pillars on the substrate film layer" includes:
laying a photosensitive dry film on the substrate film layer;
carrying out partition exposure development on the photosensitive dry film to enable the photosensitive dry film to pattern a plurality of column planting openings exposing the substrate film layer;
sequentially planting metal columns and salient points at the openings of the planting columns to obtain connecting columns;
and removing the photosensitive dry film from the substrate film layer implanted with the connecting column.
As a further improvement of one embodiment of the present invention, any two of the connecting posts are separated from each other and do not touch each other.
As a further improvement of an embodiment of the present invention, before encapsulating with the encapsulant, at least two of the first chip, the second chip, and the pins are electrically connected by a lead;
in the steps of forming a base film layer on a first surface of a second chip and planting a plurality of connecting columns on the base film layer, the plurality of second chips are integrated on the same wafer and synchronously carried out in batch; and dicing the plurality of second chips from the wafer before the step of bonding the connection posts to the upper surface of the base island to secure the second chips to the base island.
Compared with the prior art, the invention has the beneficial effects that: through the arrangement of the substrate film layer and the planting of the connecting columns, a chip (the second chip) to be erected is fixedly mounted on the base island through the connecting columns, so that the packaging material can wrap around the connecting columns and fill in a gap between the second chip and the base island, the phenomenon that gas is difficult to discharge due to the fact that two ends of the packaging material wrap back in the prior art is avoided, further, the cavity phenomenon is avoided, and the product quality is guaranteed; in addition, the upper end of the connecting column is planted in the base film layer and the lower end of the connecting column is welded on the base island, so that the connecting column is strong in connection stability with the second chip and the base island, the connecting column is prevented from falling off or shifting, and product quality is further guaranteed.
Drawings
FIG. 1 is a top view of a prior art package structure with partial perspective effect;
FIG. 2 isbase:Sub>A cross-sectional view ofbase:Sub>A package structure in the prior art, the cross-section being taken along A-A in FIG. 1;
FIG. 3 is a top view of a chip package structure with partial perspective effect according to an embodiment of the invention;
FIG. 4a is a cross-sectional view of a chip package structure according to an embodiment of the invention, the cross-section being along B-B in FIG. 3;
FIG. 4b is an enlarged view of area C of FIG. 4 a;
FIG. 5 is a flow chart of a method for manufacturing a chip package structure according to an embodiment of the invention;
FIG. 6 is a schematic view of the electrical signal functional surface of the second chip with a protective film attached;
FIG. 7 is a schematic view of the grinding and cleaning of the non-electrical signal functional side of the second chip;
FIG. 8 is a schematic view of the non-electrical signal functional side of the second chip patterned with a base film layer;
FIG. 9 is a schematic view of a substrate film layer coated with a photosensitive dry film;
FIG. 10a is a schematic diagram of the photosensitive dry film after exposure and development for patterning;
fig. 10b is a top view of the photosensitive dry film patterned after exposure and development;
FIG. 11 is a schematic view of a connection column being planted at an opening of the column;
FIG. 12 is a schematic view of the photosensitive dry film being peeled off;
fig. 13 is a schematic view of a first chip attached to a base island;
fig. 14 is a schematic view of a second chip mounted to a base island;
FIG. 15 is a schematic diagram of the connecting leads between the first chip, the second chip, and the pins;
FIG. 16 is a schematic diagram of a chip package structure formed after encapsulation;
fig. 17 is a schematic diagram of the wafer being diced into a plurality of second chips according to another embodiment of the invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
It should be noted that the terms "upper", and the like used herein to denote a spatial orientation are based on the illustrated positional relationship, which for the purpose of facilitating the description, describes a relationship of one element or feature with respect to another element or feature as illustrated in the drawings; spatially relative terms may be intended to encompass different orientations of the product in use or operation in addition to the orientation depicted in the figures, such that if the product in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features.
Referring to fig. 3, fig. 4a and fig. 4b, a chip package structure 100 according to an embodiment of the present invention is illustrated by two chips (the first chip 10 and the second chip 20) in the drawings, but the number of chips is not limited thereto, and may be set to any number of two or more. For convenience of explanation, the second chip 20 is illustrated in a perspective view in fig. 3.
Specifically, the chip package structure 100 includes a first chip 10, a second chip 20, a lead frame, a plurality of leads 70, and a package material 60.
The lead frame includes a base island 30 and a plurality of pins 40 surrounding the base island 30.
Wherein the base island 30 is used for fixedly supporting the first chip 10 and the second chip 20.
Specifically, the first chip 10 is attached to the upper surface of the base island 30. In this embodiment, the first chip 10 is tightly adhered and fixed on the upper surface of the base island 30 by the die attach adhesive 80, on one hand, the die attach adhesive 80 can make no assembly joint between the first chip 10 and the base island 30, and on the other hand, the peripheral edge of the base island 11 has an area for the die attach adhesive 80 to overflow. Among them, the mounting adhesive 80 is preferably silver adhesive.
The lower surface of the first chip 10 is a non-electrical signal functional surface, and the lower surface of the first chip 10 is bonded and fixed to the upper surface of the base island 30.
Correspondingly, the upper surface of the first chip 10 is an electrical signal functional surface, that is, the upper surface of the first chip 10 may be provided with aluminum pads/other terminals for transmitting electrical signals. The upper surface of the first chip 10 is soldered with wires 70, so that an electrical signal transmission circuit is formed between the first chip 10 and other components (such as the second chip 20, the pins 40, etc.).
The second chip 20 is also relatively fixedly connected to the upper surface of the base island 30, which is disposed away from the upper surface of the base island 30 compared to the first chip 10. That is, the second chip 20 and the first chip 10 are both located above the base island 30, and the second chip 20 is elevated, and the distance between the lower surface of the second chip 20 and the upper surface of the base island 30 is greater than the distance between the lower surface of the first chip 10 and the upper surface of the base island 30. In this way, the layout of the second chip 20 and the first chip 10 in the up-down direction is hierarchical, thereby avoiding the wire-crossing problem as mentioned in the background art.
At least two of the pins 40, the first chip 10 and the second chip 20 are electrically connected by a wire 70, so as to form an electrical signal transmission circuit required by the chip package structure 10. In the present embodiment, any two of the pins 40, the first chip 10 and the second chip 20 are electrically connected through the wire 70.
Specifically, the upper surface of the pin 40 has a conductive film 41, and the lead 70 is soldered to the conductive film 41, so that the pin 40 is electrically connected to the first chip 10 and the pin 40 is electrically connected to the second chip 20. In the present embodiment, the conductive film 41 is preferably a silver-plated film, but is not limited thereto.
The encapsulant 60 is used to encapsulate the first chip 10, the second chip 20 and the wires 70, so as to protect the first chip 10, the second chip 20 and the wires 70. Preferably, the encapsulant 60 also covers the entire upper area of the lead frame, and the lower end surface thereof is flush with the lower surface of the lead frame, so that the encapsulant 60 encapsulates the first chip 10, the second chip 20 and the leads 70, and covers the upper surface of the base island 30 and the upper surfaces of the pins 30 at the same time, and the lower surfaces of the base island 30 and the lower surfaces of the pins 30 are exposed outside the encapsulant 60.
In the present invention, the chip package structure 100 further includes a substrate film layer 52 and a connection post 51.
The base film layer 52 is disposed on the lower surface of the second chip 20, and is firmly connected to the lower surface of the second chip 20. In practical applications, the substrate film layer 52 may be disposed on the entire lower surface of the second chip 20, or may be disposed on a partial lower surface of the second chip 20 as needed, which do not depart from the technical spirit of the present invention.
The number of the connecting columns 51 is set to be plural, and may specifically be any number of 3 or more than 3, and is illustrated as 9 in the drawings, but is not limited thereto; also, in the following description with reference to the drawings, any two connection columns 51 are exemplified with substantially the same structure, but not limited thereto, and some or all of the connection columns 51 may be configured to be different from each other without affecting the implementation effect.
The upper end of the connecting column 51 is planted on the base film layer 52, the connecting strength is high, the structure is stable and is not easy to fall off or break, and the connecting column can be planted on the base film layer 52 by adopting the technologies of electroplating, evaporation, sputtering, deposition and the like; the lower end of the connecting column 51 is welded to the upper surface of the base island 30, that is, the lower end of the connecting column 51 and the upper surface of the base island 30 are fixedly connected by welding, so that the connecting strength is high, and the structure is stable and is not easy to fall off or break.
Thus, by arranging the substrate film layer 52 and planting the plurality of connecting columns 51, the second chip 20 is fixedly mounted on the base island 30 through the connecting columns 51 while being elevated, and then the packaging material 60 can wrap around the connecting columns 51 and can fill in a gap S0 between the second chip 20 and the base island 30, so that gas in the gap S0 can be smoothly discharged in the wrapping process, the occurrence of a void phenomenon is avoided, and the product quality is ensured; in addition, the connecting column 51 can be stably connected with the second chip 20 and the base island 30, so that the connecting column 51 is prevented from falling off or shifting, and the product quality is further ensured.
Preferably, in an embodiment of the present invention, any two connection pillars 51 are separated from each other and do not contact each other, so that all areas of the space S0 between the second chip 20 and the base island 30 are communicated into a whole, which further ensures that the space S0 between the second chip 20 and the base island 30 can be effectively filled with the encapsulant 60 in the encapsulation process, thereby avoiding the void problem caused by the failure of gas exhaust.
Further, the upper surface of the second chip 20 is an electrical signal functional surface, that is, the upper surface of the second chip 20 may be provided with an aluminum pad/other terminal for transmitting electrical signals. The second chip 20 has a lead 70 bonded to its upper surface, so that an electrical signal transmission circuit is formed between the second chip 20 and other components (e.g., the first chip 10, the pins 40, etc.).
Correspondingly, the bottom surface of the second chip 20 is a non-electrical signal functional surface, and the bottom surface of the second chip 20 is formed with the base film layer 52 by a sputtering process, in other words, in the embodiment, the base film layer 52 is a sputtered metal film, specifically a sputtered copper film.
Further, the connection post 51 includes a metal post 511 and a bump 512.
The metal column 511 plays a role of supporting and fixing, forms the upper end of the connecting column 51, and can be specifically planted on the base film layer 52 by adopting the processes of electroplating, evaporation, sputtering, deposition and the like; in this embodiment, the metal pillar 511 may be a copper pillar.
The bumps 512 are planted at the lower ends of the metal posts 511, which form the lower ends of the connecting posts 51, and the connecting posts 51 are welded on the upper surface of the base island 30 through the bumps 512; in the present embodiment, the bumps 512 are solder balls.
Further, the distance between the lower surface of the second chip 20 and the upper surface of the base island 30 is not smaller than the distance between the upper surface of the first chip 10 and the upper surface of the base island 30. In other words, the second chip 20 is located above the first chip 10, a portion of the second chip 20 and a portion of the first chip 10 are overlapped up and down, and a chip-mounting adhesive 80 (such as silver paste) is filled between the second chip 20 and the first chip 10, so that the second chip 20 and the first chip 10 are fixedly assembled with each other and an assembly gap is avoided.
Further, an embodiment of the present invention further provides a manufacturing method of a chip package structure, which can be used to produce and manufacture the chip package structure 100, and certainly, under a varying implementation condition, a chip package structure product manufactured by using the manufacturing method may not be limited to the chip package structure 100. Referring now to fig. 5, the manufacturing method includes the steps of:
forming a base film layer on the first surface of the second chip;
planting a plurality of connecting columns on the substrate film layer;
attaching a first chip to the upper surface of the base island;
bonding the connection post to an upper surface of the base island to secure the second chip to the base island;
and encapsulating by using an encapsulating material to obtain the chip encapsulating structure.
In this way, by arranging the substrate film layer and planting the connecting columns, the chip (the second chip) to be erected is fixedly mounted on the base island through the connecting columns, so that the packaging material can wrap around the connecting columns and fill in the gap between the second chip and the base island, gas in the gap around the connecting columns in the packaging process can be smoothly discharged, the cavity phenomenon is avoided, and the product quality is ensured; in addition, the upper end of the connecting column is planted in the base film layer and the lower end of the connecting column is welded on the base island, so that the connecting column is strong in connection stability with the second chip and the base island, the connecting column is prevented from falling off or shifting, and product quality is further guaranteed.
In the manufacturing method, unless necessary dependencies exist, the execution sequence between the steps is not limited to the above-mentioned sequence: for example, although the step of "attaching the first chip to the upper surface of the base island" follows the step of "forming the base film layer on the first surface of the second chip" in the description language, the step of "attaching the first chip to the upper surface of the base island" is not limited to being performed later than the step of "forming the base film layer on the first surface of the second chip".
Next, taking the chip package structure 100 as an example, the steps of the manufacturing method will be described with reference to the embodiments shown in fig. 6 to fig. 16.
Step (1), forming a base film layer 52 on the first surface 201 of the second chip 20.
With respect to step (1), the second chip 20 includes a first surface 201 and a second surface which are oppositely disposed, the first surface 201 corresponds to a lower surface of the second chip 201 in the chip packaging structure 100, and is preferably a non-electrical signal functional surface of the second chip 20; correspondingly, the second surface of the second chip 20 corresponds to the upper surface of the second chip 201 in the chip package structure 100, and preferably, the electrical signal functional surface of the second chip 20, that is, the second surface may be provided with an aluminum pad/other terminal for transmitting electrical signals, so as to be soldered to the lead 70.
Specifically, step (1) includes the following substeps:
substep S1, pasting a film
Referring to fig. 6, a protective film 1 is attached to the second surface of the second chip 20, so that the second surface can be protected by the protective film 1 to prevent the electrical signal functions such as aluminum pads and terminals exposed on the second surface from being damaged in the subsequent step operation.
Substep S2, surface cleaning
Referring to fig. 7, after the protective film 1 is attached, on one hand, the first surface 201 of the second chip 20 is ground to flatten the first plane 201 and achieve the required chip thickness, and on the other hand, the first surface 201 of the second chip 20 is cleaned by ultrasonic waves to remove impurities and foreign matters from the first surface 201, so that preparation is made for forming the base film layer 52 on the first surface 201, and the forming effect and stability of the base film layer 52 are ensured; wherein preferably the ultrasonic cleaning can be carried out after the grinding is finished so as to clean the residues during the grinding.
Substep S3, plating film
Referring to fig. 8, after the surface of the first surface 201 of the second chip 20 is cleaned, the substrate film layer 52 is plated on the first surface 201, and the plated substrate film layer 52 can be stably connected to the first surface 201 of the second chip 20, which serves as a substrate for post implantation, so that the strength of the connection structure can be increased.
Preferably, the substrate film layer 52 can be formed on the first surface 201 by sputtering, which includes the following steps: argon is filled in a high vacuum state, the argon is ionized under the action of a strong electric field to generate argon positive ions, ion current with high energy is accelerated to bombard the surface of the target, and target atoms are sputtered (deposited) to the first surface 201 of the second chip 20 from the surface to form the substrate film layer 52.
Further preferably, the base film layer 52 is a sputtered metal film, especially a sputtered copper film.
In addition, the base film layer 52 is preferably arranged on almost the entire area of the first surface 201 of the second chip 20 as in this embodiment, but it is needless to say that the base film layer 52 may be arranged on a partial area of the first surface 201 of the second chip 20 as needed in a modified embodiment.
In step (2), a plurality of connecting posts 51 are implanted on the base film layer 52.
Regarding the step (2), the number of the connecting columns 51 is set to be plural, and may specifically be 3 or any number above 3, and is illustrated as 9 in the drawings, but is not limited thereto; also, in the following description with reference to the drawings, any two connection columns 51 are exemplified with substantially the same structure, but not limited thereto, and some or all of the connection columns 51 may be configured to be different from each other without affecting the implementation effect.
Specifically, step (2) includes the following substeps:
substep S4, covering with dry film
Referring to fig. 9, the photosensitive dry film 2 is disposed on the base film layer 52, and the photosensitive dry film 2 may be specifically formed on the base film layer 52 by a coating process; it is understood that the photosensitive dry film 2 is located on a side of the base film layer 52 facing away from the second chip 20, that is, the base film layer 52 is located between the photosensitive dry film 2 and the second chip 20.
Preferably, the photosensitive dry film 2 completely covers the entire base film layer 52.
Substep S5, patterning
Referring to fig. 10a and 10b, the photosensitive dry film 2 is subjected to divisional exposure development, so that the photosensitive dry film 2 is patterned to form a plurality of post-planting openings T exposing the substrate film layer 52; that is, the photosensitive dry film 2 is patterned by the divisional exposure and development technique, the patterned photosensitive dry film 2 has a plurality of post-planting openings T, the post-planting openings T expose the base film layer 52, and the remaining photosensitive dry film 2 except the post-planting openings T still covers and shields the base film layer 52.
Specifically, the detailed process of patterning may be: a graph is engraved on a photoetching plate, the photoetching plate is arranged on one side of the photosensitive dry film 2, and the photoetching plate can shield partial areas of the photosensitive dry film 2 and expose the rest areas of the photosensitive dry film 2 (namely, the areas where the column-planting openings T need to be formed); the photosensitive dry film 2 is exposed to high-intensity light and then developed, so that a partial region (i.e., a region where the post-planting opening T needs to be formed) of the photosensitive dry film 2 exposed to the light is removed, thereby patterning the photosensitive dry film 2.
Substep S6, planting the column
Referring to fig. 11, a metal pillar 511 and a bump 512 are sequentially implanted at the pillar-implanting opening T. Specifically, a metal pillar 511 may be implanted at the pillar-implanting opening T by electroplating, evaporation, sputtering, deposition, or other processes, and the metal pillar 511 is preferably a copper pillar; then, a bump 512 is implanted at the end of the metal pillar 511 (corresponding to the lower end of the metal pillar 511 in the chip package structure 100), wherein the bump 512 is preferably a solder ball.
It can be understood that, before the metal posts 511 are planted, the post openings T may be cleaned to remove the oxide and residues on the rear surface, so that the surface of the base film layer 52 exposed at the post openings T is clean, thereby meeting the requirement of post-planting and ensuring the connection strength between the metal posts 511 and the base film layer 52.
Substep S7, removing the dry film
Referring to fig. 12, after the post-implantation is completed, the photosensitive dry film 2 attached to the base film 52 is removed, specifically, it can be removed by mechanical peeling or cleaning.
After the above steps (1) and (2), the second chip 20 carrying the substrate film layer 52, the connection post 51 and the protection film 1 can be obtained for later use, and particularly, after the protection film 1 is removed, the second chip can be applied to the subsequent steps of the manufacturing method.
And (3) attaching the first chip 10 to the upper surface 301 of the base island 30 by using the chip attaching glue 80.
Referring to fig. 13, with reference to fig. 3, specifically, the die attach adhesive 80 is sprayed or applied at the center of the upper surface 301 of the base island 30, the die attach adhesive 80 may be silver paste, and then the first chip 10 is pressed against the die attach adhesive 80 to be attached to the upper surface 301 of the base island 30, during the pressing process, the die attach adhesive 80 fills the gap between the lower surface of the first chip 10 and the upper surface 301 of the base island 30, so as to avoid the formation of an assembly gap.
The lower surface of the first chip 10 is a non-electrical signal functional surface, and is adhered to the upper surface of the base island 30 and covered by the die attach adhesive 80. Correspondingly, the upper surface of the first chip 10 is an electrical signal functional surface, that is, the upper surface of the first chip 10 may be provided with aluminum pads/other terminals for transmitting electrical signals for bonding the leads 70.
Further, in this step (3), a die attach adhesive 80 may be applied to a local area of the upper surface 101 of the first chip 10 to assist in fixing the second chip 20 and avoiding the generation of an assembly gap (see below).
Step (4), the connection post 51 is soldered to the upper surface 301 of the base island 30, so that the second chip 20 is fixed to the base island 30.
Referring to fig. 14, specifically, the second chip 20 processed in the foregoing steps (1) and (2) (i.e., the second chip 20 carrying the base film layer 52 and the connection post 51) is peeled off from the protective film 1 and attached to the upper side of the base island 30; that is, the connection post 51 is disposed above the base island 30 so as to be on the lower second chip 20.
In the specific implementation, the chip-mounting adhesive 80 is filled between the positions where the second chip 20 and the first chip 10 are overlapped up and down, so as to stabilize the mounting position of the second chip 20 and avoid assembly gaps; moreover, the lower end of the connecting column 51 is welded to the upper surface 301 of the base island 30, specifically, the bump 512 of the connecting column 51 is welded to the base island 30, so that the position of the connecting column 51 can be ensured to be stable through welding connection.
It can be understood that, by the connection posts 51, the second chip 20 is elevated compared to the first chip 20, the distance between the lower surface of the second chip 20 and the upper surface 301 of the base island 30 is greater than the distance between the lower surface of the first chip 10 and the upper surface 301 of the base island 30, and a space S0 surrounding the connection posts 51 is formed between the second chip 20 and the base island 30.
And (5) establishing electrical connection among at least two of the first chip 10, the second chip 20 and the pins 40 through leads 70.
Referring to fig. 15, in the present embodiment, the upper surface of the pin 40 has the conductive film 41, and the pin 40 and the first chip 10, the pin 40 and the second chip 20, and the first chip 10 and the second chip 20 are electrically connected by bonding the wire 70. In the present embodiment, the conductive film 41 is preferably a silver-plated film, but is not limited thereto.
And (6) encapsulating by using the encapsulating material 60 to obtain the chip encapsulating structure 100.
Wherein the base island 30 and the pins 40 constitute at least part of a lead frame; referring to fig. 16, the encapsulant 60 covers the entire upper area of the lead frame, and the lower end surface of the encapsulant 60 is flush with the lower surface of the lead frame, and in the illustrated example, the lower end surface of the encapsulant 60 is flush with the lower surface of the base island 30, so that the encapsulant 60 encapsulates the first chip 10, the second chip 20, and the leads 70 and covers the upper surface 301 of the base island 30 and the upper surfaces of the pins 30, and the lower surfaces of the base island 30 and the pins 30 are exposed outside the encapsulant 60.
Thus, the chip packaging structure 100 can be manufactured, and thus, the substrate film layer 52 is arranged on the lower surface of the second chip 20 and the plurality of connecting columns 51 are implanted, so that the second chip 20 is fixedly mounted on the base island 30 through the connecting columns 51 while being elevated, and in the encapsulating process in the manufacturing process, the encapsulating material 60 is wrapped around the connecting columns 51 and can be filled into the gap S0 between the second chip 20 and the base island 30, so that the gas in the gap S0 can be smoothly discharged in the encapsulating process, the occurrence of a void phenomenon is avoided, and the product quality is ensured; in addition, the connection post 52 can be stably connected with the second chip 20 and the base island 30, so that the connection post 30 is prevented from falling off or shifting, and further, the product quality is ensured.
Further preferably, any two connecting posts 51 are separated from each other and do not contact with each other, so that all areas of the space S0 between the second chip 20 and the base island 30 are communicated into a whole, which further ensures that the space S0 between the second chip 20 and the base island 30 can be effectively filled with the encapsulating material 60 in the encapsulating process, and avoids the void problem caused by the fact that gas cannot be discharged.
It should be reiterated that, in the present application, unless there is a necessary dependency relationship, the execution sequence between the steps of the manufacturing method is not limited to the above-described sequence, and the numbering of the steps such as "S1", "S2", "1", "2" and the like performed for the convenience of description herein does not mean the execution sequence of the steps, and the manufacturing method can execute the steps in a reasonably feasible sequence. For example, although step (1) is located before step (3) in the order of language, it is not limited that step (1) is performed prior to step (3); for example, although step (2) is located between step (1) and step (3) in the numbering, it is not limited to the step (1), step (2), and step (3) being performed in this order.
In addition, in the embodiments shown in fig. 6 to 12, the step (1) and the step (2) are exemplified by the single second chip 20. Of course, in a variation, the steps (1) and (2) are also preferably performed in a manner that a plurality of second chips 20 are integrated on the same wafer and are performed in bulk synchronously, that is, the same wafer includes a plurality of second chips 20, and the operations of the steps (1) and/or (2) are performed synchronously on the plurality of second chips 20, so that the production efficiency can be improved; correspondingly, referring to fig. 17, after steps (1) and (2) are performed, before step (4), the wafer may be diced into a plurality of second chips 20 carrying a base film layer 52 and a plurality of connection pillars 51, that is, the plurality of second chips 20 are diced from the wafer, so as to facilitate the assembly of the second chips 20 and the base islands 30 in step (4).
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (7)
1. A chip packaging structure comprises a base island, packaging materials, a first chip and a second chip, wherein the first chip is attached to the upper surface of the base island, the second chip is arranged far away from the upper surface of the base island compared with the first chip; the connecting columns comprise metal copper columns and tin ball bumps implanted at the lower ends of the metal copper columns, and any two connecting columns are separated from each other and are not in contact with each other; the upper end of the connecting column is planted in the base film layer, the lower end of the connecting column is welded to the upper surface of the base island through the convex spot, and the packaging material encapsulates the first chip and the second chip and is filled between the base island and the second chip.
2. The chip package structure according to claim 1, wherein the upper surface of the second chip is an electrical signal functional surface; the upper surface of the first chip is an electrical signal functional surface;
the packaging structure further comprises a pin, and electrical connection is established among any two of the second chip, the pin and the first chip through a lead;
the encapsulant also encapsulates the leads and covers the upper surfaces of the pins.
3. The chip package structure according to claim 1, wherein the first chip is mounted on the upper surface of the base island by a die attach adhesive;
and a part of the second chip and a part of the first chip are arranged in an up-and-down overlapping manner, and a mounting adhesive is filled between the second chip and the first chip.
4. A method for manufacturing a chip package structure includes:
forming a base film layer on the first surface of the second chip, wherein the base film layer is set as a sputtering metal film;
sequentially planting a metal copper column and a tin ball bump on the substrate film layer to obtain a plurality of connecting columns, wherein any two connecting columns are separated from each other and are not in contact with each other;
attaching a first chip to the upper surface of the base island;
welding the connecting column to the upper surface of the base island through the bump to fixedly mount the second chip to the base island;
and encapsulating by using an encapsulating material to obtain the chip encapsulating structure.
5. The method for manufacturing the chip package structure according to claim 4, wherein the step of forming the substrate film layer on the first surface of the second chip comprises:
attaching a protective film to a second surface of a second chip, wherein the second surface is opposite to the first surface and is an electrical signal functional surface of the second chip;
grinding and ultrasonically cleaning the first surface of the second chip;
and sputtering and forming a base film layer on the first surface of the second chip.
6. The method for manufacturing a chip package structure according to claim 4, wherein the step of implanting a copper pillar and a solder bump on the substrate film in sequence to obtain a plurality of connection posts comprises:
laying a photosensitive dry film on the substrate film layer;
carrying out partition exposure development on the photosensitive dry film to pattern a plurality of column planting openings exposing the substrate film layer on the photosensitive dry film;
sequentially planting a metal copper column and a tin ball salient point at the column planting opening to obtain a connecting column;
and removing the photosensitive dry film from the substrate film layer implanted with the connecting column.
7. The method for manufacturing the chip package structure according to claim 4, wherein before the encapsulating with the encapsulant, at least two of the first chip, the second chip and the pins are electrically connected by wires;
the method comprises the steps of forming a base film layer on a first surface of a second chip, and planting a copper metal column and a tin ball bump on the base film layer in sequence to obtain a plurality of connecting columns, wherein a plurality of second chips are integrated on the same wafer and are synchronously carried out in batch; and dicing the plurality of second chips from the wafer before the step of bonding the connection posts to the upper surface of the base island to secure the second chips to the base island.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910536027.5A CN112117242B (en) | 2019-06-20 | 2019-06-20 | Chip packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910536027.5A CN112117242B (en) | 2019-06-20 | 2019-06-20 | Chip packaging structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112117242A CN112117242A (en) | 2020-12-22 |
| CN112117242B true CN112117242B (en) | 2023-01-31 |
Family
ID=73795861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910536027.5A Active CN112117242B (en) | 2019-06-20 | 2019-06-20 | Chip packaging structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112117242B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116153870A (en) * | 2023-04-21 | 2023-05-23 | 江苏长晶浦联功率半导体有限公司 | Stacked packaging structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1638118A (en) * | 2004-01-08 | 2005-07-13 | 松下电器产业株式会社 | Semiconductor apparatus |
| CN101207114A (en) * | 2006-12-20 | 2008-06-25 | 富士通株式会社 | Semiconductor device and manufacturing method of the same |
| CN101661931A (en) * | 2008-08-20 | 2010-03-03 | 桑迪士克股份有限公司 | Semiconductor die support in an offset die stack |
| US20160035712A1 (en) * | 2011-10-20 | 2016-02-04 | Invensas Corporation | Microelectronic package with stacked microelectronic units and method for manufacture thereof |
-
2019
- 2019-06-20 CN CN201910536027.5A patent/CN112117242B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1638118A (en) * | 2004-01-08 | 2005-07-13 | 松下电器产业株式会社 | Semiconductor apparatus |
| CN101207114A (en) * | 2006-12-20 | 2008-06-25 | 富士通株式会社 | Semiconductor device and manufacturing method of the same |
| CN101661931A (en) * | 2008-08-20 | 2010-03-03 | 桑迪士克股份有限公司 | Semiconductor die support in an offset die stack |
| US20160035712A1 (en) * | 2011-10-20 | 2016-02-04 | Invensas Corporation | Microelectronic package with stacked microelectronic units and method for manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112117242A (en) | 2020-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100616670B1 (en) | Image sensor module of chip scale and method of fabricating the same | |
| KR100301357B1 (en) | Semiconductor device and its manufacturing method and lead frame manufacturing method | |
| US6559528B2 (en) | Semiconductor device and method for the fabrication thereof | |
| US6774467B2 (en) | Semiconductor device and process of production of same | |
| JP3007833B2 (en) | Semiconductor device and its manufacturing method, lead frame and its manufacturing method | |
| US7576402B2 (en) | Semiconductor device, method of manufacturing the same, and camera module | |
| US8766408B2 (en) | Semiconductor device and manufacturing method thereof | |
| US8222080B2 (en) | Fabrication method of package structure | |
| US6717252B2 (en) | Semiconductor device | |
| JP2002184904A (en) | Semiconductor device and method for manufacturing the same | |
| GB2556255A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| US20040127011A1 (en) | [method of assembling passive component] | |
| CN112117242B (en) | Chip packaging structure and manufacturing method thereof | |
| JP7001445B2 (en) | Semiconductor devices and their manufacturing methods | |
| JPH11163204A (en) | Semiconductor device and mounting structure thereof | |
| JP2004235420A (en) | Electronic device, manufacturing method thereof, circuit board, manufacturing method thereof, electronic device, and manufacturing method thereof | |
| KR101064571B1 (en) | Method for manufacturing wiring board | |
| KR102651266B1 (en) | Selective emi shielding using preformed mask with fang design | |
| US5933711A (en) | Fabrication method for chip size semiconductor package | |
| JP4078760B2 (en) | Manufacturing method of chip-type electronic component | |
| KR101134706B1 (en) | Leadframe and method for manufacturing the same | |
| CN114649226B (en) | Selective EMI shielding using preformed masks with cusp designs | |
| CN114361051B (en) | Multi-chip normal-mounting reset wafer-level packaging structure and method | |
| KR0185514B1 (en) | Chip scale package and method of making the same | |
| JP3723524B2 (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |