CN114121649A - Manufacturing method of semiconductor device, memory and storage system - Google Patents

Manufacturing method of semiconductor device, memory and storage system Download PDF

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Publication number
CN114121649A
CN114121649A CN202111402336.7A CN202111402336A CN114121649A CN 114121649 A CN114121649 A CN 114121649A CN 202111402336 A CN202111402336 A CN 202111402336A CN 114121649 A CN114121649 A CN 114121649A
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China
Prior art keywords
layer
opening
sub
forming
insulating layer
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Chinese (zh)
Inventor
姚森
王猛
朱宏斌
张高升
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202111402336.7A priority Critical patent/CN114121649A/en
Publication of CN114121649A publication Critical patent/CN114121649A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The embodiment of the invention discloses a manufacturing method of a semiconductor device, the semiconductor device, a memory and a storage system. The method comprises the following steps: providing a stop layer and an insulating layer on the stop layer; forming a mask layer with an opening on the insulating layer; forming a sacrificial layer on the mask layer, wherein the sacrificial layer covers the side wall and the bottom surface of the opening so as to form a groove with a concave bottom surface in the opening in a surrounding manner; through the concave bottom surface, a through hole is formed in the insulating layer. The embodiment of the invention can reduce the process difficulty and accurately reduce the size of the through hole.

Description

Manufacturing method of semiconductor device, memory and storage system
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device, the semiconductor device, a memory and a storage system.
Background
At present, a method for manufacturing a through hole in a semiconductor device is to form a mask layer on an insulating layer and etch the through hole in the insulating layer through an opening in the mask layer. However, if the size of the required through hole is small, the size of the opening in the mask layer needs to be reduced to a target size, which requires a high process requirement. Therefore, how to reduce the size of the via without reducing the size of the opening in the mask layer is an urgent problem to be solved.
Disclosure of Invention
Embodiments of the present invention provide a method for manufacturing a semiconductor device, a memory, and a storage system, which can reduce process difficulty and accurately reduce the size of a through hole.
The embodiment of the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a stop layer and an insulating layer on the stop layer;
forming a mask layer with an opening on the insulating layer;
forming a sacrificial layer on the mask layer, wherein the sacrificial layer covers the side wall and the bottom surface of the opening so as to form a groove with a concave bottom surface in the opening in a surrounding manner;
through the concave bottom surface, a through hole is formed in the insulating layer.
Further, the lateral width of the through hole is smaller than that of the concave bottom surface, and the lateral direction is a direction parallel to the upper surface of the stop layer.
Further, the mask layer comprises an anti-reflection layer and a photoresist layer, and the opening comprises a first sub-opening and a second sub-opening;
the step of forming a mask layer having an opening on the insulating layer includes:
sequentially forming the anti-reflection layer and the photoresist layer on the insulating layer, wherein the photoresist layer is provided with the first sub-opening;
forming the second sub-opening communicating with the first sub-opening in the anti-reflection layer through the first sub-opening.
Further, the step of forming a sacrificial layer on the mask layer, where the sacrificial layer covers the side wall and the bottom surface of the opening to form a groove having a concave bottom surface in the opening includes:
removing the photoresist layer;
forming the sacrificial layer on the anti-reflection layer, wherein the sacrificial layer covers the side wall and the bottom surface of the second sub-opening to form the groove with the concave bottom surface in the second sub-opening.
Furthermore, the mask layer also comprises a hard mask layer positioned between the insulating layer and the anti-reflection layer;
the step of forming a via hole in the insulating layer through the recessed bottom surface includes:
and etching the sacrificial layer, the hard mask layer and the insulating layer corresponding to the concave bottom surface to form the through hole in the insulating layer.
Furthermore, the mask layer also comprises a hard mask layer positioned between the insulating layer and the antireflection layer, and the opening also comprises a third sub-opening;
the step of forming a mask layer having an opening on the insulating layer further includes:
and forming the third sub-opening communicated with the second sub-opening in the hard mask layer through the second sub-opening.
Further, the step of forming a sacrificial layer on the mask layer, where the sacrificial layer covers the side wall and the bottom surface of the opening to form a groove having a concave bottom surface in the opening includes:
removing the photoresist layer;
forming the sacrificial layer on the antireflection layer, wherein the sacrificial layer covers the side wall of the second sub-opening and the side wall and the bottom surface of the third sub-opening to form the groove with the concave bottom surface in the second sub-opening and the third sub-opening.
Further, the step of forming a sacrificial layer on the mask layer, where the sacrificial layer covers the side wall and the bottom surface of the opening to form a groove having a concave bottom surface in the opening includes:
removing the photoresist layer and the anti-reflection layer;
and forming the sacrificial layer on the hard mask layer, wherein the sacrificial layer covers the side wall and the bottom surface of the third sub-opening so as to enclose the groove with the concave bottom surface in the third sub-opening.
Further, the step of forming a via hole in the insulating layer through the recessed bottom surface includes:
and etching the sacrificial layer and the insulating layer corresponding to the concave bottom surface to form the through hole in the insulating layer.
An embodiment of the present invention further provides a semiconductor device, including:
a stop layer;
an insulating layer on the stop layer;
and the through structure penetrates through the insulating layer, the transverse width of the through structure is smaller than the preset width, and the transverse direction is parallel to the direction of the upper surface of the stop layer.
The embodiment of the invention also provides a memory, which comprises a memory array structure and a peripheral structure connected with the memory array structure;
at least one of the memory array structure and the peripheral structure includes the above semiconductor device.
The embodiment of the invention also provides a storage system which comprises the storage and a controller connected with the storage.
The invention has the beneficial effects that: the method comprises the steps of forming a mask layer with an opening on an insulating layer, forming a sacrificial layer on the mask layer, enabling the sacrificial layer to cover the side wall and the bottom surface of the opening, and forming a groove with a concave bottom surface in the opening in a surrounding mode.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a method of fabricating a semiconductor device in some embodiments;
fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3a to fig. 3d are schematic structural diagrams corresponding to a manufacturing method of a semiconductor device according to an embodiment of the invention;
fig. 4a to fig. 4c are schematic structural diagrams corresponding to a manufacturing method of a semiconductor device according to an embodiment of the invention;
fig. 5a to fig. 5c are schematic structural diagrams corresponding to a manufacturing method of a semiconductor device according to an embodiment of the invention;
FIG. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention
FIG. 7 is a schematic structural diagram of a memory according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a storage system according to an embodiment of the present invention.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As shown in fig. 1, in some embodiments, after forming a stop layer 1a and an insulating layer 2a on the stop layer 1a, a mask layer 3a is formed on the insulating layer 2a, the mask layer 3a including a hard mask layer 31a, an anti-reflection layer 32a and a photoresist layer 33a sequentially on the insulating layer 2a, the photoresist layer 33a having an opening 34 a. Then, the antireflection layer 32a, the hard mask layer 31a, and the insulating layer 2a are etched by an exposure development technique through the opening 34a to form a via hole 21a in the insulating layer 2 a. If the through hole 21a with a smaller size needs to be formed in the insulating layer 2a, the size of the opening 34a in the mask layer 3a needs to be reduced, but the reduction of the size of the opening 34a has higher requirements for a machine, which results in higher process difficulty.
Accordingly, the embodiment of the invention provides a manufacturing method of a semiconductor device. Fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
As shown in fig. 2, an embodiment of the present invention provides a method for manufacturing a semiconductor device, where the method includes steps 101 to 104, and specifically includes the following steps:
step 101, providing a stop layer, and an insulating layer on the stop layer.
As shown in fig. 3a, the stop layer 1 may be a conductive layer, such as a metal layer, including but not limited to tungsten, cobalt, copper, aluminum, etc. The stop layer 1 may be a semiconductor substrate, for example, a silicon substrate, or a substrate including another element semiconductor or a compound semiconductor. The stop layer 1 may be another film layer different from the insulating layer, and is not particularly limited herein.
An insulating layer 2 is formed on the stop layer 1 by a thin film deposition process, and the insulating layer 2 includes, but is not limited to, any one or more of silicon oxide, silicon nitride, and silicon oxynitride. The thin film deposition process may be physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, or the like.
Step 102, forming a mask layer with an opening on the insulating layer.
A mask layer is formed on the insulating layer 2, the mask layer having an opening therein. The opening may or may not penetrate the mask layer, i.e., the depth of the opening is less than the thickness of the mask layer.
In some embodiments, as shown in fig. 3a, masking layer 3 includes a photoresist layer 31 and an anti-reflective layer 32, anti-reflective layer 32 is on insulating layer 2, and photoresist layer 31 is on anti-reflective layer 32. The anti-reflection layer 32 includes, but is not limited to, silicon oxynitride SiON.
The opening in mask layer 3 may extend through mask layer 3, i.e. the opening extends through photoresist layer 31 and antireflective layer 32. Specifically, the opening may include a first sub-opening and a second sub-opening, and the forming a mask layer having an opening on the insulating layer in step 102 includes:
sequentially forming the anti-reflection layer and the photoresist layer on the insulating layer, wherein the photoresist layer is provided with the first sub-opening;
forming the second sub-opening communicating with the first sub-opening in the anti-reflection layer through the first sub-opening.
As shown in fig. 3a, the photoresist layer 31 has a first sub-opening 30a therein. The width of the first sub-opening 30a in the lateral direction (i.e. the direction a parallel to the upper surface of the stop layer 1) may be the same as the width of the opening 34a of the photoresist layer 33a in fig. 1, i.e. the embodiment of the present invention does not need to reduce the size of the opening in the photoresist layer 31, thereby reducing the process difficulty. When the cross-section of the first sub-opening 30a is circular, the lateral width of the first sub-opening 30a may refer to the diameter of the first sub-opening 30 a.
As shown in fig. 3b, a second sub-opening 30b is formed in the anti-reflection layer 32 through the first sub-opening 30a, the second sub-opening 30b penetrates the anti-reflection layer 32, and the second sub-opening 30b is communicated with the first sub-opening 30 a.
The first sub opening 30a and the second sub opening 30b together constitute the opening 30.
Step 103, forming a sacrificial layer on the mask layer, wherein the sacrificial layer covers the side wall and the bottom surface of the opening so as to form a groove with a concave bottom surface in the opening in a surrounding manner.
As shown in fig. 3c, the sacrificial layer 4 may be formed directly on the photoresist layer 31, and the sacrificial layer 4 covers the sidewall of the first sub-opening 30a and the sidewall and the bottom surface of the second sub-opening 30b, so that the sacrificial layer 4 encloses a groove 40 having a concave bottom surface 41 in the opening 30. The sidewall of the first sub-opening 30a is a photoresist layer 31, the sidewall of the second sub-opening 30b is an anti-reflection layer 32, and the bottom surface of the second sub-opening 30b is an insulating layer 2. Since the sacrificial layer 4 has a certain thickness, the lateral width of the groove 40 is smaller than the lateral width of the opening 30. The sacrificial layer 4 includes, but is not limited to, any one or combination of silicon oxide, silicon nitride, and silicon oxynitride.
The sacrificial Layer 4 is formed on the photoresist Layer 31 by an Atomic Layer Deposition (ALD) process, and by controlling the thickness of the sacrificial Layer 4, the lateral width of the enclosed groove 40, that is, the lateral width of the bottom surface 41, can be controlled. The larger the thickness of the sacrificial layer 4, the smaller the lateral width of the groove 40, but the thickness of the sacrificial layer 4 cannot be too thick, i.e. the lateral width of the groove 40 cannot be too small, at least the groove 40 is required to have a concave bottom surface 41.
It should be noted that, because the photoresist layer 31 has good fluidity, if the second sub-opening 30b is not formed in the anti-reflection layer 32, the sacrificial layer 4 is directly formed on the photoresist layer 31, so that the sacrificial layer 4 only covers the sidewall and the bottom surface of the first sub-opening 30a, which easily causes the photoresist layer 31 to collapse, so that the sacrificial layer 4 cannot enclose the groove 40 having the concave bottom surface 41 in the first sub-opening 30a, or the groove 40 enclosed by the sacrificial layer 4 in the first sub-opening 30a is uncontrollable, which is not favorable for etching the subsequent via. Therefore, in the present embodiment, the second sub-opening 30b is formed in the anti-reflection layer 32, so that the sacrificial layer 4 is located on the photoresist layer 31 and covers the sidewall of the first sub-opening 30a and the sidewall and the bottom of the second sub-opening 30b, even if the photoresist layer 31 is collapsed, the formation of the groove 40 is not affected due to the anti-reflection layer 32, and the lateral width of the bottom surface 41 of the groove 40 can be controlled.
To further ensure the formation and controllability of the recess 40, the photoresist layer 31 may also be removed after the second sub-opening 30b is formed in the anti-reflection layer 32. Specifically, the forming a sacrificial layer on the mask layer in step 103, where the sacrificial layer covers a sidewall and a bottom surface of the opening to form a groove with a concave bottom surface in the opening, includes:
removing the photoresist layer;
forming the sacrificial layer on the anti-reflection layer, wherein the sacrificial layer covers the side wall and the bottom surface of the second sub-opening to form the groove with the concave bottom surface in the second sub-opening.
After forming the second sub-opening 30b in the anti-reflection layer 32, the photoresist layer 31 is removed, and the mask layer 3 includes only the anti-reflection layer 32, and the opening 30 includes only the second sub-opening 30 b. Then, the sacrificial layer 4 is formed on the antireflection layer 32, and the sacrificial layer 4 covers only the sidewalls and the bottom surface of the second sub-opening 30b, so that the sacrificial layer 4 forms the groove 40 having the concave bottom surface 41 only in the second sub-opening 30 b.
And 104, forming a through hole in the insulating layer through the concave bottom surface.
The corresponding film layer (excluding the stop layer 1) at the bottom of the concave bottom surface 41 is etched using an anisotropic etching process to form the via hole 20 in the insulating layer 2.
As shown in fig. 3c, the corresponding film layers at the bottom of the concave bottom surface 41 are the sacrificial layer 4 and the insulating layer 2. As shown in fig. 3d, the sacrificial layer 4 and the insulating layer 2 corresponding to the concave bottom surface 41 are etched by using an anisotropic etching process, and the etching is stopped at the stop layer 1, so that the through hole 20 is formed in the insulating layer 2.
The lateral width of the through-hole 20 is smaller than the lateral width of the depressed bottom surface 41. Since the sidewalls of the via 20 may be inclined such that the lateral widths of the top (i.e., the side of the via 20 facing away from the stop layer 1) and the bottom (i.e., the side of the via closer to the stop layer) of the via 20 may be different, the lateral width of the via 20 in this embodiment may refer to the maximum lateral width of the via 20, such as the lateral width of the top of the via 20. When the cross-section of the through-hole 20 is circular, the lateral width of the through-hole 20 may refer to the diameter of the top of the through-hole 20.
It should be noted that the larger the thickness of the sacrificial layer 4, the smaller the lateral width of the groove 40, i.e., the lateral width of the recessed bottom surface 41, and the smaller the lateral width of the through hole 20 (i.e., the size of the through hole 20). In this embodiment, the size of the opening 30 in the mask layer 3 does not need to be reduced, and the size of the through hole 20 in the insulating layer 2 can be reduced without adding a transfer layer between the mask layer 3 and the insulating layer 2, so that the process difficulty is reduced, and the reduced size of the through hole 20 is ensured to be accurate and controllable.
In other embodiments, masking layer 3 includes a photoresist layer 31, an anti-reflective layer 32, and a hard mask layer 33, where hard mask layer 33 is on insulating layer 2, anti-reflective layer 32 is on hard mask layer 33, and photoresist layer 31 is on anti-reflective layer 32. The anti-reflective layer 32 includes, but is not limited to, silicon oxynitride SiON, and the hard mask layer 33 includes, but is not limited to, amorphous carbon.
In one embodiment, as shown in fig. 4a, the opening 30 in the mask layer 3 may penetrate through the photoresist layer 31 and the anti-reflection layer 32, but not through the hard mask layer 33, i.e., the opening 30 includes a first sub-opening 30a and a second sub-opening 30b communicating with each other, the first sub-opening 30a penetrates through the photoresist layer 31, and the second sub-opening penetrates through the anti-reflection layer 32. The forming method of the first sub-opening 30a and the second sub-opening 30b is the same as the forming method of the first sub-opening 30a and the second sub-opening 30b in the above embodiment, and detailed description thereof is omitted.
Then, as shown in fig. 4b, the sacrificial layer 4 may be formed directly on the photoresist layer 31, and the sacrificial layer 4 covers the sidewalls of the first sub-opening 30a and the sidewalls and the bottom surface of the second sub-opening 30b, so that the sacrificial layer 4 surrounds the groove 40 in the first sub-opening 30a and the second sub-opening 30 b. The sidewall of the first sub-opening 30a is a photoresist layer 31, the sidewall of the second sub-opening 30b is an anti-reflection layer 32, and the bottom surface of the second sub-opening 30b is a hard mask layer 33. Since the sacrificial layer 4 has a certain thickness, the lateral width of the concave bottom surface 41 of the groove 40 is smaller than the lateral width of the opening 30.
The photoresist layer 31 in the mask layer 3 may also be removed before the sacrificial layer 4 is formed. At this time, the mask layer 3 includes the anti-reflection layer 32 and the hard mask layer 33, and the opening 30 includes the second sub-opening 30 b. Then, the sacrificial layer 4 is formed on the anti-reflection layer 32, and the sacrificial layer 4 covers the sidewalls and the bottom surface of the second sub-opening 30b, so that the sacrificial layer 4 forms the groove 40 having the concave bottom surface 41 only in the second sub-opening 30 b.
The corresponding film layers at the bottom of the concave bottom surface 41 are the sacrificial layer 4, the hard mask layer 33 and the insulating layer 2. As shown in fig. 4c, the sacrificial layer 4, the hard mask layer 33 and the insulating layer 2 corresponding to the concave bottom surface 41 are etched by using an anisotropic etching process, and the etching is stopped at the stop layer 1, so that the through hole 20 is formed in the insulating layer 2.
The lateral width of the recessed bottom surface 41 is smaller than the lateral width of the opening 30 in the mask layer 3, and the lateral width of the via hole 20 is smaller than the lateral width of the recessed bottom surface 41, thereby effectively reducing the lateral width (i.e., size) of the via hole 20.
In another embodiment, as shown in fig. 5a, the opening 30 in the mask layer 3 may penetrate through the photoresist layer 31, the anti-reflection layer 32 and the hard mask layer 33, i.e. the opening 30 includes a first sub-opening 30a, a second sub-opening 30b and a third sub-opening 30c communicating with each other. The forming method of the first sub-opening 30a and the second sub-opening 30b is the same as the forming method of the first sub-opening 30a and the second sub-opening 30b in the above embodiments, and detailed description thereof is omitted here. After the second sub-openings 30b are formed, third sub-openings 30c communicating with the second sub-openings 30b are formed in the hard mask layer 33 through the second sub-openings 30b, i.e., the third sub-openings 30c penetrate through the hard mask layer 33.
Then, as shown in fig. 5b, the sacrificial layer 4 may be directly formed on the photoresist layer 31, and the sacrificial layer 4 covers the sidewalls of the first sub-opening 30a, the sidewalls of the second sub-opening 30b, and the sidewalls and the bottom surface of the third sub-opening 30c, so that the sacrificial layer 4 encloses a groove 40 in the first sub-opening 30a, the second sub-opening 30b, and the third sub-opening 30 c. The sidewall of the first sub-opening 30a is a photoresist layer 31, the sidewall of the second sub-opening 30b is an anti-reflection layer 32, the sidewall of the third sub-opening 30c is a hard mask layer 33, and the bottom of the third sub-opening 30c is an insulating layer 2. Since the sacrificial layer 4 has a certain thickness, the lateral width of the concave bottom surface 41 of the groove 40 is smaller than the lateral width of the opening 30.
The photoresist layer 31 in the mask layer 3 may also be removed before the sacrificial layer 4 is formed. At this time, the mask layer 3 includes the anti-reflection layer 32 and the hard mask layer 33, and the opening 30 includes the second sub-opening 30b and the third sub-opening 30 c. Specifically, the forming a sacrificial layer on the mask layer in step 103, where the sacrificial layer covers a sidewall and a bottom surface of the opening to form a groove with a concave bottom surface in the opening, includes:
removing the photoresist layer;
forming the sacrificial layer on the antireflection layer, wherein the sacrificial layer covers the side wall of the second sub-opening and the side wall and the bottom surface of the third sub-opening to form the groove with the concave bottom surface in the second sub-opening and the third sub-opening.
After the third sub-opening 30c is formed in the hard mask layer 33, the photoresist layer 31 is removed, and then the sacrificial layer 4 is formed on the anti-reflection layer 32, and the sacrificial layer 4 covers the sidewall of the second sub-opening 30b and the sidewall and the bottom surface of the third sub-opening 30c, so that the sacrificial layer 4 forms the groove 40 having the concave bottom surface 41 only in the second sub-opening 30b and the third sub-opening 30 c.
The photoresist layer 31 and the anti-reflection layer 32 in the mask layer 3 may also be removed before the sacrificial layer 4 is formed. At this time, the mask layer 3 includes the hard mask layer 33, and the opening 30 includes the third sub-opening 30 c. Specifically, the forming a sacrificial layer on the mask layer in step 103, where the sacrificial layer covers a sidewall and a bottom surface of the opening to form a groove with a concave bottom surface in the opening, includes:
removing the photoresist layer and the anti-reflection layer;
and forming the sacrificial layer on the hard mask layer, wherein the sacrificial layer covers the side wall and the bottom surface of the third sub-opening so as to enclose the groove with the concave bottom surface in the third sub-opening.
After the third sub-opening 30c is formed in the hard mask layer 33, the photoresist layer 31 and the anti-reflection layer 32 are removed, and then the sacrificial layer 4 is formed on the hard mask layer 33, and the sacrificial layer 4 covers the sidewall and the bottom surface of the third sub-opening 30c, so that the sacrificial layer 4 forms the groove 40 having the concave bottom surface 41 only in the third sub-opening 30 c.
At this time, the corresponding film layers at the bottom of the concave bottom surface 41 are the sacrificial layer 4 and the insulating layer 2. As shown in fig. 5c, the sacrificial layer 4 and the insulating layer 2 corresponding to the concave bottom surface 41 are etched by using an anisotropic etching process, and the etching is stopped at the stop layer 1, so that the through hole 20 is formed in the insulating layer 2.
After the via hole 20 is formed in the insulating layer 2, the remaining sacrificial layer 4 and mask layer 3 may be removed. Then, the through structure 5 is formed in the through hole 20 as shown in fig. 6. When the stop layer 1 is a conductive layer, the through structure 5 may be a contact point, and the through structure 5 may be connected to the stop layer 1. Another conductive layer may be formed on the insulating layer 2, so that the other conductive layer is electrically connected to the stop layer 1 through the through structure 5. Connection contacts include, but are not limited to, tungsten, cobalt, copper, aluminum, and the like.
The method for manufacturing the semiconductor device, provided by the embodiment of the invention, comprises the steps of forming a mask layer with an opening on an insulating layer, forming a sacrificial layer on the mask layer, enabling the sacrificial layer to cover the side wall and the bottom surface of the opening to form a groove with a concave bottom surface in the opening in a surrounding manner, and forming a through hole in the insulating layer through the concave bottom surface because the transverse width of the concave bottom surface is smaller than that of the opening, so that the size of the through hole can be reduced, the size of the opening in the mask layer does not need to be reduced, the process difficulty is reduced, and in addition, the transverse width of the concave bottom surface can be controlled by controlling the thickness of the sacrificial layer, and the reduced size of the through hole in the insulating layer is further accurately controlled.
Correspondingly, the embodiment of the invention also provides a semiconductor device which is formed by the manufacturing method of the semiconductor device. Fig. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
As shown in fig. 6, the semiconductor device provided by the embodiment of the present invention includes a stop layer 1, an insulating layer 2, and a through structure 5.
The stop layer 1 may be a conductive layer, such as a metal layer, including but not limited to tungsten, cobalt, copper, aluminum, and the like. The stop layer 1 may be a semiconductor substrate, for example, a silicon substrate, or a substrate including another element semiconductor or a compound semiconductor. The stop layer 1 may be another film layer different from the insulating layer, and is not particularly limited herein.
An insulating layer 2 is disposed on the stop layer 1, and the insulating layer 2 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.
The through structure 5 penetrates the insulating layer 2, and the width of the through structure 5 in the transverse direction (i.e., the direction a parallel to the upper surface of the stop layer 1) is smaller than a preset width. The preset width refers to the minimum lateral width of the through hole 21a in fig. 1, that is, the lateral width of the through structure 5 in this embodiment is smaller than the minimum lateral width of the through hole 21a in fig. 1. When the stop layer 1 is a conductive layer, the through structure 5 may be a contact point, and the through structure 5 may be connected to the stop layer 1. Connection contacts include, but are not limited to, tungsten, cobalt, copper, aluminum, and the like.
When the through structure 5 is a connection contact, the semiconductor device may further include another conductive layer, and the another conductive layer may be located on the insulating layer 2 so that the another conductive layer is electrically connected to the stop layer 1 through the through structure 5.
The present embodiment reduces the size of the semiconductor device by reducing the lateral width of the through structures 5 on the premise that the semiconductor device has the same number of through structures 5.
Fig. 7 is a schematic structural diagram of a memory according to an embodiment of the present invention.
As shown in fig. 7, the memory includes a memory array structure 100, and a peripheral structure 200 connected to the memory array structure 100. The memory array structure 100 and the peripheral structure 200 may include the semiconductor devices in the above embodiments, and are not described in detail herein.
The memory array structure 100 may be a non-volatile memory array structure, for example, the memory array structure 100 may be a NAND flash memory, a NOR flash memory, or the like. The peripheral structure 200 may include devices such as CMOS (complementary metal oxide semiconductor), SRAM (static random access memory), DRAM (dynamic random access memory), FPGA (field programmable gate array), CPU (central processing unit), Xpoint chip, and the like.
Specifically, the peripheral structure 200 may be located on the memory array structure 100, and the peripheral structure 200 is connected to the memory array structure 100. The memory array structure 100 and the peripheral structure 200 may also adopt other architecture forms, for example, the peripheral structure 200 is located below the memory array structure 100, i.e., a puc (peripheral under core array) architecture, or the peripheral structure 200 and the memory array structure 100 are arranged in parallel, i.e., a pnc (peripheral under core array) architecture, and the like, which is not limited herein.
The memory provided by the embodiment of the invention can reduce the size of a semiconductor device by reducing the transverse width of the through structure, thereby reducing the size of the memory.
Fig. 8 is a schematic structural diagram of a storage system according to an embodiment of the present invention.
As shown in fig. 8, the embodiment of the present invention further provides a memory system, which includes a memory 300 and a controller 400, wherein the memory 300 is electrically connected to the controller 400, and the controller 400 is used for controlling the memory 300 to store data. The memory 300 is the memory in the above embodiments, and is not described in detail herein. The controller 400 may be a controller well known to those skilled in the art and will not be described in detail herein.
The storage system can be applied to terminal products such as computers, televisions, set top boxes, vehicles and the like.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.

Claims (12)

1. A method for manufacturing a semiconductor device, comprising:
providing a stop layer and an insulating layer on the stop layer;
forming a mask layer with an opening on the insulating layer;
forming a sacrificial layer on the mask layer, wherein the sacrificial layer covers the side wall and the bottom surface of the opening so as to form a groove with a concave bottom surface in the opening in a surrounding manner;
through the concave bottom surface, a through hole is formed in the insulating layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein a lateral width of the via hole is smaller than a lateral width of the recessed bottom surface, the lateral width being a direction parallel to an upper surface of the stop layer.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the mask layer comprises an anti-reflection layer and a photoresist layer, and the opening comprises a first sub-opening and a second sub-opening;
the step of forming a mask layer having an opening on the insulating layer includes:
sequentially forming the anti-reflection layer and the photoresist layer on the insulating layer, wherein the photoresist layer is provided with the first sub-opening;
forming the second sub-opening communicating with the first sub-opening in the anti-reflection layer through the first sub-opening.
4. The method according to claim 3, wherein the step of forming a sacrificial layer on the mask layer, the sacrificial layer covering sidewalls and a bottom surface of the opening to form a groove having a concave bottom surface in the opening comprises:
removing the photoresist layer;
forming the sacrificial layer on the anti-reflection layer, wherein the sacrificial layer covers the side wall and the bottom surface of the second sub-opening to form the groove with the concave bottom surface in the second sub-opening.
5. The method for manufacturing a semiconductor device according to claim 3 or 4, wherein the mask layer further comprises a hard mask layer located between the insulating layer and the antireflection layer;
the step of forming a via hole in the insulating layer through the recessed bottom surface includes:
and etching the sacrificial layer, the hard mask layer and the insulating layer corresponding to the concave bottom surface to form the through hole in the insulating layer.
6. The method of manufacturing a semiconductor device according to claim 3, wherein the mask layer further comprises a hard mask layer located between the insulating layer and the antireflection layer, and the opening further comprises a third sub-opening;
the step of forming a mask layer having an opening on the insulating layer further includes:
and forming the third sub-opening communicated with the second sub-opening in the hard mask layer through the second sub-opening.
7. The method according to claim 6, wherein the step of forming a sacrificial layer on the mask layer, the sacrificial layer covering sidewalls and a bottom surface of the opening to form a groove having a concave bottom surface in the opening comprises:
removing the photoresist layer;
forming the sacrificial layer on the antireflection layer, wherein the sacrificial layer covers the side wall of the second sub-opening and the side wall and the bottom surface of the third sub-opening to form the groove with the concave bottom surface in the second sub-opening and the third sub-opening.
8. The method according to claim 6, wherein the step of forming a sacrificial layer on the mask layer, the sacrificial layer covering sidewalls and a bottom surface of the opening to form a groove having a concave bottom surface in the opening comprises:
removing the photoresist layer and the anti-reflection layer;
and forming the sacrificial layer on the hard mask layer, wherein the sacrificial layer covers the side wall and the bottom surface of the third sub-opening so as to enclose the groove with the concave bottom surface in the third sub-opening.
9. The method for manufacturing a semiconductor device according to claim 3, 4, 6, 7 or 8, wherein the step of forming a via hole in the insulating layer through the bottom recess surface includes:
and etching the sacrificial layer and the insulating layer corresponding to the concave bottom surface to form the through hole in the insulating layer.
10. A semiconductor device, comprising:
a stop layer;
an insulating layer on the stop layer;
and the through structure penetrates through the insulating layer, the transverse width of the through structure is smaller than the preset width, and the transverse direction is parallel to the direction of the upper surface of the stop layer.
11. A memory comprises a memory array structure and a peripheral structure connected with the memory array structure;
at least one of the memory array structure and the peripheral structure includes the semiconductor device of claim 11.
12. A memory system comprising the memory of claim 11, and a controller coupled to the memory.
CN202111402336.7A 2021-11-23 2021-11-23 Manufacturing method of semiconductor device, memory and storage system Pending CN114121649A (en)

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