CN113948514A

CN113948514A - Semiconductor device and manufacturing method thereof

Info

Publication number: CN113948514A
Application number: CN202010699778.1A
Authority: CN
Inventors: 郭炳容; 杨涛; 卢一泓; 胡艳鹏
Original assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Current assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Priority date: 2020-07-17
Filing date: 2020-07-17
Publication date: 2022-01-18

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for reducing parasitic capacitance between adjacent storage contact parts and improving the driving capability of the semiconductor device. The semiconductor device includes: the memory device includes a substrate, a bit line structure, a memory contact, and an isolation. The substrate has an active region. The bit line structure is formed on the substrate and contacts a portion of the active region. A memory contact and a spacer are formed between two adjacent bit line structures. The storage contact is in contact with another portion of the active region. The isolation part is used for isolating two adjacent storage contact parts. The isolation portion contains a material including a low-k material. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device provided by the technical scheme.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.

Background

A contact structure is a structure that can interconnect an active region within a semiconductor device with a metal lead located outside of a dielectric layer. The electrical signals in the active region or the electrical signals in the metal leads can be transmitted through the contact structure, so that the semiconductor device can be correspondingly operated.

However, as the semiconductor device is scaled down, a parasitic capacitance is generated between adjacent memory contacts, resulting in a reduction in driving capability of the semiconductor device, thereby making the semiconductor device poor in operation performance.

Disclosure of Invention

The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for reducing the parasitic capacitance between adjacent storage contact parts and improving the driving capability of the semiconductor device.

In order to achieve the above object, the present invention provides a semiconductor device comprising:

a substrate having an active region;

a bit line structure formed on the substrate and contacting a portion of the active region;

and a memory contact portion and an isolation portion formed between two adjacent bit line structures, the memory contact portion contacting another portion of the active region, the isolation portion for isolating the two adjacent memory contact portions, the isolation portion comprising a material including a low-k material.

Compared with the prior art, the semiconductor device provided by the invention has the advantages that the storage contact part and the isolation part are formed between the two adjacent bit line structures. The isolation part is used for isolating two adjacent storage contact parts. And, the isolation portion is made of a low-k material. In particular, the isolation formed from low-k materials has a low dielectric constant. Because the capacitance is in direct proportion to the dielectric constant, the dielectric constant of the isolation part between the adjacent storage contact parts is reduced, and the parasitic capacitance between the adjacent storage contact parts can be reduced, so that the driving capability of the semiconductor device can be improved, and the working performance of the semiconductor device can be improved.

The present invention also provides a method of manufacturing a semiconductor device, the method of manufacturing the semiconductor device including:

providing a substrate with an active region;

forming a bit line structure on the substrate in contact with a portion of the active region;

and forming a storage contact part and an isolation part between two adjacent bit line structures, wherein the storage contact part is contacted with the other part of the active region, the isolation part is used for isolating the two adjacent storage contact parts, and the material contained in the isolation part comprises low-k material.

Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention has the same beneficial effects as those of the semiconductor device provided by the technical scheme, and the detailed description is omitted here.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings, subscripts a, b in the drawings respectively represent cross-sectional views in the AA 'and BB' directions in a plan view.

FIG. 1 is a top view of a completed bit line structure according to an embodiment of the present invention, wherein FIG. 1a is a top view along AA 'shown in FIG. 1, and FIG. 1b is a cross-sectional view along BB' shown in FIG. 1;

FIG. 2 is a top view of a structure after forming a sacrificial layer according to an embodiment of the present invention, FIG. 2a is a cross-sectional view along AA 'of the top view shown in FIG. 2, and FIG. 2b is a cross-sectional view along BB' of the top view shown in FIG. 2;

FIG. 3 is a top view of a structure after forming a first groove according to an embodiment of the present invention, FIG. 3a is a cross-sectional view along AA 'of the top view shown in FIG. 3, and FIG. 3b is a cross-sectional view along BB' of the top view shown in FIG. 3;

FIG. 4 is a top view of a structure after forming a low-k material according to an embodiment of the present invention, FIG. 4a is a cross-sectional view along AA 'of the top view shown in FIG. 4, and FIG. 4b is a cross-sectional view along BB' of the top view shown in FIG. 4;

FIG. 5 is a top view of a structure after forming a spacer according to an embodiment of the present invention, FIG. 5a is a cross-sectional view along AA 'of the top view shown in FIG. 5, and FIG. 5b is a cross-sectional view along BB' of the top view shown in FIG. 5;

FIG. 6 is a top view of a structure after forming a second groove according to an embodiment of the present invention, FIG. 6a is a cross-sectional view along AA 'of the top view shown in FIG. 6, and FIG. 6b is a cross-sectional view along BB' of the top view shown in FIG. 6;

FIG. 7 is a top view of a structure after forming a storage contact according to an embodiment of the present invention, FIG. 7a is a cross-sectional view along AA 'of the top view shown in FIG. 7, and FIG. 7b is a cross-sectional view along BB' of the top view shown in FIG. 7;

FIG. 8 shows Si containing BN₃N₄The relationship between the volume percentage of BN in the film and the dielectric constant and dielectric loss (tan delta) of the film is shown schematically.

Reference numerals:

the memory device comprises a substrate 1, a bit line structure 2, a bit line body 21, a sidewall 22, a memory contact 3, an isolation 4, a sacrificial layer 5, a first groove 6, a low-k material 7 and a second groove 8.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In memory fabrication, after the transistors, the dielectric layer covering the transistors, and the bit line structures are fabricated, it is often necessary to form memory contacts and spacers between adjacent bit line structures. The isolation part is used for isolating adjacent storage contactsAnd (4) a section. The bottom of each memory contact is in contact with a corresponding active region so as to transmit electrical signals, and corresponding operation of the semiconductor device is realized. In particular, in the existing memory manufacturing process, several storage contacts (each of which is in contact with a drain region or a source region included in a corresponding transistor) are formed between adjacent bit line structures. Then, a Damascus mode can be adopted, and an insulating material Si is utilized₃N₄The spacer is fabricated to separate adjacent storage contacts.

However, as semiconductor devices shrink, the pitch of adjacent memory contacts gradually decreases. And, made of Si₃N₄The isolation portion made of the material has a high dielectric constant, so that the isolation portion has high dielectric loss, and a large parasitic capacitance is generated between adjacent storage contact portions. Due to the existence of the parasitic capacitor, when the semiconductor device is driven, the charge movement on the storage contact part is influenced, so that the driving capability of the semiconductor device is reduced, and the working performance of the memory is poor.

In order to solve the above technical problem, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. The material contained in the isolation part in the semiconductor device provided by the embodiment of the invention comprises a low-k material, and the dielectric constant of the isolation part is reduced, so that the parasitic capacitance between adjacent storage contact parts can be reduced, the driving capability of the semiconductor device is improved, and the performance of a memory is improved.

Embodiments of the present invention provide a semiconductor device, which can be applied to electronic devices such as a DRAM (dynamic random access memory), a FLASH memory, an MRAM (magnetic memory), or an RRAM (resistive random access memory).

As shown in fig. 7, 7a and 7b, the semiconductor device includes at least: a substrate 1, a bit line structure 2, a memory contact 3 and a spacer 4.

The substrate 1 may be a stack of layers in which part of the semiconductor structure has been formed. The substrate 1 has active regions, for example, source and drain regions have been formed. The number and arrangement of the active regions may be set according to practical application scenarios, as long as the active regions can be applied to the semiconductor device provided by the embodiment of the present invention. For example, the active region may be arranged in a crossing direction with the bit line structure 2. The substrate 1 may further include a gate electrode (word line) thereon, and form a transistor structure with the source region and the drain region as a switching transistor of the memory.

In some cases, the substrate 1 further has an isolation region (not shown). The isolation region is used for isolating two adjacent active regions. For the isolation region, the material contained in the isolation region may be an insulating material such as silicon oxide or silicon nitride.

In other cases, the substrate 1 further has a protective layer (not shown) covering the surfaces of the active region and the isolation region. The protective layer may be composed of an insulating layer and a buffer layer, which are usually dielectric layers, and the insulating layer and the buffer layer may be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

As shown in fig. 7, 7a and 7b, the bit line structure 2 is formed on a substrate 1. Also, the bit line structure 2 contacts a portion of the active region. The bit line structure 2 may include a bit line body 21, a cap layer (not shown) formed on the bit line body 21, and sidewalls 22 on two sides of the bit line body 21 and the cap layer. The bit line body 21 may include a bit line contact and a wiring layer. Wherein the bit line contact is electrically connected to the source region (or drain region). The bit line contact material may comprise a conductive material such as doped polysilicon or boron doped silicon germanium. The wiring layer may include doped polysilicon and a metal layer, or may be a barrier layer and a metal layer. The material of the barrier layer may include TiN, TaN, or the like, and the material contained in the metal layer may include tungsten (W), aluminum (Al), copper (Co), nickel (Ni), cobalt (Co), or the like. For the cap layer and the sidewall spacers 22, the cap layer and the sidewall spacers 22 are made of insulating materials, and the common insulating materials are SiCN, SiOCN, SiON, SiN, or the like.

As shown in fig. 7, 7a and 7b, the memory contact 3 and the isolation 4 are formed between two adjacent bit line structures 2. The storage contact 3 is in contact with another portion of the active region. The isolation portion 4 is used to isolate two adjacent storage contact portions 3. The material contained in the isolation portion 4 includes a low-k material. It should be understood that the region where the other part of the active region is located is a region where a drain region (or a source region) formed on the active region is located. The storage contact 3 contacts a drain region (or a source region) on the active region.

In addition, as shown in fig. 7, 7a and 7b, the storage contact 3 may be formed both in the protective layer provided in the substrate 1 and extended into a portion of the active region. At this time, the storage contact 3 protrudes into the substrate 1 to a large depth. On this basis, the bottom portions of the storage contacts 3 are in contact with the plurality of surface portions of the active region, which are processed in the drain region (or the source region), increasing the contact area between the storage contacts 3 and the drain region (or the source region) included in the active region. In the case of the above-described spacer 4, as shown in fig. 7b, the spacer 4 may be formed only in the protective layer provided in the substrate 1. At this time, the depth of the spacer 4 protruding into the substrate 1 is small, and the bottom of the spacer 4 is higher than the bottom of the storage contact 3.

The material contained in the memory contact 3 may be a conductive material such as doped polysilicon or boron-doped silicon-germanium. For the isolation portion 4, the material contained in the isolation portion 4 includes a low-k material. Insulating materials having k values less than or equal to 2.8 are generally considered low k materials. The isolation 4 made of a low-k material has a low dielectric constant, so that the isolation 4 has low dielectric loss. Since the capacitance is proportional to the dielectric constant, the dielectric constant of the isolation portion 4 between the adjacent memory contact portions 3 is reduced, and the parasitic capacitance between the adjacent memory contact portions 3 can be reduced, so that the driving capability of the semiconductor device can be improved, and the working performance of the memory can be improved.

Illustratively, the low-k material may be one or more of BN, SiBN, and SiCN.

For example, FIG. 8 shows Si containing BN₃N₄The relationship between the volume percentage of BN in the film and the dielectric constant and dielectric loss (tan delta) of the film is shown schematically. Where tan δ is a dielectric loss tangent, and tan δ is proportional to a dielectric loss. As can be seen from FIG. 8, Si₃N₄The higher the volume percentage of BN contained in the film, the higher the dielectric constant and dielectric constant of the filmThe lower the losses. Based on this, when the low-k material is BN, the isolation portion 4 made of the low-k material has a low dielectric constant and dielectric loss.

In summary, in practical applications, as shown in fig. 7, 7a and 7b, when the semiconductor device is applied to a DRAM, the substrate 1 may be a semiconductor substrate on which a transistor structure has been formed. A protective layer including an insulating layer and a buffer layer is formed on the transistor structure. The insulating layer and the buffer layer may be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The bit line structures 2, and the memory contact portions 3 and the isolation portions 4 between the adjacent bit line structures 2 are formed on the substrate 1. When the isolation portion 4 is made of the above-described low-k material, the parasitic capacitance between the adjacent memory contact portions 3 can be reduced, so that the driving ability and the operating performance of the DRAM device can be improved. Of course, the semiconductor device provided by the embodiment of the invention can also be applied to other electronic devices, and is not limited to the DRAM device.

The embodiment of the invention also provides a manufacturing method of the semiconductor device. The following will describe a manufacturing method provided by an embodiment of the present invention, taking DRAM manufacturing as an example, according to a top view or a cross-sectional view of the operation shown in fig. 1 to 7 b. Each of the subscripts a and b in the drawing indicates a cross-sectional view along the direction AA 'or BB' in the corresponding plan view, AA 'corresponds to the position where the memory contact portions 3 are to be formed, and BB' corresponds to the position of the spacer 4 between the memory contact portions 3, which will not be described several times below.

First, a substrate 1 having an active region is provided. As for the structure of the active regions, the number of the active regions, the arrangement of the active regions, and the like, reference may be made to the foregoing description, which is not repeated herein. In some cases, the above substrate 1 also has an isolation region and a protective layer. The isolation region is used for isolating two adjacent active regions. A protective layer covers the isolation region and the active region. As to the materials contained in the isolation region and the protection layer, reference may be made to the above.

Referring to fig. 1, 1a and 1b, a bit line structure 2 is formed on a substrate 1.

As described above, the bit line structure 2 may include a bit line contact, a bit line body 21, a cap layer, and sidewalls 22. The bit line contacts, the bit line body 21, the capping layer, and the sidewalls 22 may be sequentially formed on the substrate 1.

For example: first, a contact hole may be formed on the substrate 1 by photolithography corresponding to a position where a bit line contact is to be formed, and the bit line contact may be formed in the contact hole. After that, a layer of bit line material is deposited on the substrate 1. For example, the bit line material layer may be a stacked structure of polysilicon and metal W. Next, a cap layer pattern is formed on the stacked structure, and the stacked structure and the substrate 1 are etched using the cap layer pattern as a mask, thereby forming the bit line body 21. Finally, the side walls 22 are formed on the two sides of the bit line body 21 and the cover layer included in the cover layer pattern, specifically, a side wall material layer may be deposited on the entire substrate 1 and the bit line body 21, and the side walls 22 may be formed by anisotropic etching. As for the materials contained in the bit line contact portion, the bit line body 21, the cap layer and the sidewall spacers 22, reference is made to the foregoing, and the description thereof is omitted here.

The bit line structure 2 may be formed in various ways. How to form the bit line structure 2 is not a main feature of the embodiment of the present invention, and therefore, in the present specification, only a brief description thereof will be given so that a person having ordinary skill in the art can easily implement the embodiment provided by the present invention. It is fully conceivable for a person skilled in the art to manufacture the bit line structure 2 in other ways.

Referring to fig. 2, 2a and 2b, a sacrificial layer 5 is formed between adjacent two bit line structures 2.

Illustratively, the sacrificial layer 5 may be formed directly between two adjacent bit line structures 2 by chemical vapor deposition or the like. The sacrificial layer 5 may contain a material that is easy to remove. For example: the sacrificial layer 5 contains SiO₂And/or a carbon polymer. The specific composition of the carbon polymer may be set according to actual conditions, and is not particularly limited herein. For example: the carbon polymer may include propylene glycol monomethyl ether, propylene glycol monoethyl ether, amide methyl ether cross-linking agents, acrylic acid polymer, 2-methoxy-1-propanol, and surfactants. The above carbon polymerThe content of each substance included may be set according to actual circumstances.

The height of the top of the sacrificial layer 5 should be equal to or greater than the height of the top of the bit line structure 2. When the top height of the formed sacrificial layer 5 is greater than the top height of the bit line structure 2, after the sacrificial layer 5 is formed, planarization processing may be performed on the sacrificial layer 5 until the top of the bit line structure 2 is exposed.

In another example, after the bit line structures 2 are formed on the substrate 1, the bit line structures 2 are used as masks, and the passivation layer included in the substrate 1 is etched until the active regions between adjacent bit line structures 2 are exposed. Then, a sacrificial material is filled in the trench formed by etching the substrate 1 to form a sacrificial layer 5.

Referring to fig. 3, 3a and 3b, the sacrificial layer 5 located in the predetermined region is processed to form a first groove 6.

Illustratively, a photolithographic mask pattern may be formed over the substrate 1 filled with the sacrificial layer 5, the photolithographic mask pattern exposes the position where the isolation region needs to be formed by etching, and plasma etching, reactive ion etching or other etching methods are used to remove the sacrificial layer 5 outside the corresponding active region, and the sacrificial layer 5 on the active region is remained to form the first groove 6. The depth of the first recess 6 may be at least equal to the thickness of the sacrificial layer 5. Specifically, the shape parameters (depth, width, etc.) of the first groove 6 determine the shape parameters (depth, width, etc.) of the subsequently formed spacer 4, so the shape parameters of the first groove 6 can be set according to the shape parameters of the spacer 4.

Referring to fig. 4, 4a and 4b, a low-k material 7 may be formed on the substrate 1 covering the bit line structure 2 and the first recess 6. Illustratively, the low-k material 7 covering the bit line structure 2 and the first recess 6 may be formed by chemical vapor deposition or the like. In particular, the low-k material 7 has a k value less than or equal to 2.8.

For example: the low-k material 7 can be one or more of BN, SiBN and SiCN.

Referring to fig. 5, 5a and 5b, the spacer 4 is formed in the first groove 6. It should be appreciated that to ensure that the low-k material 7 fills the first recess 6, the top of the low-k material 7 is formed higher than the top of the bit line structure 2. At this time, the formed low-k material 7 is formed both in the first recess 6 and on the bit line structure 2. In order to form the isolation portions 4 separated from each other, it is also necessary to perform a node separation process on the low-k material 7, leaving only the low-k material 7 located in the first recess 6. Accordingly, the low-k material 7 remaining in the first recess 6 forms the isolation 4.

Specifically, the node separation treatment may be performed on the low-k material 7 by a plasma etching method or a wet etching method. The specific working parameters when the plasma etching method is used to perform the node separation treatment on the low-k material 7 may be set according to an actual application scenario, and are not specifically limited herein. When the wet etching method is used to perform the node separation treatment on the low-k material 7, the used solution may be an HF solution, or a solution containing HF and H₂SO₄、H₂O₂And deionized water. Wherein, HF and H in the mixed solution₂SO₄、H₂O₂The proportion of the deionized water can be set according to practical application scenarios, and is not particularly limited herein.

The remaining sacrificial layer 5 may then be removed, for example, the remaining sacrificial layer 5 may be removed by wet etching or dry etching, so as to expose the surface of the substrate 1 covered by the remaining sacrificial layer 5.

Referring to fig. 6, 6a and 6b, a second recess 8 is then formed between adjacent bit line structures 2. It should be understood that to form the storage contacts 3 in contact with the respective active regions, the substrate 1 may be etched down to form the second recesses 8 using the bit line structures 2 and the spacers 4 as masks to expose the active regions between adjacent bit line structures 2. Of course, the substrate 1 may be continuously etched downward after exposing the active region between the adjacent bit line structures 2, so as to increase the contact area between the drain region (or the source region) included in the active region and the storage contact 3 formed later.

Referring to fig. 7, 7a and 7b, the storage contact 3 is formed in the second groove 8. Illustratively, the storage contact 3 may be formed on the exposed active region between the adjacent bit line structures 2 by epitaxy or chemical vapor deposition.

In the process of forming the memory contact portion 3 and the isolation portion 4, the sacrificial layer 5 in the predetermined region is removed to form the first recess 6, and the isolation portion 4 is formed in the first recess 6. Thereafter, the remaining sacrificial layer 5 and the substrate 1 between the adjacent bit line structures 2 are processed to form a second recess 8, and a storage contact 3 is formed in the second recess 8. In practical application, the formation order of the memory contact 3 and the isolation portion 4 may be changed, that is, the memory contact 3 may be formed first and then the isolation portion 4 may be formed. Specifically, the formation sequence of the storage contact portion 3 and the isolation portion 4 may be set according to practical situations, and is not limited herein.

The beneficial effects of the method for manufacturing a semiconductor device provided by the embodiment of the invention are the same as those of the semiconductor device provided by the above embodiment, and are not described herein again.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a substrate having an active region;

and a memory contact portion and an isolation portion formed between two adjacent bit line structures, wherein the memory contact portion is in contact with another part of the active region, the isolation portion is used for isolating two adjacent memory contact portions, and the isolation portion contains a material including a low-k material.

2. The semiconductor device of claim 1, wherein the low-k material has a k value less than or equal to 2.8.

3. The semiconductor device according to claim 1, wherein the low-k material is one or more of BN, SiBN, and SiCN.

4. The semiconductor device according to claim 1, wherein a bottom of the isolation portion is higher than a bottom of the storage contact portion.

5. The semiconductor device according to any one of claims 1 to 4, wherein the bit line structure includes a bit line body, a cap layer on the bit line body, and sidewalls on both sides of the bit line body and the cap layer.

6. A method of manufacturing a semiconductor device, comprising:

providing a substrate with an active region;

and forming a storage contact part and an isolation part between two adjacent bit line structures, wherein the storage contact part is contacted with the other part of the corresponding active region, the isolation part is used for isolating the two adjacent storage contact parts, and the material contained in the isolation part comprises a low-k material.

7. The method of manufacturing a semiconductor device according to claim 6, wherein the forming a memory contact and an isolation between two adjacent bit line structures comprises:

forming a sacrificial layer between two adjacent bit line structures;

processing the sacrificial layer in the preset area to form a first groove;

forming the isolation part in the first groove;

removing the rest sacrificial layer, and etching the substrate downwards to form a second groove by taking the bit line structures and the isolation parts as masks so as to expose the other part of the active region between the adjacent bit line structures;

forming the storage contact in the second groove.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming a sacrificial layer between two adjacent bit line structures comprises:

etching the substrate until the active region is exposed by taking the bit line structure as a mask so as to form a groove parallel to the bit line structure;

filling a sacrificial material in the trench to form a sacrificial layer.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein a material contained in the sacrifice layer includes SiO₂And/or a carbon polymer.

10. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein the forming of the isolation portion in the first groove includes:

forming a low-k material on the substrate to cover the bit line structure and the first groove;

and carrying out node separation treatment on the low-k material to obtain the isolation part.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the node separation treatment is performed on the low-k material by a plasma etching method or a wet etching method.

12. The method for manufacturing a semiconductor device according to claim 10, wherein when the node separation treatment is performed on the low-k material by wet etching, a solution used is an HF solution or a solution containing HF and H₂SO₄、H₂O₂And deionized water.