CN114116530A - Storage control method and device, data processing method and device, and storage medium - Google Patents
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- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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Abstract
A storage control method and apparatus, a data processing method and apparatus, and a storage medium. The storage control method comprises the following steps: receiving a write request for a memory, wherein the write request comprises a part of data content to be written into the memory and a data mark; determining a writing mode based on the data flag; and writing partial data content into a target storage block of the memory according to the writing mode, and writing the data mark into an ECC code segment which is associated with the target storage block in the memory. The method can reduce the transmission times of the data blocks, reduce the transmission delay of data reading and writing, save the data bandwidth and reduce the system power consumption.
Description
Technical Field
Embodiments of the present disclosure relate to a storage control method and apparatus, a data processing method and apparatus, and a storage medium.
Background
As shown in fig. 1, current computer processors typically include multiple processor cores and multiple system memories (main memory), as well as multiple levels of cache memory (e.g., L1 cache, L2 cache, etc.) between each processor core and main memory. The plurality of processor cores and the main memory are connected to each other through an interconnection bus. Each main memory (for example, DRAM) is managed by a memory controller, and functions of the memory controller include performing interface conversion, converting requests (commands) such as read and write requests (commands) issued by a main device (processor core) into signals recognizable by the main memory, performing address decoding, data format conversion, and the like between the main device and the memory.
Disclosure of Invention
At least one embodiment of the present disclosure provides a storage control method, including: receiving a write request for a memory, wherein the write request comprises a part of data content to be written into the memory and a data mark; determining a writing mode based on the data flag; writing the partial data content to a target storage block of the memory according to the writing mode, and writing the data mark to an ECC code segment associated with the target storage block in the memory.
For example, in the storage control method according to at least one embodiment of the present disclosure, the partial data content is a part of a data block to be written to the target storage block, the data flag indicates a data pattern of the data block based on the partial data content, the writing pattern corresponds to the data pattern, and the data block is restored in the target storage block in response to writing the partial data content to the target storage block of the memory according to the writing pattern.
At least one embodiment of the present disclosure provides another storage control method, including: receiving a read request for memory; reading partial data content from a target memory block of the memory according to the read request, and acquiring a data mark from an ECC code segment associated with the target memory block; determining a readout mode based on the data flag; and returning the partial data content and the data mark according to the reading mode.
For example, in the storage control method according to at least one embodiment of the present disclosure, the partial data content is a part of a data block to be read out from the target storage block, the data flag indicates a data pattern of the data block based on the partial data content, the read-out pattern corresponds to the data pattern, and in response to returning the partial data content and the data flag according to the read-out pattern, a part of the data block other than the partial data content is no longer read out from the memory.
For example, in a storage control method according to at least one embodiment of the present disclosure, the data pattern includes one of the following patterns:
the data blocks are regularly distributed based on the partial data content;
the portion of the data block other than the partial data content is a particular value.
For example, in the storage control method according to at least one embodiment of the present disclosure, the partial data content corresponds to a lower half of the data block.
For example, in the storage control method of at least one embodiment of the present disclosure, the data block is based on a cache line of a system cache, and the length of the cache line is equal to the size of the storage block and is greater than a system bandwidth for the memory.
For example, in the storage control method according to at least one embodiment of the present disclosure, the data flag includes at least one bit, the ECC code segment includes a plurality of bits, and the length of the data flag is smaller than the length of the ECC code segment.
At least one embodiment of the present disclosure provides a storage control apparatus including: a receiving unit configured to receive a write request to a memory, wherein the write request includes a partial data content to be written to the memory and a data flag; a data flag determination unit configured to determine a writing mode based on the data flag; and the writing unit is used for writing the partial data content into a target storage block of the memory according to the writing mode and writing the data mark into an ECC code segment which is associated with the target storage block in the memory.
At least one embodiment of the present disclosure provides another storage control apparatus, including: a receiving unit configured to receive a read request for a memory; a reading unit configured to read a partial data content from a target memory block of the memory according to the read request, and acquire a data flag from an ECC code segment associated with the target memory block; a data flag determination unit configured to determine a readout mode based on the data flag; a data returning unit configured to return the partial data content and the data flag according to the readout mode.
At least one embodiment of the present disclosure provides another storage control apparatus, including: a memory for non-transitory storage of computer-executable instructions; and a processing unit for executing the computer-executable instructions, wherein the computer-executable instructions, when executed by the processing unit, perform the storage control method according to any embodiment of the present disclosure.
At least one embodiment of the present disclosure provides a non-transitory storage medium that non-transitory stores computer-executable instructions, wherein the computer-executable instructions, when executed by a computer, perform a storage control method according to any one of the embodiments of the present disclosure.
At least one embodiment of the present disclosure provides a data processing method, including: acquiring a data pattern of a data block, and generating a data mark corresponding to the data pattern; obtaining partial data content from the data block according to the data pattern; generating a write request to write the data block to memory based on the partial data content and a data flag; sending the write request to write the partial data content to a target memory block of the memory and to write the data flag to an ECC code segment in the memory associated with the target memory block.
At least one embodiment of the present disclosure provides another data processing method, including: sending a read request; receiving a portion of data content read from a target memory block of a memory according to the read request and a data flag read from an ECC code segment associated with the target memory block, wherein the data flag corresponds to a data pattern for obtaining the data block; recovering the data block from the partial data content according to the data pattern.
For example, in the data processing method according to at least one embodiment of the present disclosure, the data pattern includes one of the following patterns:
the data blocks are regularly distributed based on the partial data content;
the portion of the data block other than the partial data content is a particular value.
For example, in the data processing method according to at least one embodiment of the present disclosure, the partial data content corresponds to a lower half of the data block.
For example, in the data processing method of at least one embodiment of the present disclosure, the data block is based on a cache line of a system cache, and the length of the cache line is equal to the size of the memory block and is greater than a system bandwidth for the memory.
At least one embodiment of the present disclosure provides a data processing apparatus including: an operation unit configured to acquire a data pattern of a data block, generate a data flag corresponding to the data pattern, and obtain partial data content from the data block according to the data pattern; a request generation unit configured to generate a write request to write the data block to a memory based on the partial data content and a data flag; a sending unit configured to send the write request to write the partial data content to a target memory block of the memory and to write the data flag to an ECC code segment associated with the target memory block in the memory.
At least one embodiment of the present disclosure provides another data processing apparatus including: a transmitting unit configured to transmit a read request; a receiving unit configured to receive a partial data content read from a target memory block of a memory according to the read request and a data flag read from an ECC code segment associated with the target memory block, wherein the data flag corresponds to a data pattern for acquiring the data block; an operation unit configured to recover the data block from the partial data content according to the data pattern.
At least one embodiment of the present disclosure provides another data processing apparatus including: a memory for non-transitory storage of computer-executable instructions; and a processing unit for executing the computer-executable instructions, wherein the computer-executable instructions, when executed by the processing unit, perform a data processing method according to any of the embodiments of the present disclosure.
At least one embodiment of the present disclosure provides a non-transitory storage medium that non-transitory stores computer-executable instructions, wherein the computer-executable instructions, when executed by a computer, perform a data processing method according to any one of the embodiments of the present disclosure.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
FIG. 1 illustrates a computer system of multiple processors (cores);
FIG. 2 illustrates an exemplary system architecture provided by embodiments of the present disclosure;
FIG. 3 illustrates a storage control method provided by an embodiment of the present disclosure;
FIG. 4 illustrates another storage control method provided by embodiments of the present disclosure;
fig. 5 illustrates a data processing method provided by an embodiment of the present disclosure;
FIG. 6 illustrates another data processing method provided by an embodiment of the present disclosure;
FIG. 7A illustrates an example of when data writing is performed in one embodiment of the present disclosure;
FIG. 7B shows an example of data reading for the data written in the example of FIG. 7A;
FIG. 8 illustrates a storage control apparatus provided by an embodiment of the present disclosure;
fig. 9 illustrates a data processing apparatus provided by an embodiment of the present disclosure;
fig. 10 shows a schematic diagram of a storage control device or a data processing device according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
FIG. 1 illustrates a multiprocessor (core) computer system. In the processor shown in fig. 1, a processor core accesses data from a corresponding certain level of cache in units of cache lines, and if the accessed data hits in the cache, the data is directly accessed from the cache; if the cache misses, the data is read from the next-level cache or from the main memory (memory), and if there is still no hit in the main memory, the data needs to be further read from an external storage device such as a hard disk.
The capacity of the Cache (Cache) is usually very small, the content stored in the Cache is a subset of the content of the main memory, and the data exchange between the Cache and the main memory is in units of Cache lines (Cache lines). In order to cache the data in the main memory into the cache, some function may be applied to locate the address corresponding to the data in the main memory into the cache, which is called address mapping. After the data in the main memory is cached in the cache memory according to the mapping relation, when a processor (processor core) executes a program, a main memory address in the program is converted into a cache memory address.
When a processor core needs to read a cache line of data from main memory, it needs to access the main memory through a memory controller. In the case of a 64byte (including 8 bit) size cache behavior, the interface between the memory controller and the processor core is usually designed to be 128 bits (bit) or 256 bits for bandwidth performance, i.e. reading 64 bytes of data requires 4 beats (transmission times) or 2 beats of read completion. And the memory controller returns the read data to the processor core sending the request and the corresponding cache. The main memory needs to read and write all data in the address when reading and writing the data of the cache line, but because of the bit width limitation of the interface of the memory controller, the reading and writing of one cache line can be completed by multiple beats, and on the other hand, the bit width increase of the memory brings extra hardware and software cost and increased design difficulty.
Dynamic Random Access Memory (DRAM) is the most common system Memory, and the basic unit (Memory bit) includes a transistor and a capacitor, and data is lost after power is turned off. Common types of memory include DDR4, DDR3, LPDDR4, LPDDR3, HBM, GDDR, and the like.
Main memory, like any electronic system, can also be subject to errors due to design failures/defects or electrical noise in any component. These errors are classified as hard errors (caused by design failures) or soft errors (memory array bit flips caused by system noise or by alpha rays, etc.). Although most memory errors are caused by DRAM from the theory, performing end-to-end protection from the memory controller to the DRAM is essential for overall memory stability. To handle these memory errors at runtime, the memory subsystem must have advanced RAS (reliability, availability, and maintainability) functionality to correct for memory errors, extending the uptime of the overall system. Without RAS functionality, the system would likely crash due to memory errors.
One of the most commonly used RAS schemes in memory subsystems is Error Correction Code (ECC) memory. The ECC code may be, for example, a parity bit added to the memory, a SECDED (single bit error correction and double bit error detection) check bit, a DECTED (double bit error correction and three bit error detection) check bit, or the like. Taking the SECDED approach as an example, the memory controller generates SECDED check bit data for actual data and stores the SECDED check bit data in the additional DRAM memory cells to perform single bit error correction and double bit error detection on the data processed by the DRAM. The ECC code data is generated by the memory controller from the currently processed write data. The memory stores the write data and the correspondingly generated ECC code aiming at the write command simultaneously. In a read operation, the memory controller reads data and corresponding ECC codes from the memory. The memory controller regenerates the ECC code using the received data and compares it with the received ECC code. If the two match, no error will occur. If not, the SECDED algorithm allows the memory controller to correct any single bit (bit) errors and detect double bit errors. The error correction function is realized, the memory needs an extra ECC code segment to store the ECC code, for example, when the data bits (the total number of bits of the data to be detected) are 32 bits, the required SECDED check bits are at least 7 bits, and the required DECTED check bits are at least 13 bits; for 64 bits of data, at least 8 bits of SECDED check bits are required and at least 15 bits of DECTED check bits are required. For example, for DDR5 memory (banks) there are 40 bits per channel, with 32 bits for data and 8 bits for ECC code segments.
The inventor of the present disclosure has noted that a main memory with ECC function includes ECC bits in addition to data bits, for example, every 32 bits of a DDR5 memory is correspondingly provided with 8 bits (ECC code segment) for storing ECC codes, and under some ECC modes, the 8-bit ECC code segment is not used completely, so if these unused redundant ECC bits are used to store additional information for data in a storage block (corresponding to a cache line), the additional information can be utilized to reduce the number of access transmission times to some extent, and improve the system access performance.
Based on the above understanding, embodiments of the present disclosure propose a method that uses redundant bits of ECC bits in main memory, except for the ECC function, to record some distribution law of stored data to reduce the number of transfers required to write or read, for example, one cache line in case of bit width limitation.
At least one embodiment of the present disclosure provides a storage control method including: receiving a write request for a memory, wherein the write request comprises a part of data content to be written into the memory and a data mark; determining a writing mode based on the data flag; and writing partial data content into a target storage block of the memory according to the writing mode, and writing the data mark into an ECC code segment which is associated with the target storage block in the memory.
At least one embodiment of the present disclosure also provides a storage control method, including: receiving a read request for memory; reading part of data content from a target storage block of the memory according to the read request, and acquiring a data mark from an ECC code segment associated with the target storage block; determining a read mode based on the data flag; and returning part of the data content and the data mark according to the reading mode.
At least one embodiment of the present disclosure also provides a storage control apparatus (memory controller) and a storage medium corresponding to the above-described storage control method.
At least one embodiment of the present disclosure provides a data processing method, including: acquiring a data pattern of a data block, and generating a data mark corresponding to the data pattern; obtaining partial data content from the data block according to the data pattern; generating a write request to write the data block to the memory based on the partial data content and the data flag; sending a write request to write a portion of the data content to a target memory block of the memory and to write the data flag to an ECC code segment of the memory associated with the target memory block.
At least one embodiment of the present disclosure also provides a data processing method, including: sending a read request; receiving a portion of data content read from a target memory block of the memory according to the read request and a data flag read from an ECC code segment associated with the target memory block, wherein the data flag corresponds to a data pattern of the acquired data block; the data blocks are recovered from the partial data content according to the data pattern.
At least one embodiment of the present disclosure also provides a processing processor and a storage medium corresponding to the above-described data processing method.
The storage control method and the data processing method provided by the embodiments of the present disclosure may utilize an ECC code segment (e.g., a redundant bit) of a memory as a data flag to store a data mode (or a distribution rule) in an operated data block, so that when a (large and small system bandwidth) data block is read and written, the number of times of transmission between a memory controller and the memory may be reduced, or the number of times of transmission between a processor and the memory controller may be reduced, transmission delay of data reading and writing may be reduced, a data bandwidth may be saved, and system power consumption may be reduced.
Various embodiments of the present disclosure are described below with reference to specific examples.
Fig. 2 illustrates an exemplary system architecture provided by embodiments of the present disclosure. As shown in fig. 2, a computer system includes one or more processors (or processor cores) and one or more system memories (e.g., main memory), and may also include one or more levels of cache (e.g., an L1 cache, an L2 cache, etc.) between the processors and the system memories. The processor and the system memory are connected to each other by an interconnection bus. The system memory is managed by a memory controller, and the functions of the memory controller include performing interface conversion, converting requests (commands) such as read and write requests (commands) issued by a host device (such as a processor or a processor core) into signals which can be recognized by the system memory, and completing address decoding, data format conversion and the like between the host device and the system memory. A control interface, a data interface and an ECC code segment interface are arranged between the memory controller and the system memory to transmit control information, data information and ECC codes, and each interface has different bits according to different specifications. Connected between the memory controller and the processor by a system interconnect (e.g., bus, network on chip, etc.) and having a control interface and a data interface to communicate control information and data information.
At least one embodiment of the present disclosure provides a storage control method 100, for example, for a memory controller to write data into a controlled system memory (e.g., main memory) at, for example, a processor request, as shown in FIG. 3, the method comprising the following steps 101-103:
step 101: a write request to memory is received. The write request, e.g., from a host device of a processor, requests that data be written to a target address in memory, e.g., as main memory, the write request including a portion of the data content to be written to memory and a data flag.
Step 102: the writing pattern is determined based on the data flag.
For example, the memory controller determines the write mode, i.e., how to write the data block that results in the actual write, based on the data flag.
Step 103: and writing partial data content into a target storage block of the memory according to the writing mode, and writing the data mark into an ECC code segment which is associated with the target storage block in the memory.
For example, the memory controller writes a portion of the data content to a target memory block of the memory based on the write pattern and writes the data flag to an ECC code segment in the memory associated with the target memory block.
For example, in at least one example, the write request includes a portion of data content that is a portion of a data block to be written to the target storage block, and the data flag indicates a data pattern of the data block based on the portion of data content, where the write pattern corresponds to the data pattern of the data block. Depending on the write mode, the memory controller writes a partial data content to a target memory block of the memory and makes up the data block for parts other than the partial data content, e.g. restores the partial data content at the target memory block to get a complete data block, i.e. the data block is actually written at a target address in the memory.
At least one embodiment of the present disclosure provides a storage control method 200, for example, for a memory controller to read data from a controlled system memory (e.g., main memory) at, for example, a processor request, as shown in FIG. 4, the method comprising the following steps 201-204:
step 201: a read request for memory is received. The read request, for example from a master device such as a processor, requests to read data from a target address of memory.
Step 202: the method includes reading a portion of data content from a target memory block of the memory in accordance with a read request, and obtaining a data flag from an ECC code segment associated with the target memory block.
For example, the memory controller reads a part of data content from the memory according to the read request and simultaneously obtains a corresponding ECC code, and analyzes the ECC code to obtain the data flag.
Step 203: the read mode is determined based on the data flag.
For example, the memory controller determines the read mode based on the data flag, e.g., determines whether to continue reading other data portions from the memory.
Step 204: and returning part of the data content and the data mark according to the reading mode.
For example, the memory controller returns the read partial data content along with the data flag to the master device that issued the read request.
For example, in at least one example, the partial data content is a portion of a data block to be read from the target storage block, the data flag indicates a data pattern of the data block based on the partial data content, the read pattern corresponds to the data pattern, and in response to returning the partial data content and the data flag according to the read pattern, a portion of the data block other than the partial data content is no longer read from the memory.
For example, with respect to the method 100 or 200 described above, the data pattern of the processed data block based on the partial data content includes one of the following patterns:
the data blocks are regularly distributed based on partial data content;
the portion of the data block other than the partial data content is a particular value.
For the case that the data blocks are regularly distributed based on the partial data content, for example, the data blocks are obtained by repeating n cycles based on the partial data content, where n is a positive integer greater than or equal to 2, such as 2, 4, 8, and the like. For example, for the case of n =2, the partial data content corresponds to the lower half of the data block, i.e. the lower half of the data block is processed first, while the upper half is the same as the lower half, and thus can be obtained directly from the lower half.
For the case where the portion of the data block other than the partial data content is a specific value, for example, the portion of the data block other than the partial data content is all 0's, or all 1's, or other specific data. For example, when the partial data content corresponds to the lower half of the data block, the upper half of the data block may be all 0's, or all 1's, or for example 101010 … …, etc.
For example, in at least one example, a processor, e.g., as a device, when reading and writing data to and from a cache, if there is no hit in the cache, it needs to further read and write data from and to a main memory, and this number of times is transferred in units of cache lines. That is, the data block is based on a cache line of the system cache, e.g., the length of the cache line may be the smallest unit of the cache when reading and writing data, e.g., the length of the cache line may also be equal to the size of the memory block and larger than the system bandwidth for the memory, e.g., the bandwidth between the processor and the memory controller, e.g., determined by the interconnect bandwidth connecting the processor and the memory controller.
For example, the data flag includes at least one bit, the ECC code segment includes a plurality of bits, and the length of the data flag is smaller than the length of the ECC code segment. For example, when the data flag is one bit, there are only two values of 0 and 1, and thus only two data patterns can be represented; when the data flag is a plurality of bits (at least two bits), the plurality of bits can be used to represent a plurality of different cases of data patterns.
In the above-described storage control method, a write request or a read request is generated by a host device such as a processor (or a processor core), and a data block that needs to be written and a data block that needs to be read are processed, so at least one embodiment of the present disclosure also provides a data processing method as follows.
At least one embodiment of the present disclosure also provides a data processing method 300, for example for a processor to generate and send a write request to a memory controller, as shown in fig. 5, the method comprising the steps 301-304 of:
step 301: a data pattern of the data block is obtained, and a data flag corresponding to the data pattern is generated.
For example, when the processor needs to write data, the entire cached data block in which the data is located is written into the memory, the data pattern of the data block is analyzed, and a data flag corresponding to the data pattern is generated based on the analysis result.
Step 302: partial data content is derived from the data block according to the data pattern.
For example, the processor will select the portion of the data content that is actually transmitted in the data block based on the obtained data pattern.
Step 303: a write request to write the data block to the memory is generated based on the partial data content and the data flag.
For example, after obtaining the partial data content and the data flag, the processor generates a write request to write the data block to the memory.
Step 304: a write request is sent.
For example, the processor sends a write request to the memory controller for writing a portion of the data content to a target memory block of the memory and writing a data flag to an ECC code segment in the memory associated with the target memory block.
At least one embodiment of the present disclosure also provides a data processing method 400, for example, for a processor to generate a read request and send the read request to a memory controller, receive data read based on the read request from the memory controller, as shown in fig. 6, the method including the following steps 401-403:
step 401: a read request is sent.
For example, when the processor needs to read data, the entire memory block of the memory in which the data is stored is read and written into the cache.
Step 402: a portion of data content read from a target memory block of a memory according to a read request and a data tag read from an ECC code segment associated with the target memory block are received.
For example, after the memory controller reads a portion of the data content from the target memory block of the memory according to the read request and the data tag read from the ECC code segment associated with the target memory block, these signals are returned to the processor and received by the processor. Here, the data flag corresponds to a data pattern of the acquired data block.
Step 403: the data blocks are recovered from the partial data content according to the data pattern.
For example, the processor will complement the data block with the portion of the data content other than the portion of the data content in accordance with the data pattern indicated by the data flag in conjunction with the portion of the data content received, thereby resulting in the entire data block actually being read.
Likewise, with respect to the above-described method 300 or 400, the data pattern of the processed data block based on the partial data content includes one of the following patterns:
the data blocks are regularly distributed based on partial data content;
the portion of the data block other than the partial data content is a particular value.
For the case that the data blocks are regularly distributed based on the partial data content, for example, the data blocks are obtained by repeating n cycles based on the partial data content, where n is a positive integer greater than or equal to 2, such as 2, 4, 8, and the like. For example, for the case of n =2, the partial data content corresponds to the lower half of the data block, i.e. the lower half of the data block is processed first, while the upper half is the same as the lower half, and thus can be obtained directly from the lower half.
For the case where the portion of the data block other than the partial data content is a specific value, for example, the portion of the data block other than the partial data content is all 0's, or all 1's, or other specific data. For example, when the partial data content corresponds to the lower half of the data block, the upper half of the data block may be all 0's, or all 1's, or for example 101010 … …, etc.
For example, in at least one example, when a processor reads and writes data to and from a cache, if there is no hit in the cache, the processor needs to further read and write data from and to main memory, and this number of times is transferred in units of cache lines. That is, the data block is based on a cache line of the system cache, e.g., the length of the cache line is equal to the size of the memory block and greater than the system bandwidth for the memory, e.g., the bandwidth between the processor and the memory controller, e.g., as determined by the interconnect bandwidth connecting the processor and the memory controller.
For example, the data flag includes at least one bit, the ECC code segment includes a plurality of bits, and the length of the data flag is smaller than the length of the ECC code segment. When the data flag is one bit, there are only two values of 0 and 1, and thus only two data patterns can be represented; when the data flag is a plurality of bits (at least two bits), the plurality of bits can be used to represent a plurality of different cases of data patterns.
It is noted that the various embodiments of the present disclosure have no limitation on the type of processor (or processor core), and may be, for example, a CISC architecture (e.g., X86 architecture), a RISC architecture (e.g., ARM architecture), etc. The embodiments of the present disclosure have no limitation on the type of main memory, and may be, for example, a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), a Synchronous Link Dynamic Random Access Memory (SLDRAM), or a direct memory bus random access memory (DRRAM), or the like. Embodiments of the present disclosure are not limited as to the type of cache, and may be, for example, a Dynamic Random Access Memory (DRAM) or the like. The embodiments of the present disclosure have no limitation on the size of the cache line and the size of the memory block of the main memory, and for example, the following may be described by taking the size of the cache line and the size of the memory block as 64 bytes as examples. The embodiment of the present disclosure has no limitation on the bandwidth size between the processor and the memory controller, and may be, for example, 1/8 cache line sizes, 1/4 cache line sizes, half cache line sizes, and the like, and for example, the following may illustrate that the bandwidth between the processor and the memory controller is 256 bits (i.e., 32 bytes).
Fig. 7A shows an example when data writing is performed in an embodiment of the present disclosure. During the running of the application program, it is necessary to write data of a 64-byte cache line from the processor to the main memory, the data of the upper half and the data of the lower half of the cache line being identical to each other. The bandwidth between the processor and the memory controller is 32 bytes, so that a 64-byte cache line of data typically requires 2 transfers to be able to be transferred completely to the memory controller.
First, the processor generates a data flag (e.g., a 1-bit flag) based on the data pattern of the data block in the cache line, generates a write request based on the lower half of the data and the data flag (i.e., the 1-bit flag is included in the write request), and then sends the write request to the memory controller.
Secondly, after receiving the write request, the storage controller checks the data flag bit to know that the data of the upper half and the lower half of the data block to be written are the same, so that the data of the upper half can not be received any more subsequently, sends half of the data block (namely, the lower half of the data block) to the target address in the main memory and stores the data as the lower half of the storage block, writes the data flag representing the consistency of the data of the upper half and the data of the lower half of the data block into a redundant bit in the ECC code segment of the main memory, and sends half of the data block to the target address in the main memory again (with an offset of half the storage block length relative to the storage of the lower half) and stores the data as the upper half of the storage block, thereby recovering the complete data block in the main memory.
In this example, when the processor writes a data block corresponding to one cache line into the main memory through the memory controller, only the lower half of the data block needs to be transmitted once (1 beat), so that the data of the whole cache line can be completely recovered in the main memory.
Fig. 7B illustrates an example when data reading is performed in an embodiment of the present disclosure, corresponding to the example illustrated in fig. 7A. And when the processor needs to read the data written into the storage block in the memory in the running process of the application program, sending a read request to the memory controller, reading the data of the lower half data block of the corresponding address and the ECC code segment from the main memory by the memory controller, and obtaining a data mark from the data corresponding to the ECC code segment. According to the data mark, the memory controller knows that the data of the upper half of the data block is the same as the data of the lower half of the data block, so that the data of the upper half of the data block does not need to be read again. The memory controller returns the lower half of the data block and the data flag to the processor. The processor receives the returned lower half of the data block and the data mark, and learns that the data of the upper half of the data block is the same as the data of the lower half of the data block according to the data mark, so that a complete data block is directly obtained and can be stored in a cache line of the cache.
In at least one embodiment of the present disclosure, a storage control apparatus corresponding to the storage control method 100 is provided, as shown in fig. 8, the storage control apparatus 800 at least includes a receiving unit 801, a data flag determining unit 802, and a writing unit 803. The storage control apparatus is coupled between a host device (e.g., a processor) and a memory (e.g., a main memory) and controls write operations to the memory.
In the memory control apparatus, a receiving unit 801 is configured to receive a write request to a memory, the write request including a partial data content to be written to the memory and a data flag. The data flag determination unit 802 is configured to determine a writing mode based on the data flag. The writing unit 803 writes part of the data content to a target memory block of the memory according to the writing mode, and writes the data flag to an ECC code segment in the memory associated with the target memory block.
For example, in at least one example of this embodiment, the partial data content is a portion of a data block to be written to the target storage block, the data flag indicates a data pattern of the data block based on the partial data content, and the write pattern corresponds to the data pattern. The writing unit 803 is further configured to restore the data block in a target storage block of the memory in response to writing the partial data content to the target storage block according to the writing pattern.
At least one embodiment of the present disclosure provides a storage control apparatus, corresponding to the storage control method 200, as shown in fig. 8, the storage control apparatus 800 at least includes a receiving unit 801, a reading unit 804, a data flag determining unit 802, and a data returning unit 805. The memory control device is coupled between a host device (e.g., a processor) and a memory (e.g., a main memory) and controls read operations with respect to the memory.
In the memory control apparatus, a receiving unit 801 is configured to receive a read request for a memory. The reading unit 804 is configured to read a portion of the data content from a target memory block of the memory according to the read request, and to obtain a data flag from an ECC code segment associated with the target memory block. The data flag determination unit 802 is configured to determine a readout mode based on the data flag. The data return unit 805 is configured to return a part of the data content and the data flag according to the readout mode.
For example, in at least one example of this embodiment, the partial data content is a portion of a data block to be read from the target storage block, the data flag indicates a data pattern of the data block based on the partial data content, and the read pattern corresponds to the data pattern. The data return unit 805 is further configured to, in response to returning the partial data content and the data flag according to the readout mode, no longer read a portion of the data block other than the partial data content from the memory.
For other aspects of the above storage control apparatus of the embodiments of the present disclosure, reference may be made to the description of specific examples of the storage control method 100 or 200, which is not repeated here.
The technical effect of the storage control device is the same as that of the storage control method 100 or 200, the number of transmission times of the data block can be reduced, the transmission delay of data reading and writing is reduced, the data bandwidth is saved, and the system power consumption is reduced, which is not described herein again.
At least one embodiment of the present disclosure provides a data processing apparatus, corresponding to the data processing method 300 described above, for sending a write request to a storage control apparatus, as shown in fig. 9, the data processing apparatus 900 includes at least an operation unit 901, a request generation unit 902, and a sending unit 903. The data processing apparatus 900 is, for example, a processor or a processor core of a multi-core processor, for example, the processor may be a Central Processing Unit (CPU).
In the data processing apparatus, the operation unit 901 is configured to acquire a data pattern of a data block, generate a data flag corresponding to the data pattern, and obtain partial data content from the data block according to the data pattern; the request generation unit 902 is configured to generate a write request to write a data block to the memory based on the partial data content and the data flag; the sending unit 903 is configured to send a write request to write a part of the data content to a target memory block of the memory and to write a data flag to an ECC code segment associated with the target memory block in the memory.
At least one embodiment of the present disclosure provides a data processing apparatus, corresponding to the data processing method 400 described above, for sending a read request to a storage control apparatus and receiving read data, as shown in fig. 9, the data processing apparatus 900 includes at least a sending unit 903, a receiving unit 904, and an operating unit 901. Also, for example, the data processing apparatus is a processor or a processor core of a multi-core processor, for example, the processor may be a Central Processing Unit (CPU).
In this data processing apparatus 900, a transmitting unit 903 is configured to transmit a read request. The receiving unit 904 is configured to receive a portion of data content read from a target memory block of the memory according to the read request and a data flag read from an ECC code segment associated with the target memory block, the data flag corresponding to a data pattern of the acquired data block. The operation unit 901 is configured to restore a data block from a partial data content according to a data pattern.
The technical effect of the data processing apparatus 900 is the same as that of the data processing method 300 or 400, which can reduce the transmission times of data blocks, reduce the transmission delay of data reading and writing, save the data bandwidth, and reduce the system power consumption, and will not be described herein again.
In the above apparatus, the units, such as the receiving unit, the reading unit, the data flag determining unit, the writing unit, the data returning unit, the operating unit, and the like, may be implemented by hardware, software, firmware, and any feasible combination thereof, and the disclosure is not limited thereto.
At least one embodiment of the present disclosure further provides a storage control apparatus, including: a memory for non-transitory storage of computer-executable instructions; and a processing device for executing the computer-executable instructions, wherein the computer-executable instructions, when executed by the processing device, perform the storage control method provided by at least one embodiment of the present disclosure.
At least one embodiment of the present disclosure further provides a data processing apparatus, including: a memory for non-transitory storage of computer-executable instructions; and a processing unit, configured to execute the computer-executable instructions, where the computer-executable instructions, when executed by the processing unit, perform a data processing method according to at least one embodiment of the present disclosure.
FIG. 6 shows a schematic diagram of a storage control device or data processing device 600 according to an embodiment of the present disclosure. As shown in fig. 6, a data processing device 600 according to an embodiment of the present disclosure may include a processing unit 601 and a storage unit 602, which may be interconnected by a bus 603.
The processing unit 601 can perform various actions and processes according to a program or code stored in the storage unit 602. In particular, the processing unit 601 may be an integrated circuit chip having signal processing capabilities. For example, the processing means may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps, flows, and logic blocks disclosed in the embodiments of the disclosure may be implemented or performed. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, which may be the X86 architecture or the ARM architecture or the like.
The storage unit 602 stores computer-executable instructions, wherein the computer-executable instructions, when executed by the processing unit 601, implement a storage control method or a data processing method provided by at least one embodiment of the present disclosure. The memory unit 602 may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Synchronous Link Dynamic Random Access Memory (SLDRAM), and direct memory bus random access memory (DRRAM). It should be noted that the memories of the methods described herein are intended to comprise, without being limited to, these and any other suitable types of memory.
Embodiments of the present disclosure also provide a computer-readable storage medium for non-transitory storage of computer-executable instructions that, when executed by a processing unit, implement a storage control method or a data processing method provided by at least one embodiment of the present disclosure.
Similarly, computer-readable storage media in embodiments of the disclosure may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. It should be noted that the memories of the methods described herein are intended to comprise, without being limited to, these and any other suitable types of memory.
Embodiments of the present disclosure also provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processing unit executes the computer instructions, so that the computer device executes the storage control method or the data processing method according to the embodiment of the present disclosure.
The technical effects of the storage control device or the data processing device and the storage medium are the same as those of the storage control method 100 or 200 or the data processing method 300 or 400, and are not described herein again.
For the present disclosure, there are also the following points to be explained:
(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.
Claims (21)
1. A storage control method, comprising:
receiving a write request for a memory, wherein the write request comprises a part of data content to be written into the memory and a data mark;
determining a writing mode based on the data flag;
writing the partial data content to a target storage block of the memory according to the writing mode, and writing the data mark to an ECC code segment associated with the target storage block in the memory.
2. The storage control method according to claim 1, wherein the partial data content is a portion of a data block to be written to the target storage block, the data flag indicates a data pattern of the data block based on the partial data content, the writing pattern corresponding to the data pattern,
in response to writing the partial data content to a target storage block of the memory according to the write pattern, restoring the data block at the target storage block.
3. A storage control method, comprising:
receiving a read request for memory;
reading partial data content from a target memory block of the memory according to the read request, and acquiring a data mark from an ECC code segment associated with the target memory block;
determining a readout mode based on the data flag;
and returning the partial data content and the data mark according to the reading mode.
4. The storage control method according to claim 3, wherein the partial data content is a portion of a data block to be read out from the target storage block, the data flag indicates a data pattern of the data block based on the partial data content, the read-out pattern corresponds to the data pattern,
in response to returning the partial data content and the data flag according to the readout mode, no further portions of the data block other than the partial data content are read from memory.
5. The storage control method according to claim 2 or 4, wherein the data pattern includes one of:
the data blocks are regularly distributed based on the partial data content;
the portion of the data block other than the partial data content is a particular value.
6. The storage control method of claim 5, wherein the partial data content corresponds to a lower half of the data block.
7. The storage control method of claim 2 or 4, wherein the data block is based on a cache line of a system cache, the length of the cache line being equal to the size of the storage block and greater than a system bandwidth for the memory.
8. The memory control method according to any one of claims 1 to 4, wherein the data flag includes at least one bit, the ECC code segment includes a plurality of bits, and the length of the data flag is smaller than the length of the ECC code segment.
9. A storage control apparatus comprising:
a receiving unit configured to receive a write request to a memory, wherein the write request includes a partial data content to be written to the memory and a data flag;
a data flag determination unit configured to determine a writing mode based on the data flag;
and the writing unit is used for writing the partial data content into a target storage block of the memory according to the writing mode and writing the data mark into an ECC code segment which is associated with the target storage block in the memory.
10. A storage control apparatus comprising:
a receiving unit configured to receive a read request for a memory;
a reading unit configured to read a partial data content from a target memory block of the memory according to the read request, and acquire a data flag from an ECC code segment associated with the target memory block;
a data flag determination unit configured to determine a readout mode based on the data flag;
a data returning unit configured to return the partial data content and the data flag according to the readout mode.
11. A storage control apparatus comprising:
a memory for non-transitory storage of computer-executable instructions; and
a processing unit for executing the computer-executable instructions,
wherein the computer-executable instructions, when executed by the processing unit, perform the storage control method of any of claims 1-8.
12. A non-transitory storage medium that non-transitory stores computer-executable instructions, wherein the computer-executable instructions, when executed by a computer, perform the storage control method according to any one of claims 1 to 8.
13. A method of data processing, comprising:
acquiring a data pattern of a data block, and generating a data mark corresponding to the data pattern;
obtaining partial data content from the data block according to the data pattern;
generating a write request to write the data block to memory based on the partial data content and a data flag;
sending the write request to write the partial data content to a target memory block of the memory and to write the data flag to an ECC code segment in the memory associated with the target memory block.
14. A method of data processing, comprising:
sending a read request;
receiving a portion of data content read from a target memory block of a memory according to the read request and a data flag read from an ECC code segment associated with the target memory block, wherein the data flag corresponds to a data pattern for obtaining the data block;
recovering the data block from the partial data content according to the data pattern.
15. The data processing method of claim 13 or 14, wherein the data pattern comprises one of:
the data blocks are regularly distributed based on the partial data content;
the portion of the data block other than the partial data content is a particular value.
16. A data processing method according to claim 15, wherein said partial data content corresponds to the lower half of said data block.
17. The data processing method according to claim 13 or 14, wherein the data block is based on a cache line of a system cache, the length of the cache line being equal to the size of the memory block and larger than a system bandwidth for the memory.
18. A data processing apparatus comprising:
an operation unit configured to acquire a data pattern of a data block, generate a data flag corresponding to the data pattern, and obtain partial data content from the data block according to the data pattern;
a request generation unit configured to generate a write request to write the data block to a memory based on the partial data content and a data flag;
a sending unit configured to send the write request to write the partial data content to a target memory block of the memory and to write the data flag to an ECC code segment associated with the target memory block in the memory.
19. A data processing apparatus comprising:
a transmitting unit configured to transmit a read request;
a receiving unit configured to receive a partial data content read from a target memory block of a memory according to the read request and a data flag read from an ECC code segment associated with the target memory block, wherein the data flag corresponds to a data pattern for acquiring the data block;
an operation unit configured to recover the data block from the partial data content according to the data pattern.
20. A data processing apparatus comprising:
a memory for non-transitory storage of computer-executable instructions; and
a processing unit for executing the computer-executable instructions,
wherein the computer-executable instructions, when executed by the processing unit, perform the data processing method of any of claims 13-17.
21. A non-transitory storage medium that non-transitory stores computer-executable instructions, wherein the computer-executable instructions, when executed by a computer, perform the data processing method of any one of claims 13-17.
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