CN114115739A - Memory management method, memory storage device and memory control circuit unit - Google Patents

Memory management method, memory storage device and memory control circuit unit Download PDF

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Publication number
CN114115739A
CN114115739A CN202111417695.XA CN202111417695A CN114115739A CN 114115739 A CN114115739 A CN 114115739A CN 202111417695 A CN202111417695 A CN 202111417695A CN 114115739 A CN114115739 A CN 114115739A
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memory module
memory
time
time threshold
query
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CN202111417695.XA
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CN114115739B (en
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塞巴斯蒂安·尚
梁鸣仁
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The method comprises the following steps: sending a first operation instruction sequence to the rewritable nonvolatile memory module to instruct a first memory module in the rewritable nonvolatile memory module to execute a first operation; obtaining a first time critical value corresponding to a first operation; updating a first count value corresponding to the first memory module; and responding to the first counting value reaching the first time critical value, and sending a first query instruction sequence to the rewritable nonvolatile memory module so as to query the state of the first memory module. Therefore, the state query efficiency of the memory module can be improved.

Description

Memory management method, memory storage device and memory control circuit unit
Technical Field
The present invention relates to a memory management technology, and more particularly, to a memory management method, a memory storage device, and a memory control circuit unit.
Background
Portable electronic devices such as mobile phones and notebook computers have grown rapidly in these years, so that the demand of consumers for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable electronic devices as exemplified above.
Generally, if the rewritable nonvolatile memory module includes a plurality of memory modules, each of the memory modules may be used separately to perform data reading or data writing. To obtain the current status of each memory module (e.g., busy or standby), the memory controller typically polls each memory module for its current status in sequence at intervals by polling. However, as the number of memory modules included in the rewritable nonvolatile memory module increases, the time taken for each polling is longer, which results in a decrease in the operating efficiency of the system.
Disclosure of Invention
In view of the above, the present invention provides a memory management method, a memory storage device and a memory control circuit unit, which can improve the status query efficiency of a memory module.
An exemplary embodiment of the present invention provides a memory management method for a rewritable nonvolatile memory module. The rewritable non-volatile memory module comprises a plurality of memory modules. The memory management method comprises the following steps: sending a first operation instruction sequence to the rewritable non-volatile memory module to instruct a first memory module in the plurality of memory modules to execute a first operation; obtaining a first time threshold corresponding to the first operation; updating a first count value corresponding to the first memory module; and responding to the first counting value of the first counter reaching the first time critical value, and sending a first query instruction sequence to the rewritable non-volatile memory module so as to query the state of the first memory module.
In an exemplary embodiment of the invention, the memory management method further includes: and if the first counting value does not reach the first time critical value, not sending the first query instruction sequence.
In an exemplary embodiment of the present invention, the step of obtaining the first time threshold corresponding to the first operation comprises: obtaining the first time critical value corresponding to the first operation according to the type of the first operation.
In an exemplary embodiment of the invention, the step of obtaining the first time threshold corresponding to the first operation according to the instruction type of the first operation comprises: in response to the type of the first operation being a first type of operation, determining the first time threshold value as a first time value; and in response to the type of the first operation being a second type of operation, determine the first time threshold to be a second time value, wherein the first time value is different from the second time value.
In an exemplary embodiment of the invention, the memory management method further includes: and adjusting the first time critical value according to the actual completion time of the first operation.
In an exemplary embodiment of the present invention, the step of obtaining the first time threshold corresponding to the first operation comprises: receiving time assessment information corresponding to the first memory module from the rewritable non-volatile memory module; and determining the first time critical value according to the time evaluation information.
In an exemplary embodiment of the invention, the memory management method further includes: sending a second operation instruction sequence to the rewritable non-volatile memory module to instruct a second memory module in the plurality of memory modules to execute a second operation; obtaining a second time threshold corresponding to the second operation, wherein the second time threshold is different from the first time threshold; updating a second count value corresponding to the second memory module; and responding to the second counting value reaching the second time critical value, and sending a second query instruction sequence to the rewritable nonvolatile memory module so as to query the state of the second memory module.
In an exemplary embodiment of the invention, the memory management method further includes: sending a third operation instruction sequence to the rewritable non-volatile memory module to instruct the first memory module to execute a third operation; obtaining a third time threshold corresponding to the third operation, wherein the third time threshold is different from the first time threshold; updating a third count value corresponding to the third memory module; and sending a third query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module in response to the third count value reaching the third time critical value.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable non-volatile memory module comprises a plurality of memory modules. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: sending a first operation instruction sequence to the rewritable non-volatile memory module to instruct a first memory module in the plurality of memory modules to execute a first operation; obtaining a first time threshold corresponding to the first operation; updating a first count value corresponding to the first memory module; and responding to the first counting value reaching the first time critical value, and sending a first query instruction sequence to the rewritable nonvolatile memory module so as to query the state of the first memory module.
In an exemplary embodiment of the invention, the memory control circuit unit does not send the first query command sequence if the first count value does not reach the first time threshold.
In an exemplary embodiment of the present invention, the operation of obtaining the first time threshold corresponding to the first operation comprises: obtaining the first time critical value corresponding to the first operation according to the type of the first operation.
In an exemplary embodiment of the present invention, the operation of obtaining the first time threshold corresponding to the first operation according to the instruction type of the first operation comprises: in response to the type of the first operation being a first type of operation, determining the first time threshold value as a first time value; and in response to the type of the first operation being a second type of operation, determine the first time threshold to be a second time value, wherein the first time value is different from the second time value.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: and adjusting the first time critical value according to the actual completion time of the first operation.
In an exemplary embodiment of the present invention, the operation of obtaining the first time threshold corresponding to the first operation comprises: receiving time assessment information corresponding to the first memory module from the rewritable non-volatile memory module; and determining the first time critical value according to the time evaluation information.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: sending a second operation instruction sequence to the rewritable non-volatile memory module to instruct a second memory module in the plurality of memory modules to execute a second operation; obtaining a second time threshold corresponding to the second operation, wherein the second time threshold is different from the first time threshold; updating a second count value corresponding to the second memory module; and responding to the second counting value reaching the second time critical value, and sending a second query instruction sequence to the rewritable nonvolatile memory module so as to query the state of the second memory module.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: sending a third operation instruction sequence to the rewritable non-volatile memory module to instruct the first memory module to execute a third operation; obtaining a third time threshold corresponding to the third operation, wherein the third time threshold is different from the first time threshold; updating a third count value corresponding to the third memory module; and sending a third query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module in response to the third count value reaching the third time critical value.
An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable non-volatile memory module comprises a plurality of memory modules. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuitry to: sending a first operation instruction sequence to the rewritable non-volatile memory module to instruct a first memory module in the plurality of memory modules to execute a first operation; obtaining a first time threshold corresponding to the first operation; updating a first count value corresponding to the first memory module; and responding to the first counting value reaching the first time critical value, and sending a first query instruction sequence to the rewritable nonvolatile memory module so as to query the state of the first memory module.
In an exemplary embodiment of the invention, the memory management circuit does not send the first query command sequence if the first count value does not reach the first time threshold.
In an exemplary embodiment of the invention, the memory management circuit is further configured to: and adjusting the first time critical value according to the actual completion time of the first operation.
In an exemplary embodiment of the invention, the memory management circuit is further configured to: sending a second operation instruction sequence to the rewritable non-volatile memory module to instruct a second memory module in the plurality of memory modules to execute a second operation; obtaining a second time threshold corresponding to the second operation, wherein the second time threshold is different from the first time threshold; updating a second count value corresponding to the second memory module; and responding to the second counting value reaching the second time critical value, and sending a second query instruction sequence to the rewritable nonvolatile memory module so as to query the state of the second memory module.
In an exemplary embodiment of the invention, the memory management circuit is further configured to: sending a third operation instruction sequence to the rewritable non-volatile memory module to instruct the first memory module to execute a third operation; obtaining a third time threshold corresponding to the third operation, wherein the third time threshold is different from the first time threshold; updating a third count value corresponding to the third memory module; and sending a third query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module in response to the third count value reaching the third time critical value.
Based on the above, after the first operation instruction sequence is sent to the rewritable non-volatile memory module to instruct the first memory module to perform the first operation, the first time threshold corresponding to the first operation may be obtained and the first count value corresponding to the first memory module may be updated. Thereafter, in response to the first count value reaching the first time threshold, a first query command sequence may be sent to the rewritable non-volatile memory module to query a state of the first memory module. Compared with the conventional polling mechanism, the memory management method, the memory storage device and the memory control circuit unit provided by the exemplary embodiment of the invention can effectively improve the state query efficiency of the memory module.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the invention;
FIG. 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;
FIG. 7 is a diagram illustrating memory management circuitry in communication with a rewritable non-volatile memory module via multiple channels according to an example embodiment of the invention;
FIG. 8 is a schematic diagram illustrating querying a state of a memory module in accordance with an exemplary embodiment of the present invention;
FIG. 9 is a diagram illustrating time thresholds for different types of operations according to an example embodiment of the present invention;
FIG. 10 is a flowchart illustrating a memory management method according to an example embodiment of the invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system so that the host system can write data to or read data from the memory storage device.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 may include a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 may be connected to a system bus (system bus) 110.
In an example embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 may be connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In an exemplary embodiment, the processor 111, the RAM 112, the ROM 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner.
In an example embodiment, the memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, Near Field Communication (NFC) memory storage, wireless fidelity (WiFi) memory storage, Bluetooth (Bluetooth) memory storage, or Bluetooth low energy memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an example embodiment, the host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.
FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the invention. Referring to FIG. 3, the memory storage device 30 can be used with a host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.
FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.
The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the PCI Express (Peripheral Component Interconnect Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also conform to Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Memory (Flash) interface standard, CF interface standard, Device interface standard, and Electronic drive interface (Electronic interface), IDE) standard or other suitable standard. The connection interface unit 41 may be packaged with the memory control circuit unit 42 in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.
The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to commands of the host system 11.
The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In an exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, a physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit region includes 32 physical sectors, and one physical sector has a size of 512 bit groups (bytes, B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).
FIG. 5 is a diagram illustrating a memory control circuit unit according to an exemplary embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53.
The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 51 is explained below, it is equivalent to the operation of the memory control circuit unit 42.
In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the RAM of the memory management circuit 51. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 43. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory reading circuit is used for issuing a reading instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 43 so as to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may issue other types of command sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.
The host interface 52 is connected to the memory management circuit 51. The memory management circuitry 51 may communicate with the host system 11 through a host interface 52. The host interface 52 is used for receiving and recognizing commands and data transmitted by the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 may transmit data to the host system 11 through the host interface 52. In the exemplary embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.
The memory interface 53 is connected to the memory management circuit 51 and is used for accessing the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format accepted by the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits a corresponding command sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
In an exemplary embodiment, the memory control circuitry unit 42 further includes error checking and correction circuitry 54, buffer memory 55, and power management circuitry 56.
The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 43. Thereafter, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 54 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.
The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is a power supply connected to the memory management circuit 51 and used to control the memory storage device 10.
In an example embodiment, the rewritable nonvolatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of FIG. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of FIG. 5 may include a flash memory management circuit.
FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable nonvolatile memory module 43 into a storage area 601 and an idle (spare) area 602.
In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also refer to a Virtual Block (VB). A virtual block may include a plurality of physical addresses or a plurality of physical programming units.
The physical units 610(0) -610 (A) in the storage area 601 are used to store user data (e.g., user data from the host system 11 of FIG. 1). For example, entity units 610(0) -610 (A) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610(a +1) to 610(B) in the idle region 602 store no data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle region 602. In addition, the physical cells in the idle region 602 (or the physical cells not storing valid data) can be erased. When new data is written, one or more physical units may be fetched from the idle region 602 to store the new data. In an exemplary embodiment, the idle region 602 is also referred to as a free pool.
Memory management circuitry 51 may configure logic units 612(0) - (612 (C) to map physical units 610(0) - (610 (A) in memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a Logical Address may include one or more Logical Block Addresses (LBAs) or other Logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic program unit or be composed of a plurality of continuous or discontinuous logic addresses.
It is noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is mapped by a certain logic unit, it indicates that the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not currently mapped by any logic unit, it indicates that the data currently stored in the entity unit is invalid.
The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing mapping relationships between the logical units and the physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.
FIG. 7 is a diagram illustrating a memory management circuit in communication with a rewritable non-volatile memory module via multiple channels according to an example embodiment of the invention. Referring to FIG. 7, the rewritable nonvolatile memory module 43 may include a plurality of memory modules 71(0) -71 (n). n can be any positive integer. Each of the memory modules 71(0) -71 (n) may include a plurality of physical units. Each of the memory modules 71(0) -71 (n) can independently perform data read, write, or erase operations. In addition, a plurality of the memory modules 71(0) -71 (n) can also perform data reading, writing or erasing operations in parallel. For example, one of the memory modules 71(0) -71 (n) may refer to a plane (plane), a Chip Enable (CE) area, a die (die), or other physical management unit.
The memory management circuit 51 can communicate with the memory modules 71(0) to 71(n) via the channels 70(0) to 70(n), respectively. For example, the memory management circuit 51 may issue an operation command to the memory module 71(i) via the channel 70 (i). The memory module 71(i) can receive the operation instruction via the channel 70(i) and execute the corresponding operation behavior. In addition, memory module 71(i) may transmit data back to memory management circuitry 51 via channel 70 (i). Alternatively, in an exemplary embodiment, multiple memory modules of the memory modules 71(0) -71 (n) may share the same channel 70 (i).
The memory management circuit 51 can send an operation command sequence (also referred to as a first operation command sequence) to the rewritable nonvolatile memory module 43 to instruct one of the memory modules 71(0) -71 (n) (also referred to as a first memory module) to perform a specific operation (also referred to as a first operation). For example, assuming that the first memory module is the memory module 71(i), the memory module 71(i) may perform the first operation according to the first operation instruction sequence. For example, the first operation may include reading data from at least one physical cell in the memory module 71(i), writing data to at least one physical cell in the memory module 71(i), or erasing at least one physical cell in the memory module 71 (i).
In addition, the memory management circuit 51 may obtain a time threshold (also referred to as a first time threshold) corresponding to the first operation. The first time threshold may be close to a time required for the first memory module to perform the first operation. For example, assuming that the time required for the first memory module to completely perform the first operation is approximately 30 microseconds (μ s), the first time threshold may be close to and/or slightly less than 30 μ s.
After sending the first sequence of operation instructions, the memory management circuit 51 may continuously update the count value (also referred to as the first count value) corresponding to the first memory module. The first count value may positively correlate to the length of time that elapses after the memory management circuit 51 issues the first sequence of operation instructions. For example, assume that the first count value is 20, indicating that about 20 microseconds has elapsed after the memory management circuit 51 issues the first operation instruction sequence.
In an example embodiment, the memory management circuit 51 may determine whether the first count value reaches (e.g., is greater than or equal to) the first time threshold. If the first count value reaches the first time threshold, it indicates that the first operation performed by the first memory module has a high probability of being completed or nearly completed. If the first operation executed by the first memory module is completed, the first memory module can be switched to a standby (ready) state. In the standby state, the first memory module may begin to perform the next operation. In addition, if the first count value does not reach the first time threshold, it indicates that the first operation executed by the first memory module has a high probability of not being completed. If the first operation performed by the first memory module is not completed, the first memory module may be continuously in a busy (busy) state. In the busy state, the first memory module is unable to perform other operations.
In response to the first count value reaching the first time threshold, the memory management circuit 51 may send a query command sequence (also referred to as a first query command sequence) to the rewritable nonvolatile memory module 43 to query the status of the first memory module. For example, assuming that the first memory module is memory module 71(i), the first query instruction sequence may be transmitted via channel 70 (i). In response to the first query command sequence, the rewritable nonvolatile memory module 43 can send a status message (also referred to as a first status message) back to the memory management circuit 51. The memory management circuit 51 can obtain the status of the first memory module according to the status information. For example, assuming that the first memory module is memory module 71(i), the first status information may be transmitted via channel 70 (i). Alternatively, in an exemplary embodiment, the memory management circuit 51 may not send the first query command sequence if the first count value does not reach the first time threshold.
FIG. 8 is a diagram illustrating querying a state of a memory module, according to an exemplary embodiment of the present invention. Referring to fig. 7 and 8, in an exemplary embodiment, at a certain time point (also referred to as a first time point), the memory management circuit 51 may send a query instruction sequence to the rewritable nonvolatile memory module 43 to query the states of the memory modules 71(0) and 71 (2). However, the memory module 71(1) is skipped. In response to the polling command sequence, memory modules 71(0) and 71(2) may report their respective statuses back to memory management circuit 51, but memory module 71(1) does not need to report their statuses back to memory management circuit 51. Thus, status queries may be performed for memory modules whose tasks are about to complete or have completed (e.g., memory modules 71(0) and 71 (2)). On the other hand, for the memory module whose task is apparently not completed (for example, the memory module 71(1)), the status of the memory module can be temporarily not queried, so as to avoid occupying the communication bandwidth between the memory management circuit 51 and the rewritable nonvolatile memory module 43. Furthermore, in the example embodiment of fig. 8, at a first point in time, the status of more or fewer memory modules may be queried and/or more or fewer memory modules may be skipped, as the invention is not limited.
In an example embodiment, the memory management circuit 51 may obtain a first time threshold corresponding to the first operation according to the type of the first operation. For example, the first time threshold obtained may be different according to different types of first operations.
In an example embodiment, in response to the type of the first operation being a first type of operation, the memory management circuit 51 may determine the first time threshold to be a certain time value (also referred to as a first time value). Alternatively, in response to the type of the first operation being the second type of operation, the memory management circuit 51 may determine the first time threshold as another time value (also referred to as a second time value). The first time value may be different from the second time value. For example, assuming that the first operation is a read operation, the first time threshold may be determined to be 27 or 30 microseconds. Alternatively, assuming the first operation is a write operation, the first time threshold may be determined to be 115 microseconds or 120 microseconds.
FIG. 9 is a diagram illustrating time thresholds for different types of operations according to an example embodiment of the invention. Referring to FIG. 9, in an exemplary embodiment, the memory management circuit 51 may look up the table information 91 to obtain a time threshold corresponding to a particular type of operation. The table information 91 may be stored in the rewritable nonvolatile memory module 43. For example, the table information 91 may record time thresholds t (a), t (B), and t (C) corresponding to different types of operations (a), (B), and (C), respectively. For example, operation (a), operation (B), and operation (C) may be a read operation, a write operation, and an erase operation, respectively. According to the type of the first operation, the memory management circuit 51 may obtain a first time threshold corresponding to the first operation from the table information 91. For example, assuming that the first operation belongs to operation (a), the memory management circuit 51 may set the first time threshold according to the time threshold t (a).
In an example embodiment, the memory management circuit 51 may record the actual completion time of the first operation. Then, the memory management circuit 51 may adjust the first time threshold according to the actual completion time of the first operation. For example, assume that the first operation belongs to operation (a) in the table information 91. After the first memory module performs the first operation, the memory management circuit 51 may record the actual completion time of the first operation and update or adjust the time threshold t (a) in the table information 91 according to the actual completion time. Thereby, the table information 91 can be continuously maintained according to the latest state of each memory module.
In an example embodiment, after sending the first operation instruction sequence, the memory management circuit 51 may receive the time evaluation information corresponding to the first memory module from the rewritable non-volatile memory module 43. This time evaluation information may reflect the length of time required for the first memory module to perform the first operation. For example, assume that the first memory module is memory module 70(i) and the length of time required for memory module 70(i) to completely perform the first operation is approximately 30 microseconds. The rewritable non-volatile memory module 43 may communicate the time evaluation information corresponding to the first memory module to the memory management circuit 51 via channel 70 (i). The length of time required for the memory management circuit 51 to obtain the memory module 70(i) to completely execute the first operation according to the time evaluation information is about 30 microseconds. Then, the memory management circuit 51 may determine the first time threshold according to the time evaluation information, for example, set the first time threshold to 27 μ sec (e.g., 30 × 0.9 ═ 27).
Referring back to FIG. 7, in an exemplary embodiment, the memory management circuit 51 can send another operation instruction sequence (also referred to as a second operation instruction sequence) to the rewritable non-volatile memory module 43 to instruct another memory module (also referred to as a second memory module) in the rewritable non-volatile memory module 43 to perform a specific operation (also referred to as a second operation). Memory management circuit 51 may obtain a time threshold corresponding to the second operation (also referred to as a second time threshold). In particular, the second time threshold may be different from the first time threshold. For example, the first time threshold may be 27 microseconds (corresponding to the first operation being a read operation) and the second time threshold may be 115 microseconds (corresponding to the second operation being a write operation).
After sending the second operation instruction sequence, the memory management circuit 51 may continuously update the count value (also referred to as a second count value) corresponding to the second memory module. In response to the second count value reaching the second time threshold, the memory management circuit 51 may send a query command sequence (also referred to as a second query command sequence) to the rewritable nonvolatile memory module 43 to query the status of the second memory module. In addition, if the second count value does not reach the second time threshold, the memory management circuit 51 may not send the second query command sequence. For details of the operation, reference may be made to the description of the foregoing exemplary embodiments, which are not repeated herein.
In an example embodiment, the memory management circuit 51 may send another operation instruction sequence (also referred to as a third operation instruction sequence) to the rewritable non-volatile memory module 43 to instruct the first memory module to perform a specific operation (also referred to as a third operation). The memory management circuit 51 may obtain a time threshold corresponding to a third operation (also referred to as a third time threshold). In particular, the third time threshold may be different from the first time threshold. For example, the first time threshold may be 27 microseconds (corresponding to the first operation being a read operation) and the third time threshold may be 115 microseconds (corresponding to the third operation being a write operation).
After sending the third sequence of operational instructions, the memory management circuit 51 may continue to update the first count value corresponding to the first memory module. In response to the first count value reaching the third time threshold, the memory management circuit 51 may send a query command sequence (also referred to as a third query command sequence) to the rewritable non-volatile memory module 43 to query the status of the first memory module. In addition, if the first count value does not reach the third time threshold, the memory management circuit 51 may not send the third query instruction sequence. For details of the operation, reference may be made to the description of the foregoing exemplary embodiments, which are not repeated herein.
In an exemplary embodiment, if the status of a memory module (e.g., the first memory module) obtained by the polling is busy, the memory module may be added to a polling list. Then, the memory management circuit 51 may send the polling command sequence again to poll the state of the memory module at intervals until the state of the memory module is switched to the standby state. In addition, the memory management circuit 51 may issue a new operation command sequence to the memory module in the standby state to instruct the memory module in the standby state to perform the next operation.
FIG. 10 is a flowchart illustrating a memory management method according to an example embodiment of the invention. Referring to fig. 10, in step S1001, a first operation instruction sequence is sent to the rewritable non-volatile memory module to instruct the first memory module to perform a first operation. In step S1002, a first time threshold corresponding to a first operation is obtained. In step S1003, a first count value corresponding to the first memory module is updated. In step S1004, it is determined whether the first count value reaches the first time threshold. In response to the first count value reaching the first time threshold, in step S1005, a first query command sequence is sent to the rewritable non-volatile memory module to query the state of the first memory module. Alternatively, if the first count value does not reach the first time threshold, step S1004 may be repeated.
However, the steps in fig. 10 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 10 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In summary, the exemplary embodiments of the invention can set the time threshold for the operation task executed by the specific memory module. Thereafter, the status of the memory module is queried only when the count value corresponding to the memory module satisfies the time threshold. Therefore, even if the total number of the memory modules is continuously increased, the state query efficiency of the memory modules can be effectively improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (24)

1. A memory management method for a rewritable non-volatile memory module including a plurality of memory modules, the memory management method comprising:
sending a first operation instruction sequence to the rewritable non-volatile memory module to instruct a first memory module in the plurality of memory modules to execute a first operation;
obtaining a first time threshold corresponding to the first operation;
updating a first count value corresponding to the first memory module; and
and sending a first query instruction sequence to the rewritable nonvolatile memory module to query the state of the first memory module in response to the first count value reaching the first time critical value.
2. The memory management method of claim 1, further comprising:
and if the first counting value does not reach the first time critical value, not sending the first query instruction sequence.
3. The memory management method of claim 1, wherein obtaining a first time threshold corresponding to the first operation comprises:
obtaining the first time critical value corresponding to the first operation according to the type of the first operation.
4. The memory management method of claim 3, wherein obtaining the first time threshold corresponding to the first operation according to the instruction type of the first operation comprises:
in response to the type of the first operation being a first type of operation, determining the first time threshold value as a first time value; and
determine the first time threshold as a second time value in response to the type of the first operation being a second type of operation,
wherein the first time value is different from the second time value.
5. The memory management method of claim 1, further comprising:
and adjusting the first time critical value according to the actual completion time of the first operation.
6. The memory management method of claim 1, wherein obtaining the first time threshold corresponding to the first operation comprises:
receiving time assessment information corresponding to the first memory module from the rewritable non-volatile memory module; and
and determining the first time critical value according to the time evaluation information.
7. The memory management method of claim 1, further comprising:
sending a second operation instruction sequence to the rewritable non-volatile memory module to instruct a second memory module in the plurality of memory modules to execute a second operation;
obtaining a second time threshold corresponding to the second operation, wherein the second time threshold is different from the first time threshold;
updating a second count value corresponding to the second memory module; and
and sending a second query instruction sequence to the rewritable non-volatile memory module to query the state of the second memory module in response to the second count value reaching the second time critical value.
8. The memory management method of claim 1, further comprising:
sending a third operation instruction sequence to the rewritable non-volatile memory module to instruct the first memory module to execute a third operation;
obtaining a third time threshold corresponding to the third operation, wherein the third time threshold is different from the first time threshold;
updating a third count value corresponding to the first memory module; and
and sending a third query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module in response to the third count value reaching the third time critical value.
9. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module including a plurality of memory modules; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is to:
sending a first operation instruction sequence to the rewritable non-volatile memory module to instruct a first memory module in the plurality of memory modules to execute a first operation;
obtaining a first time threshold corresponding to the first operation;
updating a first count value corresponding to the first memory module; and
and sending a first query instruction sequence to the rewritable nonvolatile memory module to query the state of the first memory module in response to the first count value reaching the first time critical value.
10. The memory storage device of claim 9, wherein the memory control circuitry unit does not send the first query command sequence if the first count value does not reach the first time threshold.
11. The memory storage device of claim 9, wherein obtaining a first time threshold corresponding to the first operation comprises:
obtaining the first time critical value corresponding to the first operation according to the type of the first operation.
12. The memory storage device of claim 11, wherein, in accordance with the instruction type of the first operation, obtaining the first time threshold corresponding to the first operation comprises:
in response to the type of the first operation being a first type of operation, determining the first time threshold value as a first time value; and
determine the first time threshold as a second time value in response to the type of the first operation being a second type of operation,
wherein the first time value is different from the second time value.
13. The memory storage device of claim 9, wherein the memory control circuitry unit is further configured to:
and adjusting the first time critical value according to the actual completion time of the first operation.
14. The memory storage device of claim 9, wherein obtaining the first time threshold corresponding to the first operation comprises:
receiving time assessment information corresponding to the first memory module from the rewritable non-volatile memory module; and
and determining the first time critical value according to the time evaluation information.
15. The memory storage device of claim 9, wherein the memory control circuitry unit is further configured to:
sending a second operation instruction sequence to the rewritable non-volatile memory module to instruct a second memory module in the plurality of memory modules to execute a second operation;
obtaining a second time threshold corresponding to the second operation, wherein the second time threshold is different from the first time threshold;
updating a second count value corresponding to the second memory module; and
and sending a second query instruction sequence to the rewritable non-volatile memory module to query the state of the second memory module in response to the second count value reaching the second time critical value.
16. The memory storage device of claim 9, wherein the memory control circuitry unit is further configured to:
sending a third operation instruction sequence to the rewritable non-volatile memory module to instruct the first memory module to execute a third operation;
obtaining a third time threshold corresponding to the third operation, wherein the third time threshold is different from the first time threshold;
updating a third count value corresponding to the first memory module; and
and sending a third query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module in response to the third count value reaching the third time critical value.
17. A memory control circuit unit for controlling a rewritable nonvolatile memory module including a plurality of memory modules, the memory control circuit unit comprising:
a host interface for connecting to a host system;
a memory interface for connecting to a rewritable non-volatile memory module; and
a memory management circuit connected to the host interface and the memory interface,
wherein the memory management circuitry is to:
sending a first operation instruction sequence to the rewritable non-volatile memory module to instruct a first memory module in the plurality of memory modules to execute a first operation;
obtaining a first time threshold corresponding to the first operation;
updating a first count value corresponding to the first memory module; and
and sending a first query instruction sequence to the rewritable nonvolatile memory module to query the state of the first memory module in response to the first count value reaching the first time critical value.
18. The memory control circuit unit of claim 17, wherein the memory management circuit does not send the first query command sequence if the first count value does not reach the first time threshold.
19. The memory control circuit unit of claim 17, wherein obtaining a first time threshold corresponding to the first operation comprises:
obtaining the first time critical value corresponding to the first operation according to the type of the first operation.
20. The memory control circuitry unit of claim 19, wherein obtaining the first time threshold corresponding to the first operation according to the instruction type of the first operation comprises:
in response to the type of the first operation being a first type of operation, determining the first time threshold value as a first time value; and
determine the first time threshold as a second time value in response to the type of the first operation being a second type of operation,
wherein the first time value is different from the second time value.
21. The memory control circuitry unit of claim 17, wherein the memory management circuitry is further configured to:
and adjusting the first time critical value according to the actual completion time of the first operation.
22. The memory control circuitry unit of claim 17, wherein obtaining the first time threshold corresponding to the first operation comprises:
receiving time assessment information corresponding to the first memory module from the rewritable non-volatile memory module; and
and determining the first time critical value according to the time evaluation information.
23. The memory control circuitry unit of claim 17, wherein the memory management circuitry is further configured to:
sending a second operation instruction sequence to the rewritable non-volatile memory module to instruct a second memory module in the plurality of memory modules to execute a second operation;
obtaining a second time threshold corresponding to the second operation, wherein the second time threshold is different from the first time threshold;
updating a second count value corresponding to the second memory module; and
and sending a second query instruction sequence to the rewritable non-volatile memory module to query the state of the second memory module in response to the second count value reaching the second time critical value.
24. The memory control circuitry unit of claim 17, wherein the memory management circuitry is further configured to:
sending a third operation instruction sequence to the rewritable non-volatile memory module to instruct the first memory module to execute a third operation;
obtaining a third time threshold corresponding to the third operation, wherein the third time threshold is different from the first time threshold;
updating a third count value corresponding to the first memory module; and
and sending a third query instruction sequence to the rewritable non-volatile memory module to query the state of the first memory module in response to the third count value reaching the third time critical value.
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