CN114115022A - FPGA hardware acceleration array upgrading method and system - Google Patents

Abstract

The application provides a method and a system for upgrading an FPGA hardware acceleration array, and the system comprises the following steps: cloud data center, at least one terminal equipment. The cloud data center is used for storing at least one hardware acceleration program; and sending at least one upgrading instruction to the terminal equipment according to the hardware acceleration program. The terminal device is used for receiving an upgrading instruction sent by the cloud data center and loading the FPGA upgrading program to the FPGA chip to be upgraded in response to the upgrading instruction so as to complete the task of upgrading the FPGA chip. According to the method and the device, the ID of each FPGA chip in the terminal equipment is identified, and the control module switches the upgrading channel according to the ID of the FPGA chip, so that the upgrading of each FPGA chip in the hardware acceleration array is realized.

Description

FPGA hardware acceleration array upgrading method and system

Technical Field

The application relates to the technical field of hardware acceleration arrays, in particular to a method and a system for upgrading an FPGA hardware acceleration array.

Background

The Internet of things connects different things, people and the like together by utilizing various communication technologies to form person-to-thing connection and thing-to-thing connection, and various Internet of things are formed, so that city construction and economic development are promoted. With the application of the internet of things, data processing becomes richer and more important. A Field-programmable Gate Array (FPGA) is widely used in data hardware acceleration processing. Through hardware accelerated calculation of the FPGA, people can know and master real-time running states of important assets such as assets and equipment, and the real-time running states play an important role in equipment maintenance, personnel/equipment monitoring, emergency plans, intelligent decision making and the like.

The hardware acceleration array comprises a plurality of FPGA chips, when the FPGA chips are used for logic block upgrading, the burn-in board loading upgrading is generally carried out under the condition of power failure through Joint Test Action Group (JTAG) downloading lines, and the method is only suitable for the development and debugging stage of the FPGA chips. Once the FPGA chip is put into use after being installed in a case, JTAG download lines are difficult to insert in use, however, power failure is not allowed for many devices, and upgrading management is more difficult for the situation that a plurality of hardware acceleration arrays exist.

Disclosure of Invention

The application provides an FPGA hardware acceleration array upgrading method and system, by identifying the ID of each FPGA chip in the hardware acceleration array, a Central Processing Unit (CPU) switches an upgrading channel according to the ID of the FPGA chip, and upgrading of each FPGA chip in the hardware acceleration array is achieved.

In a first aspect, the present application provides an FPGA hardware acceleration array upgrading system, including: the system comprises a cloud data center and at least one terminal device;

the cloud data center is used for storing at least one hardware acceleration program; sending at least one upgrading instruction to the terminal equipment according to the hardware acceleration program;

the terminal device is used for receiving the upgrading instruction sent by the cloud data center and loading an FPGA upgrading program to an FPGA chip to be upgraded in response to the upgrading instruction so as to complete the task of upgrading the FPGA chip.

Optionally, the terminal device includes a control module, a bus channel switching control module, and a hardware acceleration array module;

the control module is used for responding to the upgrading instruction, acquiring IDs corresponding to a plurality of FPGA chips in the hardware acceleration array module, and judging whether the corresponding FPGA chip is an FPGA chip to be upgraded or not according to the IDs;

sending a loading instruction to the bus channel switching control module under the condition that the FPGA chip corresponding to the ID is the FPGA chip to be upgraded, wherein the loading instruction is used for instructing to load the FPGA upgrading program to the FPGA chip to be upgraded corresponding to the ID;

the bus channel switching control module is used for managing and switching the bus channels according to the ID so as to realize the upgrading of different FPGA chips;

and the hardware acceleration array module is used for responding to the FPGA upgrading program and carrying out hardware acceleration calculation according to a preset functional algorithm so as to complete a corresponding upgrading task.

Optionally, the terminal device further includes a bus channel isolation module and a power supply unit;

and the bus channel isolation module is used for responding to a switching instruction sent by the bus channel switching control module and switching a channel to the FPGA chip to be upgraded.

And the power supply unit is used for supplying power to the control module, the bus channel switching control module, the hardware acceleration array module and the bus channel isolation module so as to ensure that the task is normally executed.

Optionally, the hardware acceleration array module further includes a plurality of hardware acceleration units, and the hardware acceleration units are configured to assign the corresponding ID to each FPGA chip to be upgraded in the hardware acceleration array module.

Optionally, the cloud data center and the terminal are connected through LTE 4G or NB IoT communication.

Optionally, the cloud data center and the terminal are connected through ethernet communication.

In a second aspect, the present application provides a method for upgrading an FPGA hardware acceleration array, which specifically includes the following steps:

responding to an upgrading instruction, and acquiring IDs corresponding to a plurality of FPGA chips in a hardware acceleration array;

judging whether the corresponding FPGA chip is an FPGA chip to be upgraded or not according to the ID;

and under the condition that the FPGA chip corresponding to the ID is the FPGA chip to be upgraded, loading an FPGA upgrading program to the FPGA chip to be upgraded corresponding to the ID so as to complete the task of upgrading the FPGA chip.

According to the technical scheme, the application provides an FPGA hardware acceleration array upgrading method and system, and the system comprises: cloud data center, at least one terminal equipment. The cloud data center is used for storing at least one hardware acceleration program; and sending at least one upgrading instruction to the terminal equipment according to the hardware acceleration program. The terminal device is used for receiving an upgrading instruction sent by the cloud data center and loading the FPGA upgrading program to the FPGA chip to be upgraded in response to the upgrading instruction so as to complete the task of upgrading the FPGA chip. According to the method and the device, the ID of each FPGA chip in the terminal equipment is identified, and the control module switches the upgrading channel according to the ID of the FPGA chip, so that the upgrading of each FPGA chip in the hardware acceleration array is realized.

Drawings

In order to more clearly explain the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of an FPGA hardware accelerated array upgrade system;

fig. 2 is a schematic structural diagram of a bus channel switching control module and a bus channel isolation module in an FPGA hardware accelerated array upgrade system.

Detailed Description

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following examples do not represent all embodiments consistent with the present application. But merely as exemplifications of systems and methods consistent with certain aspects of the application, as recited in the claims.

Referring to fig. 1, a schematic structural diagram of an FPGA hardware accelerated array upgrade system is shown. The application provides an FPGA hardware acceleration array upgrading system, includes: the system comprises a cloud data center and at least one terminal device, wherein the terminal device comprises a control module, a bus channel switching control module, bus channel isolation module hardware, an acceleration array module and a power supply unit.

The cloud data center is used for storing at least one hardware acceleration program; and sending at least one upgrading instruction to the terminal equipment according to the hardware acceleration program.

And the terminal equipment is used for receiving the upgrading instruction sent by the cloud data center and loading the FPGA upgrading program to the FPGA chip to be upgraded in response to the upgrading instruction so as to complete the task of upgrading the FPGA chip.

And the control module is used for responding to the upgrading instruction, acquiring IDs corresponding to the FPGA chips in the hardware acceleration array module, and judging whether the corresponding FPGA chip is the FPGA chip to be upgraded or not according to the IDs.

And under the condition that the FPGA chip corresponding to the ID is the FPGA chip to be upgraded, sending a loading instruction to the bus channel switching control module, wherein the loading instruction is used for instructing to load the FPGA upgrading program to the FPGA chip to be upgraded corresponding to the ID.

And the bus channel switching control module is used for managing and switching the bus channels according to the ID so as to realize upgrading of different FPGA chips.

And the hardware acceleration array module is used for responding to the FPGA upgrading program and carrying out hardware acceleration calculation according to a preset functional algorithm so as to complete a corresponding upgrading task.

And the bus channel isolation module is used for responding to a switching instruction sent by the bus channel switching control module and switching the channel to the FPGA chip to be upgraded.

And the power supply unit is used for supplying power to the control module, the bus channel switching control module, the hardware acceleration array module and the bus channel isolation module so as to ensure the normal execution of the task.

In some embodiments, the hardware acceleration array module further includes a plurality of hardware acceleration units, and the hardware acceleration units are configured to assign a corresponding ID to each FPGA chip to be upgraded in the hardware acceleration array module.

In some embodiments, the cloud data center may be a self-built HTTP server, MQTT server, or a public cloud.

In some embodiments, the cloud data center and the terminal are connected through LTE 4G or NB IoT communication, where the LTE 4G or NB IoT communication is wireless data transmission.

In some embodiments, the cloud data center and the terminal are connected through ethernet communication, wherein the ethernet communication is wired data transmission.

In some embodiments, the user may update the required hardware acceleration engineering program, such as calculation of electrical energy, a platform topology identification algorithm, a fire probability study and judgment algorithm, and the like, by using the cloud data center.

In some embodiments, the control module may be an ARM core processor with a strong processing capability, an MCU running for management with low power consumption, or other types of processor modules.

In some embodiments, the bus channel switching management module may be one or more of a hardware analog switch device, a programmable logic device CPLD, an erasable programmable logic device EPLD, and a field programmable gate array FPGA.

The specific operation of the above system will be described as follows:

the cloud data center stores at least one hardware acceleration program. The cloud data center sends at least one upgrading instruction to the terminal equipment after receiving the operation of the hardware acceleration program input by the user. And the control module in the terminal equipment starts a corresponding upgrading task after receiving the upgrading instruction, and receives a hardware acceleration program needing upgrading from the cloud data center. The control module starts an upgrading task, judges which FPGA chip needs to be upgraded by reading the ID corresponding to each FPGA chip in the hardware acceleration array, starts the bus channel switching management module according to the ID of the FPGA chip needing to be upgraded, controls the bus channel isolation module to switch the bus channel to the FPGA chip corresponding to the ID, and loads an FPGA upgrading program to the FPGA chip corresponding to the ID. And the hardware acceleration array module responds to the FPGA upgrading program and performs hardware acceleration calculation according to a preset functional algorithm so as to complete a corresponding upgrading task. After the upgrading task of the current hardware acceleration array module is completed, the upgrading result is fed back to the control module, and the control module feeds back the result to the cloud data center.

Fig. 2 is a schematic structural diagram of a bus channel switching control module and a bus channel isolation module in an FPGA hardware accelerated array upgrade system. The bus channel switching management module can be one or more of a hardware analog switch device, a programmable logic device CPLD, an erasable programmable logic device EPLD and a field programmable gate array FPGA. And after the bus channel switching management module is started, the bus channel is switched by controlling the bus channel isolation module so as to realize the connection with the FPGA chip corresponding to the ID.

Further, the application provides an FPGA hardware acceleration array upgrading method, which specifically comprises the following steps:

responding to an upgrading instruction, and acquiring IDs corresponding to a plurality of FPGA chips in a hardware acceleration array;

judging whether the corresponding FPGA chip is an FPGA chip to be upgraded or not according to the ID;

and under the condition that the FPGA chip corresponding to the ID is the FPGA chip to be upgraded, loading an FPGA upgrading program to the FPGA chip to be upgraded corresponding to the ID so as to complete the task of upgrading the FPGA chip.

The information interaction and execution process between the devices in the system are based on the same concept as the embodiment of the method of the present application, and specific contents may be referred to the description in the embodiment of the system of the present application, and are not described herein again.

According to the technical scheme, the application provides an FPGA hardware acceleration array upgrading method and system, and the system comprises: cloud data center, at least one terminal equipment. The cloud data center is used for storing at least one hardware acceleration program; and sending at least one upgrading instruction to the terminal equipment according to the hardware acceleration program. The terminal device is used for receiving an upgrading instruction sent by the cloud data center and loading the FPGA upgrading program to the FPGA chip to be upgraded in response to the upgrading instruction so as to complete the task of upgrading the FPGA chip. According to the method and the device, the ID of each FPGA chip in the terminal equipment is identified, and the control module switches the upgrading channel according to the ID of the FPGA chip, so that the upgrading of each FPGA chip in the hardware acceleration array is realized.

The embodiments provided in the present application are only a few examples of the general concept of the present application, and do not limit the scope of the present application. Any other embodiments extended according to the scheme of the present application without inventive efforts will be within the scope of protection of the present application for a person skilled in the art.

Claims (7)

1. An FPGA hardware accelerated array upgrade system, comprising: the system comprises a cloud data center and at least one terminal device;

the cloud data center is used for storing at least one hardware acceleration program; sending at least one upgrading instruction to the terminal equipment according to the hardware acceleration program;

the terminal device is used for receiving the upgrading instruction sent by the cloud data center and loading an FPGA upgrading program to an FPGA chip to be upgraded in response to the upgrading instruction so as to complete the task of upgrading the FPGA chip.

2. The system of claim 1, wherein the terminal device comprises a control module, a bus channel switching control module and a hardware acceleration array module;

the control module is used for responding to the upgrading instruction, acquiring IDs corresponding to a plurality of FPGA chips in the hardware acceleration array module, and judging whether the corresponding FPGA chip is an FPGA chip to be upgraded or not according to the IDs;

sending a loading instruction to the bus channel switching control module under the condition that the FPGA chip corresponding to the ID is the FPGA chip to be upgraded, wherein the loading instruction is used for instructing to load the FPGA upgrading program to the FPGA chip to be upgraded corresponding to the ID;

the bus channel switching control module is used for managing and switching the bus channels according to the ID so as to realize the upgrading of different FPGA chips;

and the hardware acceleration array module is used for responding to the FPGA upgrading program and carrying out hardware acceleration calculation according to a preset functional algorithm so as to complete a corresponding upgrading task.

3. The system of claim 2, wherein the terminal device further comprises a bus lane isolation module and a power supply unit;

the bus channel isolation module is used for responding to a switching instruction sent by the bus channel switching control module and switching a channel to the FPGA chip to be upgraded;

and the power supply unit is used for supplying power to the control module, the bus channel switching control module, the hardware acceleration array module and the bus channel isolation module so as to ensure that the task is normally executed.

4. The system according to claim 3, wherein the hardware acceleration array module further comprises a plurality of hardware acceleration units, and the hardware acceleration units are configured to assign the corresponding ID to each FPGA chip to be upgraded in the hardware acceleration array module.

5. The system of claim 1, wherein the cloud data center and the terminal are communicatively connected via an LTE 4G or NB IoT.

6. The system of claim 1, wherein the cloud data center and the terminal are connected by ethernet communication.

7. An FPGA hardware acceleration array upgrading method is characterized by specifically comprising the following steps:

responding to an upgrading instruction, and acquiring IDs corresponding to a plurality of FPGA chips in a hardware acceleration array;

judging whether the corresponding FPGA chip is an FPGA chip to be upgraded or not according to the ID;

and under the condition that the FPGA chip corresponding to the ID is the FPGA chip to be upgraded, loading an FPGA upgrading program to the FPGA chip to be upgraded corresponding to the ID so as to complete the task of upgrading the FPGA chip.

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