CN114095012B - Level conversion circuit - Google Patents
Level conversion circuit Download PDFInfo
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- CN114095012B CN114095012B CN202111144563.4A CN202111144563A CN114095012B CN 114095012 B CN114095012 B CN 114095012B CN 202111144563 A CN202111144563 A CN 202111144563A CN 114095012 B CN114095012 B CN 114095012B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
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Abstract
The invention relates to a level switching circuit, which comprises a first PMOS tube, a second PMOS tube and a third PMOS tube, wherein the first PMOS tube is connected between VBAT and GND; the first NMOS tube is connected between the first PMOS tube and GND; the second NMOS tube is connected between the first NMOS tube and the GND under the control of the delayed negation signal; the second PMOS tube is connected between the VBAT and the first reference node; the third PMOS tube is connected between the second PMOS tube and GND; the third NMOS tube is connected between the third PMOS tube and GND under the control of the inverted signal; the fourth NMOS tube is connected between the first reference node and the GND under the control of the start enabling signal; the fifth NMOS tube is connected between the second reference node and the second power supply voltage VSS 1; and the fourth PMOS tube is controllably connected to the VBAT and the output voltage end. The invention can quickly convert the input low-voltage signal into the high-voltage output signal.
Description
Technical Field
The invention relates to the field of circuits, in particular to a level conversion circuit.
Background
The level shift circuit has a wide application in the circuit field, and the conventional level shift circuit is shown in fig. 1 and comprises a first NMOS transistor NM0, a second NMOS transistor NM1, a first PMOS transistor PM1 and a second PMOS transistor PM2 which are connected in a cross-coupling manner, a third PMOS transistor PM3 and a fourth PMOS transistor PM4; the gate of the first NMOS transistor NM0 is connected with an input signal Vin, the gate of the second NMOS transistor NM1 is connected with an inverted signal Vinb of the input signal, and the source of the first NMOS transistor NM0 and the source of the second NMOS transistor NM1 are connected to a ground terminal GND; the grid electrode of the first PMOS pipe PM1 is connected with the drain electrode of the second PMOS pipe PM2 to serve as an output signal end vout, the source electrode of the first PMOS pipe PM1 and the source electrode of the second PMOS pipe PM2 are connected to a power supply voltage VBAT, the grid electrode of the second PMOS pipe PM2 is connected with the drain electrode of the first PMOS pipe PM1, a signal of a connection point is recorded as voutb, the grid electrode of the third PMOS pipe PM3 is connected with the grid electrode of the fourth PMOS pipe PM4, a signal of the connection point is recorded as vpb, the source electrode of the third PMOS pipe PM3 is connected with the drain electrode of the first PMOS pipe PM1, the drain electrode of the third PMOS pipe PM3 is connected with the drain electrode of the first NMOS pipe NM0, the source electrode of the fourth PMOS pipe PM4 is connected with the drain electrode of the second PMOS pipe PM2, and the drain electrode of the fourth PMOS pipe PM4 is connected with the drain electrode of the second NMOS pipe NM 1. When the low-voltage power supply and the high-voltage power supply exceed 3 times, especially when the low-voltage power supply and the high-voltage power supply are applied to a high-voltage circuit, the conventional level conversion circuit has the problem of low conversion speed, is difficult to apply to a high-speed high-voltage circuit, and is easy to generate an unstable state when being electrified and started, so that circuit errors are caused.
Disclosure of Invention
In view of the above problems, the present invention provides a level shift circuit.
A level shift circuit includes a first level shifter having a first input terminal,
an input voltage terminal receiving an input signal (Vin);
an output voltage terminal outputting the converted signal (Out);
a first PMOS transistor (PM 10) controllably connected between a first supply Voltage (VBAT) and Ground (GND) by a first reference node (X1);
a first NMOS transistor (NM 0) controllably connected between the first PMOS transistor (PM 10) and a ground terminal (GND) under control of the input signal (Vin);
a second NMOS transistor (NM 10) controllably connected between the first NMOS transistor (NM 0) and the ground terminal (GND) under the control of a delayed negation signal (Vind _ b) of the input signal (Vin);
a second PMOS transistor (PM 11), the gate of which (PM 11) is connected to the drain of the first PMOS transistor (PM 10) and is controllably connected between the first supply Voltage (VBAT) and the first reference node (X1);
a third PMOS transistor (PM 0) controllably connected between the second PMOS transistor (PM 11) and the ground terminal (GND);
a third NMOS transistor (NM 1) controllably connected between the third PMOS transistor (PM 0) and the ground terminal (GND) under the control of an inverted signal (Vinb) of the input signal (Vin);
a fourth NMOS transistor (NM 2) controllably connected between the first reference node (X1) and the ground terminal (GND) under the control of a start enable signal (startn);
a fifth NMOS transistor (NM 13) controllably connected between a second reference node (X2) and a second power voltage (VSS 1) under the control of the first reference node (X1);
a fourth PMOS transistor (PM 14) controllably connected to the first supply Voltage (VBAT) and the output voltage terminal under control of the second reference node (X2).
The level shift circuit further comprises a sixth NMOS (N-channel metal oxide semiconductor) tube (NM 11), wherein the grid electrode and the drain electrode of the sixth NMOS tube (NM 11) are connected with the first power Voltage (VBAT), and the source electrode of the sixth NMOS tube (NM 11) is connected with the drain electrode of the first PMOS tube (PM 10).
The level shift circuit further comprises a fifth PMOS tube (PM 12), wherein the grid electrode of the fifth PMOS tube (PM 12) is connected with the second reference node (X2), the source electrode of the fifth PMOS tube (PM 12) is connected with the first power Voltage (VBAT), and the drain electrode of the fifth PMOS tube (PM 12) is connected with the first reference node (X1).
The level shift circuit further comprises a sixth MOS transistor (PM 13), wherein the gate of the sixth MOS transistor (PM 13) is connected with the first reference node (X1), the source of the sixth MOS transistor (PM 13) is connected with the first power supply Voltage (VBAT), and the drain of the sixth MOS transistor (PM 13) is connected with the second reference node (X2).
The level shift circuit further comprises a first resistor connected between the first power Voltage (VBAT) and the first reference node (X1).
The level shift circuit of the present invention further includes:
a first diode D0, an anode of the first diode D0 being connected to the source of the first NMOS transistor NM0, and a cathode of the first diode D0 being connected to a third power voltage vdd5v;
and the anode of the second diode (D1) is connected with the source electrode of the fourth NMOS tube (NM 2), and a second resistor (R2) is also connected between the source electrode of the fourth NMOS tube (NM 2) and the grounding end (GND).
The level shift circuit of the invention also comprises a delay negation unit (delayn), which comprises,
a first inverter (inv 1), an input terminal of the first inverter (inv 1) being connected to the input signal (Vin), an output terminal of the first inverter (inv 1) outputting a first inverted signal (INB);
a second inverter (inv 2), an input terminal of the second inverter (inv 2) is connected to the input signal (Vin) through a third resistor (R3), and an output terminal of the second inverter (inv 2) outputs the delayed inversion signal (Vind _ b);
a seventh NMOS transistor (NM 3), wherein a gate of the seventh NMOS transistor (NM 3) is connected to the first inverted signal (INB), a source of the seventh NMOS transistor (NM 3) is connected to a ground terminal, and a drain of the seventh NMOS transistor (NM 3) is connected to an input terminal of the second inverter (inv 2);
and one end of the first capacitor (C) is connected with the input end of the second inverter (inv 2), and the other end of the first capacitor (C) is connected with the ground end (GND).
The level conversion circuit further comprises a third inverter (inv 0), wherein the input end of the third inverter (inv 0) is connected with the input signal (Vin), and the output end of the third inverter (inv 0) is connected with the grid electrode of the third NMOS tube (NM 1).
In the level shift circuit of the present invention, a gate of the third PMOS transistor (PM 0) is connected to a fourth power voltage (Vpb 1).
According to the level shift circuit, the third inverter (inv 0) comprises a seventh PMOS transistor (PM 15) and an eighth NMOS transistor (NM 14), a gate of the seventh PMOS transistor (PM 15) and a gate of the eighth NMOS transistor (NM 14) are connected to the input signal (Vin), a drain of the seventh PMOS transistor (PM 15) and a drain of the eighth NMOS transistor (NM 14) are connected to serve as an output end of the third inverter (inv 0), a source of the seventh PMOS transistor (PM 15) is connected to a fifth power Voltage (VDD), and a source of the eighth NMOS transistor (NM 14) is connected to the Ground (GND).
Has the advantages that: the invention can quickly convert the input low-voltage signal into the high-voltage output signal, and keeps low-level output in the process that no low-voltage power supply is input or the power supply is started, thereby ensuring that a power tube behind a driving chip is not damaged for the driving chip; the circuit of the invention is a logic circuit rather than a time sequence circuit, thereby greatly improving the interference resistance and preventing the circuit from outputting error signals due to the change of external conditions.
Drawings
FIG. 1 is a schematic diagram of a prior art level shift circuit;
FIG. 2 is a block diagram of a level shift circuit according to the present invention;
FIG. 3 is a signal waveform diagram illustrating the operation of the present invention;
FIG. 4 is a circuit diagram of the time delay negation unit of the present invention;
fig. 5 is a circuit configuration diagram of an inverter of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
Referring to fig. 2, a level shift circuit includes,
an input voltage terminal for receiving an input signal Vin;
an output voltage end for outputting the converted signal Out;
the first PMOS transistor PM10 controllably connected between a first power voltage VBAT and the ground GND under the action of a first reference node X1;
the first NMOS transistor NM0 is controllably connected between the first PMOS transistor PM10 and a ground end GND under the control of an input signal Vin;
the second NMOS tube NM10 is controllably connected between the first NMOS tube NM0 and a ground end GND under the control of a time delay negation signal Vin _ b;
a gate of the second PMOS transistor PM11 is connected to the drain of the first PMOS transistor PM10, and controllably connected between the first power voltage VBAT and the first reference node X1;
the third PMOS tube PM0 is controllably connected between the second PMOS tube PM11 and the ground end GND;
the third NMOS tube NM1 is controllably connected between the third PMOS tube PM0 and the ground end GND under the control of the inverted signal Vinb of the input signal Vin;
a fourth NMOS transistor NM2 controllably connected between the first reference node X1 and the ground GND under the control of a start enable signal startn;
a fifth NMOS transistor NM13 controllably connected between a second reference node X2 and a second power voltage VSS1 under the control of the first reference node X1;
the fourth PMOS transistor PM14 is controllably connected to the first power voltage VBAT and the output voltage terminal under the control of the second reference node X2.
The level shift circuit further includes a sixth NMOS transistor NM11, a gate and a drain of the sixth NMOS transistor NM11 are connected to the first power voltage VBAT, and a source of the sixth NMOS transistor NM11 is connected to the drain of the first PMOS transistor PM 10.
The level conversion circuit further comprises a fifth PMOS tube PM12, a grid electrode of the fifth PMOS tube PM12 is connected with the second reference node X2, a source electrode of the fifth PMOS tube PM12 is connected with the first power voltage VBAT, and a drain electrode of the fifth PMOS tube PM12 is connected with the first reference node X1.
The level shift circuit further comprises a sixth MOS transistor PM13, wherein the grid electrode of the sixth MOS transistor PM13 is connected with the first reference node X1, the source electrode of the sixth MOS transistor PM13 is connected with the first power voltage VBAT, and the drain electrode of the sixth MOS transistor PM13 is connected with the second reference node X2.
The level shift circuit further includes a first resistor R1 connected between the first power voltage VBAT and the first reference node X1.
In the level shift circuit of the present invention, the gate of the third PMOS transistor PM0 is connected to a fourth power voltage Vpb1.
When the initial state of the input signal Vin is 0, the delayed inverted signal Vind _ b is V1, the signal V1n _1V at the drain of the second NMOS transistor NM10 is 0, the signal V1n _ hv at the drain of the first NMOS transistor NM0 is equal to the first power supply voltage VBAT, the inverted signal Vinb of the input signal Vin is V1, the signal V1p _1V at the drain of the third NMOS transistor NM1 is 0, the signal V1p _ hv at the first reference node X1 is the second power supply voltage VSS1, the signal V2n _ hv at the second reference node X2 is the first power supply voltage VBAT, and the fourth transistor PM14 is turned off, that is, the level signal Out at the output voltage end becomes low.
With reference to fig. 3, at time t1, when the input signal Vin changes from 0 to V1, the delayed inversion signal Vind _ b remains unchanged, that is, still 1, the signal V1n _1V at the drain of the second NMOS transistor NM10 remains unchanged, that is, 0, the signal V1n _ hv at the drain of the first NMOS transistor NM0 changes from the first power voltage VBAT to V2, the inversion signal Vinb of the input signal Vin changes from V1 to 0, the signal V1p _ hv at the first reference node X1 changes from the second power voltage VSS1 to the first power voltage VBAT, the signal V2n _ hv at the second reference node X2 is the second power voltage VSS1, and the fourth PMOS transistor PM14 is turned on, that is, the signal Out at the output voltage end is the first power voltage VBAT;
when one end of time reaches t2, the input signal Vin keeps V1, the inverted signal Vinb of the input signal Vin keeps 0, the delayed inverted signal Vind _ b is changed from V1 to 0, the signal V1n _ hv at the drain of the first NMOS tube NM0 is changed from V2 to a first power supply voltage VBAT, the signal V1p _ hv at the first reference node X1 keeps VBAT, the signal V2n _ hv at the second reference node X2 keeps a second power supply voltage VSS1, the fourth PMOS tube PM14 keeps on, and the signal Out at the output voltage end keeps the first power supply voltage VBAT;
after time t3, the input signal Vin is changed from V1 to 0, the delayed inversion signal Vind _ b is kept to 0, the signal V1n _ hv at the drain of the first NMOS transistor NM0 is kept to the first power voltage VBAT, the inversion signal Vinb of the input signal Vin is changed from 0 to V1, the signal V1p _1V at the drain of the third NMOS transistor NM1 is quickly changed to 0 from the first power voltage VBAT, the signal V1p _ hv at the first reference node X1 is quickly changed to the second power voltage VSS1 from the first power voltage VBAT, the signal V2n _ hv at the second reference node X2 is changed to the first power voltage VBAT from the second power voltage VSS1, and the fourth PMOS transistor PM14 is turned off, that is, the signal Out at the output voltage end is turned low;
after the time t4, the input signal Vin maintains 0, the delayed inversion signal Vind _ b changes from 0 to V1, the signal V1n _ hv at the drain of the first NMOS transistor NM0 maintains the first power voltage VBAT, the inverted signal Vinb of the input signal Vin maintains V1, the signal V1p _1V at the drain of the third NMOS transistor NM1 maintains 0, the signal V1p _ hv at the first reference node X1 maintains the second power voltage VSS1, the signal V2n _ hv at the second reference node X2 maintains the first power voltage VBAT, and the fourth PMOS transistor PM14 is kept off, that is, the signal Out at the output voltage end is kept low.
Where V1 denotes a power supply of a low voltage circuit, a first power supply voltage VBAT denotes a power supply of a high voltage circuit, a second power supply voltage VSS1 denotes a value of the first power supply voltage VBAT minus V1, and V2 denotes a value smaller than the first power supply voltage VBAT but larger than the second power supply voltage VSS 1.
In the starting process of the level shift circuit, the first power supply voltage VBAT is changed from low to high, the starting enabling signal startn is also changed from low to high, the signal V1p _ hv at the first reference node X1 is pulled to the second power supply voltage VSS1, the signal V2n _ hv at the second reference node X2 is always the first power supply voltage VBAT, the fourth PMOS pipe PM14 is kept disconnected, and the signal Out at the output voltage end is 0.
The level shift circuit of the present invention further includes:
a first diode D0, an anode of the first diode D0 is connected to the source of the first NMOS transistor NM0, and a cathode of the first diode D0 is connected to a third power voltage vdd5v;
and the anode of the second diode D1 is connected with the source electrode of the fourth NMOS tube NM2, and a second resistor R2 is also connected between the source electrode of the fourth NMOS tube NM2 and the ground end GND.
The first diode D0 and the second diode D1 are used for protecting the source voltages of the first NMOS transistor NM0 and the fourth NMOS transistor NM2 from exceeding V1+0.7V, and preventing the first NMOS transistor NM0 and the fourth NMOS transistor NM2 from being broken down. The second resistor 2 acts as a current limiting preventing the signal V2n _ hv at the second reference node X2 from being pulled too low.
The level shift circuit of the present invention further includes a delay negation unit delayn, referring to fig. 4, including,
the input end of the first inverter inv1 is connected with the input signal Vin, and the output end of the first inverter inv1 outputs a first inversion signal INB;
an input end In _ sw of the second inverter inv2 is connected with the input signal Vin through a third resistor R3, and an output end of the second inverter inv2 outputs a delay negation signal (Vind _ b);
a seventh NMOS transistor NM3, a gate of the seventh NMOS transistor NM3 being connected to the first inverted signal INB, a source of the seventh NMOS transistor NM3 being connected to the ground, a drain of the seventh NMOS transistor NM3 being connected to an input terminal of the second inverter inv 2;
and one end of the first capacitor C is connected with the input end of the second inverter inv2, and the other end of the first capacitor C is connected with the ground terminal GND.
The level conversion circuit further comprises a third inverter inv0, wherein the input end of the third inverter inv0 is connected with the input signal Vin, and the output end of the third inverter inv0 is connected with the grid electrode of a third NMOS tube NM 1.
Referring to fig. 5, the third inverter inv0 includes a seventh PMOS transistor PM15 and an eighth NMOS transistor NM14, a gate of the PM15 and a gate of the eighth NMOS transistor NM14 of the seventh PMOS transistor are connected to the input signal Vin, a drain of the PM15 and a drain of the eighth NMOS transistor NM14 of the seventh PMOS transistor are connected to output the inverted signal Vinb as an output terminal of the third inverter inv0, a source of the PM15 of the seventh PMOS transistor is connected to a fifth power voltage VDD, and a source of the eighth NMOS transistor NM14 is connected to the ground terminal GND.
According to the invention, a second NMOS tube NM10, a fifth NMOS tube NM13 and a sixth NMOS tube NM11 adopt low-voltage NMOS tubes, a first NMOS tube NM0, a third NMOS tube NM1 and a fourth NMOS tube NM2 adopt high-voltage NMOS tubes, a first PMOS tube PM10, a second PMOS tube PM11, a fifth PMOS tube PM12 and a sixth PMOS tube PM13 adopt low-voltage PMOS tubes, and a third PMOS tube PM0 and a fourth PMOS tube PM14 adopt high-voltage PMOS tubes.
In the process that no low-voltage power supply is input or the power supply is started, the low-level output is kept, and for a driving chip, a power tube behind the driving chip is prevented from being damaged; the anti-interference degree is high, when the circuit is subjected to an Electrical fast pulse train anti-interference degree test (EFT), an Electro-static Discharge (ESD) or a voltage source VDD (VDD) has large fluctuation, the output cannot be changed high, the system is ensured not to be in a problem, a low-voltage signal can be quickly converted into high voltage, and when the low voltage is 5V, the high-voltage output converted into 30V only needs 500ps.
While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the foregoing invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (9)
1. A level shift circuit, comprising,
an input voltage terminal receiving an input signal (Vin);
an output voltage terminal outputting the converted signal (Out);
a first PMOS transistor (PM 10) controllably connected between a first power Voltage (VBAT) and Ground (GND) under the action of a first reference node (X1);
a first NMOS transistor (NM 0) controllably connected between the first PMOS transistor (PM 10) and a ground terminal (GND) under control of the input signal (Vin);
a second NMOS transistor (NM 10) controllably connected between the first NMOS transistor (NM 0) and the ground terminal (GND) under the control of a delayed negation signal (Vind _ b) of the input signal (Vin);
a second PMOS transistor (PM 11), the gate of which (PM 11) is connected to the drain of the first PMOS transistor (PM 10) and is controllably connected between the first supply Voltage (VBAT) and the first reference node (X1);
a third PMOS transistor (PM 0) controllably connected between the second PMOS transistor (PM 11) and the Ground (GND), a gate of the third PMOS transistor (PM 0) being connected to a fourth power voltage (Vpb 1);
a third NMOS transistor (NM 1) controllably connected between the third PMOS transistor (PM 0) and the ground terminal (GND) under the control of an inverted signal (Vinb) of the input signal (Vin);
a fourth NMOS transistor (NM 2) controllably connected between the first reference node (X1) and the ground terminal (GND) under the control of a start-up enable signal (startn);
a fifth NMOS transistor (NM 13) controllably connected between a second reference node (X2) and a second power voltage (VSS 1) under the control of the first reference node (X1);
a fourth PMOS transistor (PM 14) controllably connected to the first supply Voltage (VBAT) and the output voltage terminal under control of the second reference node (X2).
2. The level shift circuit according to claim 1, further comprising a sixth NMOS transistor (NM 11), wherein the gate and the drain of the sixth NMOS transistor (NM 11) are connected to the first power Voltage (VBAT), and the source of the sixth NMOS transistor (NM 11) is connected to the drain of the first PMOS transistor (PM 10).
3. The circuit of claim 1, further comprising a fifth PMOS transistor (PM 12), wherein a gate of the fifth PMOS transistor (PM 12) is connected to the second reference node (X2), a source of the fifth PMOS transistor (PM 12) is connected to the first power Voltage (VBAT), and a drain of the fifth PMOS transistor (PM 12) is connected to the first reference node (X1).
4. The circuit of claim 1, further comprising a sixth PMOS transistor (PM 13), a gate of the sixth PMOS transistor (PM 13) being connected to the first reference node (X1), a source of the sixth PMOS transistor (PM 13) being connected to the first power Voltage (VBAT), and a drain of the sixth PMOS transistor (PM 13) being connected to the second reference node (X2).
5. The circuit of claim 1, further comprising a first resistor coupled between the first supply Voltage (VBAT) and the first reference node (X1).
6. The level shift circuit of claim 1, further comprising:
a first diode D0, an anode of the first diode D0 being connected to a source of the first NMOS transistor (NM 0), and a cathode of the first diode D0 being connected to a third power voltage vdd5v;
the anode of the second diode (D1) is connected with the source electrode of the fourth NMOS tube (NM 2), and a second resistor (R2) is further connected between the source electrode of the fourth NMOS tube (NM 2) and the grounding terminal (GND).
7. The level shift circuit according to claim 1, further comprising a delay inverting unit (delayn) comprising,
a first inverter (inv 1), an input terminal of the first inverter (inv 1) being connected to the input signal (Vin), an output terminal of the first inverter (inv 1) outputting a first inverted signal (INB);
a second inverter (inv 2), an input terminal of the second inverter (inv 2) is connected to the input signal (Vin) through a third resistor (R3), and an output terminal of the second inverter (inv 2) outputs the delayed inversion signal (Vind _ b);
a seventh NMOS transistor (NM 3), a gate of the seventh NMOS transistor (NM 3) is connected to the first inverted signal (INB), a source of the seventh NMOS transistor (NM 3) is connected to a ground terminal, and a drain of the seventh NMOS transistor (NM 3) is connected to an input terminal of the second inverter (inv 2);
and one end of the first capacitor (C) is connected with the input end of the second inverter (inv 2), and the other end of the first capacitor (C) is connected with the ground end (GND).
8. The level shift circuit according to claim 1, further comprising a third inverter (inv 0), wherein an input terminal of the third inverter (inv 0) is connected to the input signal (Vin), and an output terminal of the third inverter (inv 0) is connected to the gate of the third NMOS transistor (NM 1).
9. The level shift circuit according to claim 8, wherein the third inverter (inv 0) comprises a seventh PMOS transistor (PM 15) and an eighth NMOS transistor (NM 14), the gate of the seventh PMOS transistor (PM 15) and the gate of the eighth NMOS transistor (NM 14) are connected to the input signal (Vin), the drain of the seventh PMOS transistor (PM 15) and the drain of the eighth NMOS transistor (NM 14) are connected as the output terminal of the third inverter (inv 0), the source of the seventh PMOS transistor (PM 15) is connected to a fifth power Voltage (VDD), and the source of the eighth NMOS transistor (NM 14) is connected to the ground terminal (GND).
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| CN108540124A (en) * | 2018-04-16 | 2018-09-14 | 电子科技大学 | A kind of level shifting circuit |
| CN111130533A (en) * | 2020-01-10 | 2020-05-08 | 电子科技大学 | High-speed high dv/dt inhibition ability's level shifter circuit |
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| US8692576B2 (en) * | 2006-09-18 | 2014-04-08 | Linear Technology Corporation | Circuit and methodology for high-speed, low-power level shifting |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108540124A (en) * | 2018-04-16 | 2018-09-14 | 电子科技大学 | A kind of level shifting circuit |
| CN111130533A (en) * | 2020-01-10 | 2020-05-08 | 电子科技大学 | High-speed high dv/dt inhibition ability's level shifter circuit |
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