CN114093822A

CN114093822A - Semiconductor packaging structure, preparation method of semiconductor packaging structure and preparation method of chip to be packaged

Info

Publication number: CN114093822A
Application number: CN202111310201.8A
Authority: CN
Inventors: 李明亮; 陈鹏; 莫平
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-11-03
Filing date: 2021-11-03
Publication date: 2022-02-25

Abstract

The application provides a semiconductor packaging structure and a preparation method thereof, and relates to a preparation method of a chip to be packaged for the semiconductor packaging structure. The semiconductor package structure includes: the semiconductor device includes a package substrate, a multi-layered chip stacking structure attached to the package substrate and including a plurality of chips stacked in sequence, and a molding compound layer formed on a surface of the package substrate and encapsulating the multi-layered chip stacking structure. The chip includes: the semiconductor substrate comprises a first surface and a second surface which are opposite, the circuit layer is formed on the first surface, and the reinforcing warping-reducing film covers the second surface. The semiconductor packaging structure and the chip structure thereof can effectively avoid the risk of chip damage or warpage and the problem of failure of a packaging device by changing the release direction of local mechanical stress in the chip and increasing the mechanical strength of the chip.

Description

Semiconductor packaging structure, preparation method of semiconductor packaging structure and preparation method of chip to be packaged

Technical Field

The present disclosure relates to the field of semiconductor technologies, and more particularly, to a semiconductor package structure and a method for manufacturing the same, and a method for manufacturing a chip to be packaged for the semiconductor package structure.

Background

Semiconductor package devices are usually processed through two processes, i.e., chip manufacturing and chip packaging, so that the characteristics of the chip itself and the quality of the packaging technology directly determine the final performance of the semiconductor package device product.

With the continuous development of semiconductor technology, the overall thickness of a chip is becoming thinner, and a metal circuit layer therein is becoming thicker, so that in a packaging structure of an ultra-thin chip such as a three-dimensional memory, the mechanical strength of the chip becomes worse and worse, and at the same time, the chip may warp due to thermal stress generated by thermal matching in the packaging process, so that the problems of chip cracking, breakage or warpage, semiconductor packaging device failure and the like of the conventional semiconductor packaging device and the intermediate thereof tend to occur due to the above reasons.

Disclosure of Invention

The present application provides a semiconductor package structure, a semiconductor package structure manufacturing method, and a manufacturing method of a chip to be packaged for the semiconductor package structure, which can at least partially solve the above-mentioned problems in the related art.

One aspect of the present application provides a semiconductor package structure, including: a package substrate; a multilayer chip stacking structure attached to the package substrate and including a plurality of chips stacked in sequence; and a molding compound layer formed on a surface of the package substrate and encapsulating the multi-layered chip stacking structure, wherein the chip includes: a semiconductor substrate comprising opposing first and second surfaces; a circuit layer formed on the first surface; and a reinforced lift-off film covering the second surface.

In one embodiment of the present application, the semiconductor substrate further includes a substrate side surface connecting the first surface and the second surface; and the reinforced warping reduction film also covers the side surface of the substrate and the side surface of the circuit layer.

In one embodiment of the present application, the thickness of the reinforced lift-off film is 1% to 17% of the common thickness of the semiconductor substrate and the circuit layer.

In one embodiment of the present application, a thickness of the semiconductor substrate and the circuit layer is 30 to 50 micrometers, and a thickness of the reinforced warpage reducing film is 0.5 to 5 micrometers.

In one embodiment of the present application, the thickness of the reinforced lift-off film becomes larger as the thickness of the circuit layer becomes larger, without changing the common thickness.

In one embodiment of the present application, the reinforced lift-off film has a single-layer structure or a composite structure.

In one embodiment of the present application, the reinforced lift-off film is at least one of a nitride layer, a silicide layer, and an oxide layer.

In one embodiment of the present application, the reinforced lift-off film is prepared by a chemical vapor deposition process.

In one embodiment of the present application, the chip includes a three-dimensional nonvolatile memory, wherein the three-dimensional nonvolatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

Another aspect of the present application provides a method for manufacturing a semiconductor package structure, including: attaching a multi-layered chip stacking structure to a package substrate, wherein the multi-layered chip stacking structure includes a plurality of chips stacked in sequence; and forming a molding compound layer for encapsulating the multi-layered chip build-up structure on a surface of the package substrate, wherein the chip includes: a semiconductor substrate comprising opposing first and second surfaces; a circuit layer formed on the first surface; and a reinforced lift-off film covering the second surface.

In one embodiment of the present application, the thickness of the reinforced lift-off film is set to become larger as the thickness of the circuit layer becomes larger, without changing the common thickness.

In one embodiment of the present application, the reinforced lift-off film is provided as a single layer structure or a composite structure.

In one embodiment of the present application, the reinforced warpage reducing film is prepared by a chemical vapor deposition process.

In another aspect, the present application provides a method for manufacturing a chip to be packaged for a semiconductor package structure, including: half-cutting the wafer from the front side of the wafer, which is provided with the circuit layer; a temperature-resistant shaping layer is arranged on the front surface; thinning the wafer from the back side opposite to the front side so as to separate the wafer into a plurality of independent sub-wafers fixed on the temperature-resistant shaping layer; forming a reinforced warping reduction film on the surface of the sub-wafer, which is not in contact with the temperature-resistant shaping layer; adhering a scribing film on the partial surface of the reinforced warping reduction film, and removing the temperature-resistant shaping layer; and carrying out scribing treatment to obtain a plurality of independent chips to be packaged, wherein the chips to be packaged comprise the sub-wafer and the reinforced warping reducing film formed on part of the surface of the sub-wafer.

In an embodiment of this application, wherein the sub-wafer includes relative upper surface and lower surface, and connects the upper surface with the lower surface the side of sub-wafer, the upper surface of sub-wafer is fixed on the temperature resistant design layer sub-wafer, not with the temperature resistant design layer contact form on the surface that the reinforcement falls the perk membrane and includes: and forming the reinforced warping reduction film on the lower surface of the sub-wafer and the side surface of the sub-wafer.

In one embodiment of the present application, forming a reinforced lift-off film on a surface of the sub-wafer not in contact with the temperature-resistant sizing layer includes: and forming the reinforced warping reduction film on the surface of the sub-wafer, which is not in contact with the temperature-resistant sizing layer, by adopting a chemical vapor deposition process.

In one embodiment of the present application, the temperature-resistant shaping layer is a quartz glass layer.

In an embodiment of the present application, the front surface is provided with a temperature-resistant sizing layer including: and arranging the temperature-resistant shaping layer on the front surface by adopting an adhesive or laminating process.

In one embodiment of the present application, the chip to be packaged includes a three-dimensional nonvolatile memory, wherein the three-dimensional nonvolatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

According to the semiconductor package structure, the semiconductor package structure manufacturing method and the semiconductor package structure chip to be packaged manufacturing method provided by at least one embodiment of the present application, the reinforcement and warpage-reducing film covering the bottom surface of the semiconductor substrate (or covering the bottom surface, the side surface of the semiconductor substrate and the side surface of the circuit layer) is formed in the structure of the chip to be packaged, so that the release direction of local mechanical stress in the chip can be changed, the mechanical strength of the chip can be increased, and the risks of cracking, damage or warpage of the chip and the problems of failure of the semiconductor package device can be effectively avoided.

In addition, according to at least one embodiment of the present application, before forming the reinforced warpage reducing film, a film layer with temperature-resistant shaping characteristics may be formed on a front surface of a half-cut processed wafer (the wafer is used for cutting to obtain a chip to be packaged, which includes a semiconductor substrate and a circuit layer), and the film layer may enable the reinforced warpage reducing film to be formed later to have a thinner thickness while fixing and protecting the wafer, and is more suitable for a packaging structure of an ultra-thin chip, such as a three-dimensional memory.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

FIG. 1A is a schematic cross-sectional view of a semiconductor package structure according to one embodiment of the present application;

FIG. 1B is an enlarged schematic view of a partial cross-sectional structure at A in a semiconductor package structure according to one embodiment of the present application;

fig. 2 is a photograph showing the occurrence of cracks and breakage in a chip formed by a conventional method for manufacturing a semiconductor package structure;

fig. 3 is a schematic cross-sectional view showing warpage and breakage in a multi-layered chip stacking structure formed by a conventional method for manufacturing a semiconductor package structure;

fig. 4 is a schematic cross-sectional view showing warpage and breakage in a multi-layered chip stacking structure formed by a conventional method for manufacturing a semiconductor package structure;

FIG. 5 is a schematic diagram of the distribution of mechanical stress on a die in a conventional semiconductor package structure;

FIG. 6 is a schematic diagram of a distribution of die mechanical stresses in a semiconductor package structure, according to an embodiment of the present application;

FIG. 7 is a flow chart of a method of fabricating a semiconductor package structure according to one embodiment of the present application;

FIG. 8 is a flow chart of a method of fabricating a chip to be packaged for use in a semiconductor package structure according to one embodiment of the present application; and

fig. 9 to 15 are process diagrams of a method for manufacturing a chip to be packaged for a semiconductor package structure according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in this specification the expressions first, second, third etc. are only used to distinguish one feature from another, and do not indicate any limitation of features, in particular any order of precedence. Thus, a first surface discussed in this application may also be referred to as a second surface, and vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Further, in this application, when "connected" or "coupled" is used, it may mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or can be inferred from the context.

Fig. 1A is a schematic cross-sectional view of a semiconductor package structure 1000 according to an embodiment of the present application. Fig. 1B is an enlarged schematic view of a partial cross-sectional structure at a in a semiconductor package structure 1000 according to an embodiment of the present application.

As shown in fig. 1A and 1B, the semiconductor package structure 1000 provided by the present application may include: a package substrate 100, a multi-layer chip stacking structure 200, and a molding compound layer 300. The multi-layered chip stacking structure 200 is attached to the package substrate 100, and may include a plurality of chips 201 stacked in sequence. The molding compound layer 300 is formed on the surface 110 of the package substrate 100 and encapsulates the multi-layered chip build-up structure 200. The chip 201 may include a semiconductor substrate 210, a circuit layer 220, and a reinforced lift-off film 230. The semiconductor substrate 210 includes a first surface 11 and a second surface 12 opposite to each other. The circuit layer 220 is formed on the first surface 11 of the semiconductor substrate 210 and has a circuit layer side 14. The reinforced lift-off film 230 covers the second surface 12 of the semiconductor substrate 210.

Further, the semiconductor substrate 210 may optionally further include a substrate side 13 connecting the first surface 11 and the second surface 12. The circuit layer 220 also has a circuit layer side 14. The reinforced lift-off film 230 covers the second surface 12 of the semiconductor substrate 210, and further covers the substrate side 13 and the circuit layer side 14.

Specifically, in one embodiment of the present application, the chip 201 in the multi-layered chip stacking structure 200 may include a device structure and an interconnection structure of the device structure. The device structure may include at least one of an active device and a passive device. The active device may for example comprise a MOS device, a memory device or other semiconductor device, wherein the memory device may for example comprise a non-volatile memory or a random access memory or the like. The non-volatile memory may include, for example, a floating gate field effect transistor such as a NOR type memory, a NAND type memory, or the like, or a ferroelectric memory, a phase change memory, or the like. Passive devices may for example comprise resistors, capacitors or inductors, etc. Further, the device structure may be a planar device or a stereoscopic device, wherein the stereoscopic device may be, for example, a FIN-FET (FIN field effect transistor), a three-dimensional memory, or the like.

The specific parameter characteristics of the package substrate 100, such as material, thickness or size, can be selected according to actual requirements, for example, according to the specific type of the multi-layer chip stacking structure 200 to be carried. The multi-layered chip stacking structure 200 may be adhered to the surface 110 of the package substrate 100 by an adhesive layer, and the adhesive layer is only located in a projection area of the multi-layered chip stacking structure 200 on the package substrate 100.

Alternatively, the chips 201 in the multi-layered chip stacking structure 200 may be stacked on the package substrate 100 in a zigzag pattern, thereby providing space for bonding wires of the chips 201 to be formed later; alternatively, the chips 201 may be vertically stacked on each other and/or laterally spaced apart to provide space for subsequently formed bonding wires, and the present application is not limited to the manner in which the chips 201 are stacked in the multi-layer chip stacking structure 200.

Furthermore, although the plurality of chips 201 are shown as having the same chip size in fig. 1A, in some embodiments, the plurality of chips 201 may have different chip sizes.

The molding compound layer 300 may be formed of any suitable material, such as a silicon oxide filler or a resin, etc. Alternatively, the molding compound layer 300 may include an Epoxy Molding Compound (EMC). Typically, the molding compound layer 300 and the chip 201 have different thermal expansion coefficients and thermal conductivities.

Fig. 2 is a photograph showing the occurrence of cracks and breakage in a chip formed by a conventional method for manufacturing a semiconductor package structure. Fig. 3 is a schematic cross-sectional view showing warpage and breakage in a multi-layered chip stacking structure formed by a conventional method for manufacturing a semiconductor package structure. Fig. 4 is a schematic cross-sectional view showing warpage and breakage in a multi-layered chip stacking structure formed by a conventional method for manufacturing a semiconductor package structure.

Semiconductor package devices are usually processed through two processes, i.e., chip manufacturing and chip packaging, so that the characteristics of the chip itself and the quality of the packaging technology directly determine the final performance of the semiconductor device product. Conventional semiconductor packaging techniques may generally include: carrying out half-cutting treatment on the wafer; sticking a thinning protective film on the front surface of the wafer; thinning the back of the wafer to separate the wafer into a plurality of independent sub-wafers (to-be-packaged chips) fixed on the thinning protective film; pasting a scribing film on the back surface of the wafer, and removing the thinning protective film; picking up the sub-wafer and forming a multilayer chip stacking structure; carrying out lead bonding on the chips in the multilayer chip stacking structure; and forming a molding compound layer for encapsulating the multilayer chip build-up structure, and the like.

However, as shown in fig. 2 to 4, with the continuous development of semiconductor technology, the overall thickness of a chip is becoming thinner, and a metal circuit layer therein is becoming thicker, so that in a packaging structure of an ultra-thin chip such as a three-dimensional memory, the mechanical strength of the chip becomes worse, and at the same time, the chip may be warped due to thermal stress generated by thermal matching during packaging, and thus, the conventional semiconductor packaging device and its intermediate body tend to have failure problems such as cracking, breaking or breakage due to the above reasons.

The left and right images of fig. 2 are photographs of cracks and damages in the chip formed after the thinning process of the back surface of the wafer in the conventional semiconductor packaging process. The surface of the portion encircled by the oval coil in the left figure is cracked, the crack may have already extended to the inside of the chip, and in a subsequent step, such as a wire bonding step, a case of chip fracture failure may occur. The surface of the portion encircled by the elliptical coil in the right drawing is broken, and the breakage can directly cause the failure of the semiconductor packaging device.

As shown in fig. 3, in a conventional semiconductor packaging process, it is necessary to electrically connect (wire bonding) the chips in the multi-chip stacking structure with an external package frame to ensure smooth transmission of electrical signals. Specifically, the chip 30 in the multi-layer chip stacking structure 20 and the package frame may be soldered by using the cleaver 10 and the bonding wires, so that the chip 30 and the package frame are electrically conducted, wherein the heat generated in the wire bonding process tends to further aggravate the warpage of the chip in the ultra-thin chip package structure, and thus the semiconductor package device and the intermediate thereof may have failure problems such as cracks, fractures or damages.

As shown in fig. 4, in a conventional semiconductor packaging process, a molding compound layer 40 for encapsulating the multi-layered chip build-up structure 20 may be formed on a surface of a package substrate 50. As the number of metal layers included in the chip 30 in the multi-layer chip stacking structure 20 is increased, the circuit density is increased, the mechanical strength of the chip 30 is deteriorated, and warpage (e.g., a portion circled by a polygon in the figure) of the chip 30 may occur due to thermal stress generated by thermal matching during the packaging process. In addition, the molding compound layer 40 such as a molding resin body becomes thinner and thinner, and the number of the multilayer chip stacking structures 20 encapsulated therein is increased, so that the semiconductor package device is liable to fail due to breakage or breakage.

The application provides a semiconductor package structure, through the reinforcement that forms the bottom surface that covers the semiconductor substrate in waiting to encapsulate the structure of chip and fall the perk membrane, can change local mechanical stress's among the chip release direction, increase the mechanical strength of chip, and then effectively avoid appearing the problem that the risk of chip crackle, damage or warpage and semiconductor package device became invalid in the packaging process.

In addition, in order to enhance the above advantageous effects, a reinforcing lift film may be further coated on the side surface of the semiconductor substrate and the side surface of the circuit layer.

Specifically, the technical features, the preparation steps, and the effects of the reinforced warpage reducing film 230 will be described in detail below by taking the reinforced warpage reducing film 230 as an example covering the bottom surface 12 and the side surface 13 of the semiconductor substrate 210 and the side surface 14 of the circuit layer 220, however, it should be understood by those skilled in the art that the present application is not limited to the constituent materials, structures, formation processes, and embodiments of the reinforced warpage reducing film without departing from the teachings of the present application, and the reinforced warpage reducing film in the present application is within the scope of the present application as long as the same technical problems as the reinforced warpage reducing film in the present embodiment can be solved and the same technical effects can be achieved.

Referring again to fig. 1B, in one embodiment of the present application, the thickness D1 of the reinforced turn-down film 230 is 1% to 17% of the common thickness D2 of the semiconductor substrate 210 and the circuit layer 220. Alternatively, in the case where the common thickness D2 of the semiconductor substrate 210 and the circuit layer 220 is 30 micrometers to 50 micrometers, the thickness D1 of the reinforced lift-off film 230 may be 0.5 micrometers to 5 micrometers. In other words, the thickness of the reinforced lift-off film 230 is relatively thin compared to the overall thickness of the chip 201, which is more suitable for use in the packaging structure of ultra-thin chips such as three-dimensional memories.

In addition, in one embodiment of the present application, in a case where the common thickness D2 of the semiconductor substrate 210 and the circuit layer 220 is not changed, the thickness D1 of the reinforced turn-down film 230 becomes larger as the thickness of the circuit layer 220 becomes larger. For example, in the case that the common thickness D2 of the semiconductor substrate 210 and the circuit layer 220 is 40 micrometers, when the thickness of the circuit layer 220 is only 5 micrometers, the thickness D1 of the reinforced lift-off film 230 may be selected to be 0.2 micrometers to 1 micrometer; when the thickness of the circuit layer 220 is 20 micrometers, the thickness D1 of the reinforced lift-off film 230 may be selected to be 3 micrometers to 5 micrometers.

Since the circuit layer 220 generally includes a plurality of metal layers having higher thermal expansion coefficient and thermal conductivity relative to the semiconductor substrate 210, the increase in the thickness of the circuit layer 220 may cause the chip 201 to warp due to uneven thermal stress generated by thermal matching during the packaging process. Therefore, the reinforced warpage reducing film 230 wrapping the semiconductor substrate 210 and the circuit layer 220 can be increased in thickness as appropriate under the condition that the thickness of the circuit layer 220 is increased, so as to improve the effect of changing the releasing direction of the local mechanical stress in the chip 201 and increasing the mechanical strength of the chip.

In addition, in one embodiment of the present application, the reinforced lift-off film 230 may have a single layer structure or a composite structure. Specifically, the reinforced lift-off film 230 may be at least one of a nitride layer, a silicide layer, and an oxide layer. In addition, the preparation material and structure of the reinforced warpage reducing film 230 may be determined according to the thickness of the circuit layer 220 in the chip 201, the device type of the chip 201, the number of layers of the multilayer chip stacking structure 20, and the specific parameters involved in the packaging process, which are not limited in this application. For example, the material for preparing the reinforced lift-off film 230 may be silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide SiOC, silicon nitride SixNyHz containing a certain hydrogen atom, or the like.

Alternatively, in one embodiment of the present application, the reinforced lift-off film 230 may be prepared by a Chemical Vapor Deposition (CVD) process. The reinforced lift-off film 230 formed by the chemical vapor deposition process may have a thinner film thickness and a denser film structure, is beneficial to changing the release direction of local mechanical stress in the chip, increases the mechanical strength of the chip, and is suitable for the packaging structure of an ultra-thin chip such as a three-dimensional memory.

Fig. 5 is a schematic diagram of the distribution of die mechanical stress in a conventional semiconductor package structure 60. Fig. 6 is a schematic diagram of a distribution of die mechanical stresses in a semiconductor package structure 70, according to an embodiment of the present application.

As shown in fig. 5, a conventional semiconductor package structure 60 may include a package substrate and a structure in which a plurality of chips are stacked formed thereon, wherein each chip may include a semiconductor base 61 and a circuit layer 62 on the semiconductor base 61. When warpage or cracks occur in the conventional semiconductor package structure 60, the chips inside the conventional semiconductor package structure may have a mechanical stress of bending upward as indicated by arrows in the drawing, and in addition, the chips may have a mechanical stress of bending downward in the case where the semiconductor substrate 61 and the circuit layer 62 are different in material type or structure, for example. The mechanical stress of the downward bending or the upward bending can not keep the chip in a flat state, so that the semiconductor packaging device is easy to have failure problems such as fracture or breakage.

As shown in fig. 6, the semiconductor package structure 70 provided by the present application may include a package substrate and a multi-layer chip stacking structure formed thereon, wherein the multi-layer chip stacking structure includes a plurality of chips stacked in sequence, and each chip may include a semiconductor substrate 71, a circuit layer 72 formed on the semiconductor substrate 71, and a reinforcing and tilting film 73 in a semi-wrapping state. The reinforced lift-off film 73 may include two portions, wherein a first portion 73-1 covers the bottom surface of the semiconductor substrate 71, and a second portion 73-2 covers the side surface of the semiconductor substrate 71 and the side surface of the circuit layer 72. Therefore, after the semiconductor package structure 70 has a warp or a crack, the semiconductor substrate 71 and the circuit layer 72 can be prevented from being deformed due to the fixing effect of the second portion 73-2 in the reinforcing and de-warping film 73, and the releasing direction of the internal mechanical stress of the chip can be changed under the combined action of the first portion 73-1 and the second portion 73-2, so that the downward bending or upward bending mechanical stress can be decomposed into the mechanical stress perpendicular to the semiconductor substrate 71 and the mechanical stress parallel to the semiconductor substrate 71, and the risk of chip breakage or warp and the problem of failure of the packaged device can be effectively avoided.

Fig. 7 is a flow chart of a method 2000 of fabricating a semiconductor package structure according to one embodiment of the present application.

As shown in fig. 7, a method 2000 for fabricating a semiconductor package structure may include:

and S11, attaching a multilayer chip stacking structure to the packaging substrate, wherein the multilayer chip stacking structure comprises a plurality of chips stacked in sequence, the chips comprise a semiconductor substrate, a circuit layer and a reinforcing and warping film, the semiconductor substrate comprises a first surface and a second surface which are opposite, the circuit layer is formed on the first surface, and the reinforcing and warping film covers the second surface.

S12, forming a molding compound layer for encapsulating the multi-layered chip stacking structure on the surface of the package substrate.

Specific processes of the steps of the method 2000 for manufacturing the semiconductor package structure are illustrated below.

Step S11

Specifically, in one embodiment of the present application, specific parameter characteristics of the package substrate, such as material, thickness or size, may be selected according to actual needs; alternatively, the selection may be made according to the particular type of multilayer chip stacking structure to be carried.

The package substrate may have a conductive trace formed therein, and one side of the package substrate may have an electrical connector (e.g., a solder ball) electrically connected to the conductive trace. The multi-layer chip stacking structure can be adhered to the other side of the packaging substrate through the bonding layer, and the bonding layer is only positioned in a projection area of the multi-layer chip stacking structure on the packaging substrate.

In some embodiments, the multi-layer chip stacking structure may include a plurality of chips stacked in sequence, and the plurality of chips are stacked in a shingled manner in sequence on the package substrate. In addition, as an option, the plurality of chips may be stacked one on another.

In addition, in some embodiments, the multi-layered chip stacking structure may utilize, for example, a wire bonding (wire bonding) process to electrically connect the bonding pads in each chip to the conductive traces in the package substrate by wire bonding, so as to ensure smooth electrical signal transmission.

The chip can include a semiconductor substrate, a circuit layer and a reinforced lift-off film. The semiconductor substrate includes opposing first and second surfaces and a substrate side connecting the first and second surfaces. The circuit layer is formed on the first surface of the semiconductor substrate and has a circuit layer side surface.

In one embodiment of the present application, a chip may include a three-dimensional nonvolatile memory, wherein the three-dimensional nonvolatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

Alternatively, the reinforced lift-off film may cover the second surface of the semiconductor substrate. Therefore, after the semiconductor packaging structure has warpage or cracks, the semiconductor substrate can be prevented from deforming due to the fixing effect of the reinforcing and warping film, the releasing direction of the internal mechanical stress of the chip is changed on the basis, and the risks of chip damage or warpage and the problems of failure of a semiconductor packaging device are effectively avoided.

Alternatively, the reinforcement lift-off film may cover the second surface and the substrate side surface of the semiconductor substrate, and cover the circuit layer side surface of the circuit layer. In other words, the reinforced lift-off film in this option may include two portions, wherein the first portion covers the bottom surface of the semiconductor substrate, and the second portion covers the side surface of the semiconductor substrate and the side surface of the circuit layer.

Therefore, after the semiconductor packaging structure has warpage or cracks, the semiconductor substrate and the circuit layer can be prevented from deforming due to the fixing effect of the second part in the reinforcing and warping film, the releasing direction of the internal mechanical stress of the chip can be changed under the action of the resultant force of the first part and the second part, and the downward bending mechanical stress or the upward bending mechanical stress is decomposed into the mechanical stress vertical to the semiconductor substrate and the mechanical stress parallel to the semiconductor substrate, so that the risks of chip breakage or warpage and the problems of failure of a semiconductor packaging device can be effectively avoided.

In one embodiment of the present application, the thickness of the reinforced lift-off film is 1% to 17% of the common thickness of the semiconductor substrate and the circuit layer. Alternatively, in the case where the semiconductor substrate and the circuit layer have a common thickness of 30 to 50 micrometers, the thickness of the reinforced warpage reducing film may be 0.5 to 5 micrometers. In other words, the thickness of the reinforced lift-off film is relatively thin compared to the overall thickness of the chip, which is more useful in the packaging structure of ultra-thin chips such as three-dimensional memories.

In addition, in one embodiment of the present application, in a case where the common thickness of the semiconductor substrate and the circuit layer is not changed, the thickness of the reinforcing lift-off film may become larger as the thickness of the circuit layer becomes larger. For example, in the case where the thickness of the semiconductor substrate and the circuit layer is micron, when the thickness of the circuit layer is only 5 micron, the thickness of the reinforced lift-off film may be selected to be 0.2 micron to 1 micron; when the thickness of the circuit layer is 20 micrometers, the thickness of the reinforced lift-off film can be selected to be 3 micrometers to 5 micrometers.

Since the circuit layer usually includes a plurality of metal layers, and the metal layers have higher thermal expansion coefficient and thermal conductivity relative to the semiconductor substrate, the increase of the thickness of the circuit layer often causes the chip to warp due to uneven thermal stress generated by thermal matching during the packaging process. Therefore, the reinforcing and warping-reducing film wrapping the semiconductor substrate and the circuit layer can be properly increased in thickness under the condition that the thickness of the circuit layer is increased, so that the effects of changing the release direction of local mechanical stress in the chip and increasing the mechanical strength of the chip are improved.

In addition, in one embodiment of the present application, the reinforced lift-off film may be a single layer structure or a composite structure. Specifically, the reinforced lift-off film may be at least one of a nitride layer, a silicide layer, and an oxide layer, or any combination thereof. In addition, the preparation material and structure of the reinforced warpage reducing film can be determined according to the thickness of a circuit layer in a chip, the device type of the chip, the number of layers of a multilayer chip stacking structure, specific parameters involved in a packaging process and the like, which is not limited in the present application. For example, the material for preparing the reinforced lift-off film may be silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide SiOC, silicon nitride SixNyHz containing a certain hydrogen atom, or the like, as an alternative.

Alternatively, in one embodiment of the present application, a Chemical Vapor Deposition (CVD) process may be used to prepare the reinforced lift-off film. The reinforced warping-reducing film formed by the chemical vapor deposition process can have a thinner film thickness and a more compact film structure, and is more favorable for changing the release direction of local mechanical stress in the chip and increasing the mechanical strength of the chip.

Step S12

In particular, in one embodiment of the present application, the molding compound layer may be formed of any suitable material, such as a polymeric material having no conductive properties. Alternatively, the molding compound layer may be prepared using a silicon oxide filler or a resin, or the like. Alternatively, the molding compound layer may include an Epoxy Molding Compound (EMC). Typically, the molding compound layer and the chip have different coefficients of thermal expansion and thermal conductivity.

In one embodiment of the present application, a molding compound may be injected on a surface of the package substrate by using, for example, an injection molding process, and the multi-layered chip stack structure is encapsulated, and then the molding compound layer is formed by curing the molding compound by using a curing process.

Since the contents referred to above in describing the semiconductor package structure may be fully or partially applicable to the semiconductor package structure manufacturing method described herein, the contents related or similar thereto will not be described in detail.

According to the semiconductor packaging structure preparation method provided by at least one embodiment of the application, the reinforcing and warping reducing film covering the bottom surface of the semiconductor substrate (or covering the bottom surface, the side surface of the semiconductor substrate and the side surface covering the circuit layer) is formed in the structure of the chip to be packaged, so that the release direction of local mechanical stress in the chip can be changed, the mechanical strength of the chip is increased, and the risks of cracking, damage or warping of the chip and the problems of failure of a semiconductor packaging device can be effectively avoided.

Fig. 8 is a flow chart of a method 3000 of fabricating a chip to be packaged for a semiconductor package structure according to one embodiment of the present application.

As shown in fig. 8, a method 3000 for preparing a chip to be packaged for a semiconductor package structure may include:

s21, the wafer is half-cut from the front surface of the wafer on which the circuit layer is provided.

And S22, arranging a temperature-resistant shaping layer on the front surface of the wafer.

And S23, thinning the wafer from the back side of the wafer opposite to the front side so as to separate the wafer into a plurality of independent sub-wafers fixed on the temperature-resistant sizing layer.

And S24, forming a reinforced warping reduction film on the surface of the sub-wafer, which is not in contact with the temperature-resistant shaping layer.

And S25, adhering a scribing film on the partial surface of the reinforced warping reduction film, and removing the temperature-resistant shaping layer.

And S26, performing scribing treatment to obtain a plurality of independent chips to be packaged, wherein the chips to be packaged comprise the sub-wafer and the reinforced lifting film formed on part of the surface of the sub-wafer.

Specific processes of the steps of the above-described method 3000 for manufacturing a chip to be packaged for a semiconductor package structure will be illustrated with reference to fig. 9 to 15.

Step S21

Fig. 9 is a schematic top view of a front side 821 of a wafer 82 with circuit layers formed thereon, in accordance with one embodiment of the present application.

Specifically, as shown in fig. 9, in one embodiment of the present application, a dicing apparatus 81 may be used to separate a wafer 82 on which a circuit layer has been formed. Alternatively, wafer 82 may be half-cut from its front side 821 on which the circuit layers are disposed, in other words, wafer 82 is not scribed through and a portion of the thickness of wafer 82 remains. Alternatively, the cutting device 81 may use a diamond blade for scribing, or may use a laser for scribing.

Step S22

Fig. 10 is a schematic top view of a temperature-resistant sizing layer 83 disposed on a front side 821 of a diced wafer 82, in accordance with one embodiment of the present application.

Specifically, as shown in fig. 10, in one embodiment of the present application, a temperature-resistant sizing layer 83 may be provided on a front side 821 of the wafer 82 using, for example, an adhesive or lamination process. The temperature-resistant shaping layer 83 disposed on the front surface 821 of the wafer 82 has the characteristics of temperature resistance, shaping and easy removal, so that the strengthening and warping-reducing film which is relatively thin and can semi-wrap the sub-wafer can be conveniently formed in the process of forming the strengthening and warping-reducing film on the surface of the subsequent sub-wafer (formed by cutting the wafer 82) which is not in contact with the temperature-resistant shaping layer 83. Alternatively, the temperature-resistant shaping layer 83 may be a quartz glass layer, however, it should be understood by those skilled in the art that the specific structure and material of the temperature-resistant shaping layer 83 are not limited in the present application, and the characteristic parameters of the specific structure and material may be set according to the related parameters in the process of forming the reinforced lift-off film.

According to the preparation method of the chip to be packaged for the semiconductor packaging structure, before the reinforcing and warping reducing film is formed, the film layer with the temperature-resistant shaping characteristic is formed on the front surface of the wafer (including the semiconductor substrate and the circuit layer) after half-cutting treatment, and the reinforcing and warping reducing film can be thin in thickness while fixing and protecting the wafer, and is more suitable for the packaging structure of ultrathin chips such as a three-dimensional memory.

Step S23

Fig. 11 is a schematic top view of a thinned wafer 82 from a back side 822 of wafer 82, according to one embodiment of the present application. Fig. 12 is a cross-sectional view of a plurality of sub-wafers 85 formed after thinning a processed wafer 82, according to one embodiment of the present disclosure.

Specifically, as shown in fig. 11 and 12, in one embodiment of the present application, the handle wafer 82 is thinned from a back side 822 of the wafer 82 opposite the front side 821 to separate the wafer 82 into a plurality of sub-wafers 85 that are individually and fixedly secured to the temperature-resistant shaping layer 83.

In one embodiment of the present application, the thinning process may include, for example: the back surface 822 of the wafer 82 is thinned by the thinning processing equipment 84 by using processes such as chemical mechanical polishing, acid etching or polishing, and the thinned back surface is formed. Alternatively, the thinning process may also include, for example: the wafer 82 is thinned from its back side 822 using at least two thinning processes and a thinned back side is formed. For example, a first thinning, such as by a chemical mechanical polishing process, may be performed with a faster thinning rate, and a second thinning, such as by acid etching, may be performed with a slower rate, but may result in a thinner surface with better planarity.

The wafer 82 which is not cut through and remains with a partial thickness (after half-cut processing) can be completely separated into a plurality of sub-wafers 85 by the thinning processing, and the sub-wafers 85 can reach a predetermined packaging thickness. Each of the sub-wafers 85 mounted on the temperature-resistant primer layer 83 may include a semiconductor substrate 851 and a circuit layer 852 formed thereon.

Referring again to fig. 12, as an option, the upper surfaces 01 of the plurality of sub-wafers 85 may be fixed on the temperature-resistant shaping layer 83, and the lower surface 03 (the surface away from the circuit layer) opposite to the upper surface 01 and the side 02 connecting the upper surface 01 and the lower surface 03 are not in contact with the temperature-resistant shaping layer 83.

Step S24

Fig. 13 is a schematic cross-sectional view illustrating a reinforced lift-off film 86 formed on the surfaces of a plurality of sub-wafers 85 according to an embodiment of the present disclosure.

Specifically, as shown in fig. 12 and 13, a reinforcing lift-off film 86 may be formed on the surface of the sub-wafer 85 that is not in contact with the temperature-resistant sizing layer 83. Alternatively, the reinforcing and de-warping film 86 may be formed on the lower surface 03 of the sub-wafer 85 and the side surface 02 of the sub-wafer 85, in other words, the reinforcing and de-warping film 86 may wrap the bottom surface (the surface far away from the circuit layer 852) and the side surface of the semiconductor substrate 851 in the sub-wafer 85 and wrap the side surface of the circuit layer 852 in the sub-wafer 85, and the chips to be packaged are formed after the reinforcing and de-warping film 86 is formed on part of the surface of the sub-wafer 85.

In one embodiment of the present application, a chip to be packaged includes a three-dimensional nonvolatile memory, wherein the three-dimensional nonvolatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

According to the preparation method of the to-be-packaged chip for the semiconductor packaging structure, the reinforcing and warping-reducing film covering the partial surface of the sub-wafer is formed in the structure of the to-be-packaged chip, so that the release direction of local mechanical stress in the to-be-packaged chip can be changed, the mechanical strength of the to-be-packaged chip is increased, and further the risks of cracks, damages or warping of the to-be-packaged chip and the problem of failure of a semiconductor packaging device are effectively avoided.

In addition, in one embodiment of the present application, a Chemical Vapor Deposition (CVD) process may be used to form a reinforced lift-off film 86 on the surface of the sub-wafer 85 not in contact with the temperature-resistant sizing layer 83. The reinforced lift-off film 86 formed by the chemical vapor deposition process may have a thinner film thickness and a denser film structure, is beneficial to changing the release direction of local mechanical stress in the chip, increases the mechanical strength of the chip, and is suitable for the packaging structure of ultra-thin chips such as three-dimensional memories.

Specifically, a chemical vapor deposition process such as Plasma Enhanced Chemical Vapor Deposition (PECVD) may be selected to prepare the reinforced lift-off film 86. Further, the process temperature of the chemical vapor deposition process may alternatively be 300 ℃ to 500 ℃.

Alternatively, the material for forming the reinforced lift-off film 86 may be silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide SiOC, silicon nitride SixNyHz containing hydrogen atoms, or the like.

Taking the example of the reinforced lift-off film 86 made of silicon nitride SixNyHz containing a certain amount of hydrogen atoms, the Si/N ratio in normal silicon nitride (SixNy) is 0.75, but the stoichiometry of PECVD deposited silicon nitride varies with the process, so that besides Si and N, the silicon nitride formed by PECVD deposition also contains a certain amount of hydrogen atoms, in other words, the silicon nitride formed by PECVD deposition is silicon nitride SixNyHz, which has the characteristics of compact structure, high hardness, high dielectric strength, etc. In addition, by controlling the process parameters, the thickness of the reinforced lift-off film 86 can be controlled, so that the formed reinforced lift-off film 86 not only has a more compact film structure, but also has a thinner film thickness.

Step S25

Fig. 14 is a schematic view of a dicing film 87 attached to a portion of the surface of the reinforced lift-off film 86 according to an embodiment of the present application. Fig. 15 is a schematic illustration of the removal of a temperature-resistant sizing layer 83 from a wafer 82, in accordance with one embodiment of the present application.

Specifically, as shown in fig. 12 to 15, the roller 88 may be selectively pressed against a part of the surface of the reinforcing and de-warping film 86 to adhere the dicing film 87 to the part of the surface of the reinforcing and de-warping film 86, and the roller 88 may be moved in a predetermined direction and rolled. The dicing film 87 may be a dicing film, a DAF film, or the like, which is not limited in this application.

Alternatively, the surface of the reinforcing lift-off film 86 to which the dicing film 87 is attached may be a surface facing the lower surface 03 of the sub-wafer 85.

In addition, after the dicing film 87 is formed, the temperature-resistant sizing layer 83 on the upper surface 01 of the sub-wafer 85 may be removed. The temperature-resistant shaping layer 83 has the characteristics of temperature resistance, shaping and easy removal, and can be removed after the reinforcing warping-reducing film 86 is formed. In one embodiment of the present application, the temperature-resistant shaping layer 83 may be removed by a de-curing process such as UV, heat or laser, and the process of removing the temperature-resistant shaping layer 83 is not limited in the present application.

Step S26

The method 3000 for manufacturing a chip to be packaged for a semiconductor package structure further includes step S26: and carrying out scribing treatment to obtain a plurality of independent chips to be packaged, wherein the chips to be packaged comprise the sub-wafer and the reinforcing and warping reducing film formed on part of the surface of the sub-wafer.

In one embodiment of the present application, the dicing film adhered to the partial surface of the reinforced lift-off film is a thin film having an adhesive layer, which can fix a plurality of independent chips to be packaged. However, since the pitch between the individual chips to be packaged is small, the pitch can be further enlarged to facilitate the pickup of the subsequent chips.

Alternatively, a cold-collapse process may be used to increase the spacing between individual chips to be packaged. In the cold-collapse process, the cut wafer may be placed in a low-temperature environment, which is usually lower than room temperature, so that the dicing film is stressed in an outward direction along the radius of the wafer, and the dicing film is stretched and deformed, thereby increasing the distance between the chips to be packaged.

In addition, since the content related to the above description of the semiconductor package structure and the manufacturing method can be fully or partially applied to the manufacturing method of the chip to be packaged for the semiconductor package structure described herein, the content related or similar to the above description is not repeated.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A semiconductor package structure, comprising:

a package substrate;

a multilayer chip stacking structure attached to the package substrate and including a plurality of chips stacked in sequence; and

a molding compound layer formed on a surface of the package substrate and encapsulating the multi-layered chip stacking structure,

characterized in that the chip comprises:

a semiconductor substrate comprising opposing first and second surfaces;

a circuit layer formed on the first surface; and

and the reinforcing warping reduction film covers the second surface.

2. The semiconductor package structure of claim 1, wherein the semiconductor substrate further comprises a substrate side connecting the first surface and the second surface; and

the reinforced warping reduction film further covers the side face of the substrate and the side face of the circuit layer.

3. The semiconductor package structure of claim 1 or 2, wherein the thickness of the reinforced lift-off film is 1% to 17% of the common thickness of the semiconductor substrate and the circuit layer.

4. The semiconductor package structure of claim 1 or 2, wherein the common thickness of the semiconductor substrate and the circuit layer is 30-50 microns, and the thickness of the reinforced lift-off film is 0.5-5 microns.

5. The semiconductor package structure of claim 4, wherein the thickness of the reinforced lift-off film is larger as the thickness of the circuit layer is larger, without changing the common thickness.

6. The semiconductor package structure of claim 1 or 2, wherein the reinforced lift-off film is a single layer structure or a composite structure.

7. The semiconductor package structure of claim 1 or 2, wherein the reinforced lift-off film is at least one of a nitride layer, a silicide layer, and an oxide layer.

8. The semiconductor package structure of claim 1 or 2, wherein the reinforced lift-off film is prepared by a chemical vapor deposition process.

9. The semiconductor package structure of claim 1 or 2, wherein the chip comprises a three-dimensional non-volatile memory, wherein the three-dimensional non-volatile memory comprises at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

10. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:

attaching a multi-layered chip stacking structure to a package substrate, wherein the multi-layered chip stacking structure includes a plurality of chips stacked in sequence; and

forming a molding compound layer for encapsulating the multi-layered chip stacking structure on a surface of the package substrate,

wherein the chip comprises:

a semiconductor substrate comprising opposing first and second surfaces;

a circuit layer formed on the first surface; and

and the reinforcing warping reduction film covers the second surface.

11. The method of claim 10,

the semiconductor substrate further comprises a substrate side surface connecting the first surface and the second surface; and

12. The method according to claim 10 or 11,

the thickness of the reinforced warping reduction film is 1% -17% of the common thickness of the semiconductor substrate and the circuit layer.

13. The method according to claim 10 or 11,

the common thickness of the semiconductor substrate and the circuit layer is 30-50 microns, and the thickness of the reinforced warping reduction film is 0.5-5 microns.

14. The method of claim 13,

under the condition that the common thickness is not changed, the thickness of the reinforcing and warping reducing film is set to be larger as the thickness of the circuit layer is larger.

15. The method of claim 10 or 11, wherein the reinforced lift-off film is provided as a single layer structure or a composite structure.

16. The method of claim 10 or 11, wherein the reinforced lift-off film is at least one of a nitride layer, a silicide layer, and an oxide layer.

17. The method according to claim 10 or 11,

and preparing the reinforced warping reduction film by adopting a chemical vapor deposition process.

18. The method according to claim 10 or 11,

the chip includes a three-dimensional nonvolatile memory, wherein the three-dimensional nonvolatile memory includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

19. A preparation method of a chip to be packaged for a semiconductor packaging structure is characterized by comprising the following steps:

half-cutting the wafer from the front side of the wafer, which is provided with the circuit layer;

a temperature-resistant shaping layer is arranged on the front surface;

thinning the wafer from the back side opposite to the front side so as to separate the wafer into a plurality of independent sub-wafers fixed on the temperature-resistant shaping layer;

forming a reinforced warping reduction film on the surface of the sub-wafer, which is not in contact with the temperature-resistant shaping layer;

adhering a scribing film on the partial surface of the reinforced warping reduction film, and removing the temperature-resistant shaping layer; and

and scribing to obtain a plurality of independent chips to be packaged, wherein the chips to be packaged comprise the sub-wafer and the reinforced warping reducing film formed on part of the surface of the sub-wafer.

20. The method of claim 19, wherein the sub-wafer includes an upper surface and a lower surface opposite to each other, and a side surface of the sub-wafer connecting the upper surface and the lower surface, the upper surface of the sub-wafer being fixed on the temperature-resistant shaping layer, wherein forming a reinforced lift-off film on a surface of the sub-wafer not in contact with the temperature-resistant shaping layer comprises:

and forming the reinforced warping reduction film on the lower surface of the sub-wafer and the side surface of the sub-wafer.

21. The method of claim 19 or 20, wherein forming a reinforced lift-off film on a surface of the sub-wafer not in contact with the temperature-resistant sizing layer comprises:

and forming the reinforced warping reduction film on the surface of the sub-wafer, which is not in contact with the temperature-resistant sizing layer, by adopting a chemical vapor deposition process.

22. The method of claim 19 or 20,

the temperature-resistant shaping layer is a quartz glass layer.

23. The method of claim 19 or 20, wherein providing a temperature-resistant sizing layer on the front side comprises:

and arranging the temperature-resistant shaping layer on the front surface by adopting an adhesive or laminating process.

24. The method of claim 19 or 20,

the chip to be packaged comprises a three-dimensional nonvolatile memory, wherein the three-dimensional nonvolatile memory comprises at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.