CN114080121B - Method for manufacturing embedded element circuit board and embedded element circuit board - Google Patents
Method for manufacturing embedded element circuit board and embedded element circuit board Download PDFInfo
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- CN114080121B CN114080121B CN202010845664.3A CN202010845664A CN114080121B CN 114080121 B CN114080121 B CN 114080121B CN 202010845664 A CN202010845664 A CN 202010845664A CN 114080121 B CN114080121 B CN 114080121B
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- circuit substrate
- insulating layer
- ink
- layer
- circuit board
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 142
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000006229 carbon black Substances 0.000 claims abstract description 25
- 238000003825 pressing Methods 0.000 claims abstract description 5
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 138
- 230000009974 thixotropic effect Effects 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000003292 glue Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- YKTSYUJCYHOUJP-UHFFFAOYSA-N [O--].[Al+3].[Al+3].[O-][Si]([O-])([O-])[O-] Chemical compound [O--].[Al+3].[Al+3].[O-][Si]([O-])([O-])[O-] YKTSYUJCYHOUJP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000000378 calcium silicate Substances 0.000 description 1
- 229910052918 calcium silicate Inorganic materials 0.000 description 1
- OYACROKNLOSFPA-UHFFFAOYSA-N calcium;dioxido(oxo)silane Chemical compound [Ca+2].[O-][Si]([O-])=O OYACROKNLOSFPA-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910021485 fumed silica Inorganic materials 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
A manufacturing method of an embedded element circuit board comprises the following steps: providing a first circuit substrate; connecting at least two mutually independent elements on the surface of the first circuit substrate, wherein the at least two elements have a first height difference in a first direction; providing a first insulating layer with a first opening and a second circuit substrate with a second opening, sequentially stacking the first insulating layer and the second circuit substrate along a first direction on the surface of the first circuit substrate with the element and pressing, wherein the first opening and the second opening are communicated to form a containing space, and the element is contained in the containing space; filling white carbon black-containing ink in the accommodating space through vacuum printing, and curing the ink to form an ink layer, wherein the ink layer covers the element, and the surface of the ink layer, which is far away from the first circuit substrate, is provided with a second height difference, and the second height difference is smaller than the first height difference; and forming a second insulating layer on the surface of the second circuit substrate, which is away from the first circuit substrate, and covering the ink layer. The application also provides a circuit board with embedded elements.
Description
Technical Field
The present disclosure relates to the field of circuit board manufacturing, and in particular, to a method for manufacturing a circuit board with embedded components and a circuit board with embedded components.
Background
Along with the miniaturization development of electronic equipment, the packaging structure of a circuit board in the electronic equipment is more and more centralized, so as to improve the wiring density of the circuit board, and meanwhile, the circuit board is miniaturized by embedding elements in the circuit board.
In the embedding scheme of the element, the element with small size is mainly embedded, and bubbles remain in the pressing process of the circuit board due to the undersize of the element, so that the quality of the circuit board is affected; in addition, the components with different sizes can cause the problems of glue shortage, dent and the like due to the height difference in the pressing process of the circuit board, so that the manufactured circuit board is uneven and has poor quality.
Disclosure of Invention
In view of the foregoing, there is a need for a method of manufacturing a circuit board with embedded components that eliminates air bubbles and compensates for height differences, so as to solve the above-mentioned problems.
In addition, the application also provides an embedded element circuit board.
A manufacturing method of an embedded element circuit board comprises the following steps:
providing a first circuit substrate;
connecting at least two mutually independent elements on the surface of the first circuit substrate, wherein at least two elements have a first height difference in a first direction;
providing a first insulating layer with a first opening and a second circuit substrate with a second opening, and sequentially stacking the first insulating layer and the second circuit substrate on the surface of the first circuit substrate with the element along the first direction and pressing, wherein the first opening and the second opening are communicated to form a containing space, and the element is contained in the containing space;
filling white carbon black-containing ink in the accommodating space through vacuum printing, and curing the ink to form an ink layer, wherein the ink layer covers the element, and the surface of the ink layer, which is far away from the first circuit substrate, is provided with a second height difference which is smaller than the first height difference; and
and forming a second insulating layer on the surface of the second circuit substrate, which is away from the first circuit substrate, and covering the ink layer.
Further, the manufacturing method further comprises the following steps: and forming a third circuit substrate on the surface of the second insulating layer, which is away from the second circuit substrate, and covering the second insulating layer.
Further, the manufacturing method further comprises the following steps: and forming a solder mask layer on the surfaces of the first circuit substrate and the third circuit substrate, which are away from the second circuit substrate, wherein the solder mask layer coats the first circuit substrate and the third circuit substrate.
Further, the volume fraction of the white carbon black in the ink is 0.1% -30%.
Further, the length of the accommodating space along the second direction is greater than the sum of the lengths of at least two elements in the second direction, wherein the second direction is perpendicular to the first direction.
A circuit board with embedded components comprises a first circuit substrate, a first insulating layer, a second circuit substrate, at least two components, an ink layer and a second insulating layer. The first insulating layer is overlapped on the surface of the first circuit substrate along a first direction; the second circuit substrate is overlapped on the surface, away from the first circuit substrate, of the first insulating layer along the first direction, and a containing space penetrating through the first insulating layer and the second circuit substrate is formed along the first direction; at least two components are provided with a first height difference in the first direction, and are accommodated in the accommodating space; the ink layer fills the gaps between the element and the first insulating layer and between the element and the second circuit substrate, white carbon black is arranged in the ink layer, the surface of the ink layer, which is far away from the first circuit substrate, is provided with a second height difference, and the second height difference is smaller than the first height difference; the second insulating layer is positioned on the surface of the second circuit substrate, which is away from the first circuit substrate, and covers the ink layer.
Further, the embedded component circuit board further comprises a third circuit substrate, and the third circuit substrate is located on the surface, away from the second circuit substrate, of the second insulating layer and covers the second insulating layer.
Further, the embedded component circuit board further comprises a solder mask layer, and the solder mask layer respectively coats the surfaces of the first circuit substrate and the third circuit substrate, which are far away from the second circuit substrate.
Further, the volume fraction of the white carbon black in the ink is 0.1% -30%.
Further, the length of the accommodating space along the second direction is greater than the sum of the lengths of at least two elements in the second direction, wherein the second direction is perpendicular to the first direction.
According to the manufacturing method of the embedded component circuit board, bubbles between the component and the first circuit substrate, the first insulating layer or the second circuit substrate can be removed through the mode of vacuum printing of the ink, and the bubbles in the ink can be removed at the same time; in addition, the thixotropic ink can further remove bubbles and greatly reduce the height difference of elements with different heights away from the surface of the first circuit substrate by controlling the shear rate and the volume fraction of the white carbon black so as to ensure that the ink has proper fluidity, and the second height difference is supplemented by the second insulating layer of the low-flow glue prepreg so as to obtain the embedded element circuit board with a flat surface.
Drawings
Fig. 1 is a schematic cross-sectional view of a first circuit substrate according to an embodiment of the present application.
Fig. 2 is a schematic cross-sectional view of connecting components having different heights on the surface of the first circuit substrate shown in fig. 1.
Fig. 3 is a schematic cross-sectional view of a first insulating layer surrounding the element provided on the surface of the first circuit substrate shown in fig. 2.
Fig. 4 is a schematic cross-sectional view of a second circuit substrate surrounding the element disposed on the surface of the first insulating layer shown in fig. 3.
Fig. 5 is a schematic cross-sectional view of a gap-filling ink-forming ink layer between the element shown in fig. 4 and the first insulating layer and the second wiring substrate.
Fig. 6 is a schematic cross-sectional view of a second insulating layer covering the ink layer and a third circuit substrate formed on the surface of the second circuit substrate shown in fig. 5.
Fig. 7 is a schematic cross-sectional view of a solder mask layer formed on the surfaces of the first circuit substrate and the third circuit substrate shown in fig. 6.
FIG. 8 is a graph showing the change in the ink versus shear rate for a volume fraction of 20% white carbon in the ink.
FIG. 9 shows a shear rate of 0.25s -1 In this case, the viscosity of the ink and the volume fraction of the white carbon black are plotted.
Description of the main reference signs
Circuit board 100 with embedded components
First circuit board 10
First dielectric layer 11
First circuit layer 13
Element 20
First element 20a
Second element 20b
First insulating layer 30
First opening 31
Second circuit board 40
Second dielectric layer 41
Second circuit layer 43
Second opening 45
The accommodating space 50
Ink layer 60
Second insulating layer 70
Third line substrate 80
Third circuit layer 81
Solder mask layer 90
First direction L1
Second direction L2
First height difference delta H1
Second height difference delta H2
The following detailed description will further illustrate the application in conjunction with the above-described figures.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description. In addition, embodiments of the present application and features of the embodiments may be combined with each other without conflict. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, and the described embodiments are merely some, rather than all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes all and any combination of one or more of the associated listed items.
In various embodiments of the present application, for ease of description and not limitation, the term "coupled" as used in the specification and claims of the present application is not limited to physical or mechanical coupling, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which change accordingly when the absolute position of the object to be described changes.
Referring to fig. 1 to 7, a method for manufacturing a circuit board 100 with embedded components is provided in an embodiment of the present application, which includes the following steps:
step S1: referring to fig. 1, a first circuit substrate 10 is provided.
The first circuit board 10 includes a first dielectric layer 11 and a first circuit layer 13 on the first dielectric layer 11.
The first circuit board 10 may be a flexible board, a rigid board, or a flexible-rigid board.
The material of the first dielectric layer 11 may be, but is not limited to, one of Polyimide (PI), glass fiber epoxy (FR 4), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethylene (PE), and the like.
The first circuit layer 13 may be disposed as required, for example, the first circuit layer 13 is located on one surface or two opposite surfaces of the first dielectric layer 11. The method of forming the first wiring layer 13 includes, but is not limited to, a transfer method, an additive method, a subtractive method, or the like.
In some embodiments, the first circuit substrate 10 may be a multi-layer circuit substrate, that is, the first circuit substrate 10 further includes at least one other circuit layer embedded in the first dielectric layer 11 and stacked with the first circuit layer 13.
Step S2: referring to fig. 2, at least two mutually independent elements 20 are connected to the surface of the first circuit board 10, and at least two of the elements 20 have a first height difference Δh1 in the first direction L1.
In the present embodiment, the number of the elements 20 is two, and the elements 20 include a first element 20a and a second element 20b, and the first element 20a and the second element 20b have a first height difference Δh1 in the first direction L1. Each of the elements 20 is electrically connected with the first circuit board 10. In other embodiments, the number of elements 20 may be multiple.
Step S3: referring to fig. 3 and 4, a first insulating layer 30 and a second circuit substrate 40 are provided, the first insulating layer 30 has a first opening 31, the second circuit substrate 40 has a second opening 45, the first insulating layer 30 and the second circuit substrate 40 are stacked in sequence along the first direction L1, and pressed together on the surface of the first circuit substrate 10 having the component 20, wherein the first opening 31 and the second opening 45 are communicated to form a receiving space 50, and the component 20 is received in the receiving space 50.
The first insulating layer 30 has at least one first opening 31, and the first opening 31 penetrates through the first insulating layer 30, and the first insulating layer 30 is stacked on the surface of the first circuit substrate 10 having the element 20 along the first direction L1, so that the element 20 is accommodated in the first opening 31.
The first insulating layer 30 is a low-flow prepreg including a resin material including at least one of epoxy resin (FR 4), polyimide (PI), and acrylic resin. The low-flow prepreg has a smaller overflow width when hot-pressed, and prevents the first insulating layer 30 from entering the area where the element 20 is connected to the first circuit substrate 10, thereby reducing the possibility of generating bubbles.
In the same said first opening 31, there are at least two elements 20 of a first height difference Δh1. The first insulating layer 30 is disposed at a distance from the element 20, so that the first insulating layer 30 can be further prevented from entering the area where the element 20 is connected to the first circuit substrate 10 during the subsequent lamination process, thereby reducing the possibility of generating bubbles.
The first openings 31 are formed by, but not limited to, laser cutting or die cutting.
The length of the first opening 31 along the second direction L2 is greater than the sum of the lengths of the first element 20a and the second element 20b along the second direction L2, so that the element 20 is accommodated in the first opening 31 and the first insulating layer 30 is disposed at a distance from the first element 20a and the second element 20 b. Wherein the second direction L2 is perpendicular to the first direction L1.
The second circuit substrate 40 includes at least one second opening 45, the second opening 45 penetrates through the second circuit substrate 40, the second circuit substrate 40 is stacked on the surface of the first insulating layer 30, which is far away from the first circuit substrate 10, along the first direction L1, the second opening 45 and the first opening 31 are stacked on and communicated with each other along the first direction L1 to form the accommodating space 50, and the component 20 is accommodated in the accommodating space 50.
The second circuit substrate 40 includes a second dielectric layer 41 and a second circuit layer 43 disposed on the second dielectric layer 41, and the second opening 45 penetrates through the second dielectric layer 41 and the second circuit layer 43. In this embodiment, the second circuit substrate 40 is a dual-layer circuit substrate, and includes one second dielectric layer 41 and two second circuit layers 43. The two second circuit layers 43 are located on two opposite surfaces of the second dielectric layer 41. The second opening 45 penetrates the second circuit substrate 40 along the lamination direction of the second dielectric layer 41 and the second circuit layer 43. In other embodiments, the second circuit substrate 40 may be a single-layer circuit layer substrate or a multi-layer circuit substrate.
Further, the second dielectric layer 41 protrudes inward toward the center of the second opening 45 along the second direction L2, and the protruding portion of the second dielectric layer 41 is used to prevent the element 20 from contacting the second circuit layer 43 during the process of accommodating the element 20 on the second circuit substrate 40.
It can be appreciated that at least the first element 20a and the second element 20b having the first height difference Δh1 are located in the same accommodating space 50.
The length of the second opening 45 along the second direction L2 is greater than the sum of the lengths of the first element 20a and the second element 20b along the second direction L2, that is, the length of the accommodating space 50 along the second direction L2 is greater than the sum of the lengths of the first element 20a and the second element 20b along the second direction L2, so that the element 20 is accommodated in the accommodating space 50 and the second circuit substrate 40 is disposed at a distance from the first element 20a and the second element 20 b.
The second openings 45 are formed by a means including, but not limited to, laser cutting or die cutting.
Before the second circuit substrate 40 is stacked on the first insulating layer 30, the method further includes the following steps: a through hole (not shown) penetrating the first insulating layer 30 is formed along the first direction L1, and a conductive post (not shown) is formed in the through hole, so that the first circuit substrate 10 is electrically connected to a second circuit substrate 40 subsequently formed on the surface of the first insulating layer 30.
In another embodiment, the step of sequentially disposing the first insulating layer 30 and the second circuit substrate 40 on the surface of the first circuit substrate 10 may be performed before the step of disposing the element 20 on the first circuit substrate 10, that is, after the accommodating space 50 is formed, the element 20 is accommodated in the accommodating space 50 and electrically connected to the first circuit substrate 10.
Step S5: referring to fig. 5, the ink containing white carbon black is filled in the accommodating space 50 by vacuum printing, the ink is cured to form an ink layer 60, the ink layer 60 covers the component 20, wherein the surface of the ink layer 60 away from the first circuit board 10 has a highest point and a lowest point, the difference between the highest point and the lowest point is a second height difference Δh2, and the second height difference Δh2 is smaller than the first height difference Δh1.
The chemical formula of the white carbon black can be expressed as SiO 2 ·nH 2 O，nH 2 O is in the form of surface hydroxyl groups. The white carbon black is the general term of amorphous silicic acid and silicate products, mainly refers to precipitated silica, fumed silica and superfine silica gel, and also comprises powdery synthetic aluminum silicate, calcium silicate and the like. The white carbon black has stable chemical property, is a porous substance, is insoluble in water, resistant to high temperature, is not burnt, resistant to acid and alkali, free of pollution, and has good electrical insulation property and high dispersibility.
The ink has thixotropic properties, which are reversible. The viscosity of the ink is inversely proportional to the shear rate when subjected to a shearing force, i.e., the greater the shear rate, the less the viscosity of the ink.
The viscosity of the ink can be reduced under the same condition when the white carbon black is added into the ink compared with the ink without the white carbon black, so that the fluidity of the ink is ensured more favorably. Referring to fig. 8, fig. 8 is a graph showing the relationship between the ink and the shear rate when the volume fraction of white carbon black in the ink is 20%.
The volume fraction of the white carbon black in the ink is 0.1-30%, and the viscosity of the ink is proportional to the volume fraction, namely the viscosity of the ink increases with the increase of the volume fraction of the white carbon black. Referring to fig. 9, fig. 9 shows a shear rate of0.25s -1 And when the viscosity of the ink is changed, the relation between the viscosity of the ink and the volume fraction of the white carbon black is changed.
By vacuum printing the ink, bubbles between the element 20 and the first circuit substrate 10, the first insulating layer 30 or the second circuit substrate 40 can be removed, and bubbles in the ink can be removed; in addition, the thixotropic ink can further remove bubbles and greatly reduce the height difference of the elements 20 with different heights away from the surface of the first circuit substrate 10 by controlling the shear rate and the volume fraction of the white carbon black so that the ink has proper viscosity to ensure the fluidity of the ink, so that the second height difference delta H2 is far smaller than the first height difference delta H1.
Step S6: referring to fig. 6, a second insulating layer 70 is formed on the surface of the second circuit substrate 40 facing away from the first circuit substrate 10 and covers the ink layer 60.
The second insulating layer 70 is made of the same material as the first insulating layer 30, i.e. a low-flow prepreg. By covering the elements 20 having different heights with thixotropic ink, after the height difference is greatly reduced, the process of grinding the ink layer 60 is not required, and the surface of the second insulating layer 70 adjacent to the ink layer 60 having low overflow property can compensate for the second height difference Δh2 and maintain the flatness of the second insulating layer 70 facing away from the ink layer 60, so that the prepared embedded element circuit board 100 is prevented from being recessed in the subsequent steps.
Step S7: referring to fig. 6 again, a third circuit substrate 80 is formed on the surface of the second insulating layer 70 facing away from the second circuit substrate 40 and covers the second insulating layer 70, so as to obtain the embedded component circuit board 100.
The third circuit substrate 80 includes a third circuit layer 81, and the third circuit substrate 80 may further include a third dielectric layer (not shown). The third circuit layer 81 is formed by, but not limited to, covering the surface of the second insulating layer 70 with a copper layer, and etching the copper layer to form the third circuit layer 81.
Further, referring to fig. 7, the manufacturing method further includes the following steps: a solder mask is formed on the surfaces of the first circuit substrate 10 and the third circuit substrate 80 facing away from the second circuit substrate 40, and the solder mask covers the first circuit substrate 10 and the third circuit substrate 80.
Referring to fig. 1 to 7 again, the present application further provides an embedded component circuit board 100, where the embedded component circuit board 100 includes a first circuit board 10, a first insulating layer 30, a second circuit board 40, and a second insulating layer 70 stacked in sequence along a first direction L1, and the embedded component circuit board 100 further includes at least two components 20 having a first height difference Δh1 along the first direction L1 and an ink layer 60.
The first circuit board 10 includes a first dielectric layer 11 and a first circuit layer 13 disposed on a surface of the first dielectric layer 11.
The first insulating layer 30 is located on a surface of the first circuit substrate 10.
The second circuit substrate 40 includes a second dielectric layer 41 and a second circuit layer 43 disposed on the surface of the second dielectric layer 41, and the second circuit substrate 40 is electrically connected to the first circuit substrate 10.
The embedded component circuit board 100 further includes a receiving space 50, the receiving space 50 penetrates through the first dielectric layer 11 and the second circuit substrate 40 along the first direction L1, and the component 20 is received in the receiving space 50 and electrically connected to the first circuit substrate 10. The ink layer 60 fills the gap between the element 20 and the first insulating layer 30 and the second circuit substrate 40, and the ink layer 60 also covers the surface of the element 20 away from the first circuit substrate 10.
Wherein the surface of the ink layer 60 remote from the first circuit board 10 has a second height difference Δh2, the second height difference Δh2 being smaller than the first height difference Δh1.
The ink layer 60 includes the white carbon black therein, and the volume fraction of the white carbon black in the ink layer 60 is 0.1% to 30%.
The second insulating layer 70 is located on the surface of the second circuit substrate 40 facing away from the first circuit substrate 10 and covers the ink layer 60, and the second insulating layer 70 compensates the second height difference Δh2.
The embedded component circuit board 100 further includes a third circuit board 80, the third circuit board 80 is located on the surface of the second insulating layer 70 facing away from the second circuit board 40 and covers the second insulating layer 70, and the third circuit board 80 is electrically connected to the second circuit board 40 and the first circuit board 10.
The embedded component circuit board 100 further includes a solder mask layer, which covers the surfaces of the first circuit substrate 10 and the third circuit substrate 80, which are far away from the second circuit substrate 40, respectively.
The materials of the first insulating layer 30 and the second insulating layer 70 are the low-flow glue prepreg.
According to the manufacturing method of the embedded component circuit board 100, bubbles between the component 20 and the first circuit substrate 10, the first insulating layer 30 or the second circuit substrate 40 can be removed by vacuum printing of the ink, and bubbles in the ink can be removed at the same time; in addition, the thixotropic ink, by controlling the shear rate and the volume fraction of the white carbon black, so that the ink has proper fluidity, not only can further remove bubbles, but also can greatly reduce the height difference of the components 20 with different heights from the surface of the first circuit substrate 10, and then the second height difference is supplemented by the second insulating layer 70 of the low-flow prepreg, so as to obtain the embedded component circuit board 100 with a flat surface.
The above embodiments are only for illustrating the technical solution of the present application and not for limiting, and although the present application has been described in detail with reference to the above preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present application may be modified or substituted without departing from the spirit and scope of the technical solution of the present application.
Claims (10)
1. The manufacturing method of the embedded element circuit board is characterized by comprising the following steps of:
providing a first circuit substrate;
connecting at least two mutually independent elements on the surface of the first circuit substrate, wherein at least two elements have a first height difference in a first direction;
providing a first insulating layer with a first opening and a second circuit substrate with a second opening, and sequentially stacking the first insulating layer and the second circuit substrate on the surface of the first circuit substrate with the element along the first direction and pressing, wherein the first opening and the second opening are communicated to form a containing space, and the element is contained in the containing space;
filling white carbon black-containing ink in the accommodating space through vacuum printing, and curing the ink to form an ink layer, wherein the ink layer covers the element, and the surface of the ink layer, which is far away from the first circuit substrate, is provided with a second height difference which is smaller than the first height difference; and
and forming a second insulating layer on the surface of the second circuit substrate, which is away from the first circuit substrate, and covering the ink layer.
2. The method of manufacturing a circuit board with embedded components according to claim 1, further comprising the steps of:
and forming a third circuit substrate on the surface of the second insulating layer, which is away from the second circuit substrate, and covering the second insulating layer.
3. The method of manufacturing a circuit board with embedded components according to claim 2, further comprising the steps of:
and forming a solder mask layer on the surfaces of the first circuit substrate and the third circuit substrate, which are away from the second circuit substrate, wherein the solder mask layer coats the first circuit substrate and the third circuit substrate.
4. The method of claim 1, wherein the white carbon black is present in the ink in an amount of 0.1% to 30% by volume.
5. The method of claim 1, wherein the length of the accommodating space along the second direction is greater than the sum of the lengths of at least two of the components along the second direction, and wherein the second direction is perpendicular to the first direction.
6. A circuit board with embedded components, comprising:
a first circuit substrate;
the first insulating layer is overlapped on the surface of the first circuit substrate along the first direction;
the second circuit substrate is overlapped on the surface of the first insulating layer, which is away from the first circuit substrate, along the first direction, and is provided with a containing space penetrating through the first insulating layer and the second circuit substrate along the first direction;
at least two elements with a first height difference along the first direction are accommodated in the accommodating space;
an ink layer filling gaps between the element and the first insulating layer and between the element and the second circuit substrate, wherein white carbon black is arranged in the ink layer, and the surface of the ink layer, which is far away from the first circuit substrate, is provided with a second height difference which is smaller than the first height difference; and
the second insulating layer is positioned on the surface of the second circuit substrate, which is away from the first circuit substrate, and covers the ink layer.
7. The embedded component circuit board of claim 6, further comprising a third wiring substrate located on a surface of the second insulating layer facing away from the second wiring substrate and covering the second insulating layer.
8. The embedded component circuit board of claim 7, further comprising solder masks that encapsulate surfaces of the first circuit substrate and the third circuit substrate that are remote from the second circuit substrate, respectively.
9. The embedded component circuit board of claim 6, wherein the white carbon black is present in the ink in an amount of 0.1% to 30% by volume.
10. The embedded component circuit board of claim 6, wherein a length of the receiving space along a second direction is greater than a sum of lengths of at least two of the components along the second direction, wherein the second direction is perpendicular to the first direction.
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| CN202010845664.3A CN114080121B (en) | 2020-08-20 | 2020-08-20 | Method for manufacturing embedded element circuit board and embedded element circuit board |
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| CN202010845664.3A CN114080121B (en) | 2020-08-20 | 2020-08-20 | Method for manufacturing embedded element circuit board and embedded element circuit board |
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| CN114080121B true CN114080121B (en) | 2024-04-12 |
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| CN114080121A (en) | 2022-02-22 |
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