CN114077562A - Protocol processing IP core of 1553B bus controller - Google Patents
Protocol processing IP core of 1553B bus controller Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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Abstract
The invention discloses a protocol processing IP core of a 1553B bus controller, which is arranged between a CPU and a 1553B bus, and comprises an AXI slave device interface, a register, a shared RAM, an instruction control logic unit, an RAM management unit, a BC protocol processor, an encoder, a decoder and a 1553B transceiver; the AXI slave equipment interface is used for realizing the initialization read-write operation of the CPU on the register and the shared RAM; the register is used for writing information through the CPU and configuring the IP core to realize a 1553B bus data communication function; the BC protocol processor is also used for writing information and recording the working state of the IP core; the shared RAM is used for storing a BC instruction list, a description of a BC message block and various data; the instruction control logic unit is used for carrying out message sequence control on the messages of the CPU; the BC protocol processor is also used for scheduling the messages processed by the BC protocol processor based on the BC instruction list; and the BC protocol processor is used for analyzing and processing the received message and sending the processed data word to the encoder.
Description
Technical Field
The invention relates to the field of data communication, in particular to a 1553B bus controller protocol processing IP core.
Background
The 1553B bus is a time division command/response type multiplexed half-duplex data bus, and the bus structure comprises: the A/B buses which are redundant backup of each other are connected with three terminal types: a Bus Controller (BC), a Remote Terminal (RT) and a Bus Monitor (BM). The bus controller plays a role in initially controlling all information transmission transactions on the bus, the remote terminal completes information transmission between the BC and the RT, the bus monitor does not participate in communication, and the monitoring function of the information transmission process on the 1553B bus is completed. There can be 1 bus controller on the bus, 31 remote terminals, and the bus monitor is optional.
At present, the internal protocol processing logic of the domestic bus controller is relatively lagged, the protocol processing is not flexible enough, the participation degree of a CPU is higher, and the message can be scheduled and managed only by continuous participation of the CPU when the message is continuously configured on software.
Disclosure of Invention
The technical problem to be solved by the invention is that the protocol processing flexibility is low and the CPU participation degree is high in the prior art, so that a 1553B bus controller IP core with strong flexibility is provided.
In order to achieve the above object, the present invention provides a 1553B bus controller protocol processing IP core, which is disposed between a CPU and a 1553B bus, and includes an AXI slave interface, a register, a shared RAM, an instruction control logic unit, a RAM management unit, a BC protocol processor, an encoder, a decoder, and a 1553B transceiver;
the AXI slave equipment interface is used for connecting the IP core to an AMBAAXI bus and enabling the IP core to work as a peripheral of the AXI bus; the CPU is also used for carrying out initialization read-write operation on the register and the shared RAM;
the register is used for writing information through the CPU and configuring the 1553B bus data communication function of the IP core; the BC protocol processor is also used for writing information and recording the working state of the IP core;
the shared RAM is used for storing a BC instruction list, description of a BC message block and various data;
the instruction control logic unit is used for performing message sequence control on the message of the CPU; the BC protocol processor is also used for scheduling the messages processed by the BC protocol processor based on the BC instruction list;
the RAM management unit is used for managing a shared RAM and distributing the shared RAM for the instruction control logic unit and the BC protocol processor;
the BC protocol processor is used for analyzing and processing the received message and sending the processed data word to the encoder;
the decoder is used for decoding the data sent by the 1553B transceiver and sending the data to the BC protocol processor;
the encoder is used for encoding the data sent by the BC protocol processor and sending the data to the 1553B transceiver;
the 1553B transceiver is used for receiving the data words and the state words transmitted on the 1553B bus and forwarding the data words and the state words to the decoder, and is also used for receiving the data output by the decoder and forwarding the data to the 1553B bus.
As an improvement of the above system, the shared RAM includes a BC instruction list area, a BC message block specification area, and a data area; the BC instruction list area is used for storing a plurality of arranged instructions, and each instruction consists of two words: an instruction code and a parameter word; an instruction code comprising: an operation code and an execution condition code; the BC message block description area stores the description of each BC message block; the sequencing of the BC message uses an instruction code list, and the starting address of the BC instruction list for controlling the sequencing of the BC message starts from a fixed position; the data area comprises a data word to be sent and a data word to be received, and the sizes of the data sending area and the data receiving area are configured through a configuration register.
As an improvement of the above system, the parameter words are matched with their instruction codes, the parameter words including: time value, parameter value to set or clear flag bit, certain address pointer value of instruction list and memory pointer value of message block start address.
As an improvement of the above system, each instruction code is 16 bits: the most significant bit is a parity bit, a 5-bit opcode field, 5 bits are a validation field, and a 5-bit condition code field.
As an improvement of the above system, when processing the CPU message, the instruction control logic unit obtains and executes an instruction code from the BC instruction list, and the pointer address points to the first word in the message block, i.e. the BC control word; when the message block is executed, the shared RAM space is opened up separately for storing the data to be sent or received, and after the execution is finished, the BC instruction list address pointer is updated according to the completion mark of the message.
As an improvement of the above system, when the instruction control logic unit obtains one or more instruction codes of error condition, the IP core immediately stops executing; the instruction code for the error condition includes: bit15 even parity, bit14-10 contains an undefined opcode and a validation field bits 9-5 not equal to 01010.
As an improvement of the above system, the message received by the BC protocol processor includes: BC to RT send messages, RT to BC send messages, RT to RT send messages, and broadcast messages.
As an improvement of the above system, the encoder performs manchester encoding on data to be transmitted, and converts the unipolar code into a manchester type ii code transmitted on a 1553B bus; the decoder carries out Manchester decoding on data to be transmitted and converts a Manchester II type code transmitted by a 1553B bus into a unipolar code.
The advantages of this aspect are:
1. the invention adopts a Manchester type II biphase coding scheme, thereby improving the reliability of a transmission system;
2. the message sequence control scheme provided by the invention arranges the message sequence in an operation code mode, and realizes the functions of realizing message scheduling and arranging in software in hardware, so that a bus controller can spontaneously arrange message flow, and the message processing is more flexible and intelligent; the processing workload of the CPU is greatly reduced;
3. the IP core has strong portability, and can be transplanted to FPGA, ASIC and SOC chips.
Drawings
FIG. 1 is a block diagram of a 1553B bus controller protocol processing IP core of the present invention;
FIG. 2 is a diagram of a shared RAM according to the present invention;
FIG. 3 is a block diagram of the BC instruction list according to the present invention.
Detailed Description
The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, a 1553B bus controller protocol processing IP core is disposed between a CPU and a 1553B bus, and includes an AXI slave interface, a register, a shared RAM, an instruction control logic unit, a RAM management unit, a BC protocol processor, an encoder, a decoder, and a 1553B transceiver;
the AXI slave equipment interface is connected with the CPU through the AXI and respectively connected with the shared RAM and the register; the AXI slave equipment interface is used for connecting the IP core to the AMBAAXI bus and enabling the IP core to work as a peripheral of the AXI bus; the CPU is also used for carrying out initialization read-write operation on the register and the shared RAM;
the register is used for writing information through the CPU and configuring the 1553B bus data communication function of the IP core; the BC protocol processor is also used for writing information and recording the working state of the IP core;
the shared RAM comprises a BC instruction list area, a message block description area and a data area; the BC instruction list area is used for storing a plurality of arranged instructions, and each instruction consists of two words: an instruction code and a parameter word; the parameter word matched with the instruction code may be the following four parameters: (1) time value, (2) parameter value of setting or clearing flag bit, (3) certain address pointer value of instruction list, (4) memory pointer value of message block start address; an instruction code comprising: the opcode plus an execution condition code; the message block description area stores the description of each BC message block; the sequencing of the BC message uses an instruction code list, and the starting address of the BC instruction list for controlling the sequencing of the BC message starts from a fixed position; the data area comprises a data word to be sent and a data word to be received, and the sizes of the data sending area and the data receiving area are configured through a configuration register.
The content of the instruction code is shown in table 1:
TABLE 1
The instruction control logic unit is used for realizing the message sequence control of the CPU: when processing CPU message, obtaining and executing instruction code from BC instruction list, the pointer address pointing to the first word in message block, namely BC control word; when the message block is executed, a shared RAM space is separately opened for storing data to be sent or received, and after the execution is finished, the system updates the address pointer of the BC instruction list according to the completion mark of the message;
each instruction code in the BC instruction list is 16 bits: the most significant bit is a parity bit, a 5-bit opcode field, 5 bits are a validation field, and a 5-bit condition code field.
The contents of the 5-bit condition code field are shown in Table 2:
TABLE 2
When the following instruction codes of one or more error conditions are acquired, the IP core immediately stops executing; the instruction code for the error condition includes: bit15 even parity, bit14-10 contains an undefined opcode and a validation field bits 9-5 not equal to 01010.
The instruction control logic unit is also used for scheduling the messages processed by the BC protocol processor based on the BC instruction list;
application example: the message is inserted. This example allows ordering one message to be inserted when a message frame of a schedule is processed by the BC, and inserting the message frame according to a condition at a designated position after a preset message processing is finished. When one or more insert messages have been processed, the previously scheduled message frame will be returned and the list of instructions will continue to be executed where it left off.
TABLE 3
The OPCODE instruction list is stored from 0x2000 fixed address, and an OPCODE instruction word plus a parameter word are arranged and stored. The first instruction unconditional execution message stores values of 0-00001-. By analogy, the inserted message instance organized according to the above summary, the initialized OPCODE instruction list is shown in table 4:
TABLE 4
Four message blocks are initialized, and data required to be initialized by the RAM in the bus controller is shown in table 5 in cooperation with OPCODE verification. The 2100 address begins to store message blocks, one for every five words. The first word control word, command word 0x0821 stored in 0x2101, indicates that BC sends 1 data word to RT1 subaddress 1, non-RT command, the second command word is ignored, the data pointer fetches data from 0000 and sends, the state of talking RT return exists at 0300 address. 55AA is stored in the data word pointer addresses 0000 and 0001 as the data word to be transmitted, and 1111, 2222, 1111, 2222 and 3333 are stored at the 0010 address as the data word to be transmitted.
TABLE 5
After initializing the instruction list, the message block, and the data block, a bc _ start is started to start executing the message. The message blocks in the instruction list are in the order msg1-msg2-msg3-msg 4. The command word data words sent by the bus controller on the A bus are Manchester codes with the sequence of 0821-55AA, 1822-.
The RAM management unit is used for managing and distributing the shared RAM to realize an arbitration function; the CPU can read and write the shared RAM through the AXI slave equipment interface, and the BC protocol processor can also read and write the RAM. In order to prevent read and write conflicts, arbitration is required. Through the VALID/READY handshake mechanism of the AXI bus, if conflicts occur, waiting can be carried out, and the BC protocol processor with high priority can interrupt reading and writing of the CPU.
And the BC protocol processor is used for completing the analysis and processing of the message, realizing the protocol processing of four message formats including BC-to-RT transmission, RT-to-BC transmission, RT-to-RT transmission and broadcasting, and transmitting the processed data word to the encoder.
The decoder is respectively connected with the BC protocol processor and the 1553B transceiver and is used for converting the received Manchester II type code transmitted on the 1553B bus into a unipolar code and transmitting the unipolar code to the 1553B protocol processor for data processing. The module mainly completes the decoding work of the status words and the data words transmitted on the bus.
The encoder is respectively connected with the BC protocol processor and the 1553B transceiver; the device is used for converting the unipolar code into the Manchester code transmitted on the 1553B bus by carrying out Manchester coding on the data to be transmitted, and transmitting the Manchester code to the 1553B bus through the 1553B transceiver. The module mainly completes the coding work of command words and data words.
And the 1553B transceiver is used for receiving the data word and the status word transmitted on the 1553B bus and sending the command word, the data word and the status word output by the BC protocol processor to the 1553B bus. The 1553B transceiver is a HOLT corporation HI-1568 transceiver.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A1553B bus controller protocol processing IP core is arranged between a CPU and a 1553B bus, and is characterized in that the IP core comprises an AXI slave device interface, a register, a shared RAM, an instruction control logic unit, a RAM management unit, a BC protocol processor, an encoder, a decoder and a 1553B transceiver;
the AXI slave equipment interface is used for connecting the IP core to an AMBAAXI bus and enabling the IP core to work as a peripheral of the AXI bus; the CPU is also used for carrying out initialization read-write operation on the register and the shared RAM;
the register is used for writing information through the CPU and configuring the 1553B bus data communication function of the IP core; the BC protocol processor is also used for writing information and recording the working state of the IP core;
the shared RAM is used for storing a BC instruction list, description of a BC message block and various data;
the instruction control logic unit is used for performing message sequence control on the message of the CPU; the BC protocol processor is also used for scheduling the messages processed by the BC protocol processor based on the BC instruction list;
the RAM management unit is used for managing a shared RAM and distributing the shared RAM for the instruction control logic unit and the BC protocol processor;
the BC protocol processor is used for analyzing and processing the received message and sending the processed data word to the encoder;
the decoder is used for decoding the data sent by the 1553B transceiver and sending the data to the BC protocol processor;
the encoder is used for encoding the data sent by the BC protocol processor and sending the data to the 1553B transceiver;
the 1553B transceiver is used for receiving the data words and the state words transmitted on the 1553B bus and forwarding the data words and the state words to the decoder, and is also used for receiving the data output by the decoder and forwarding the data to the 1553B bus.
2. The 1553B bus controller protocol processing IP core of claim 1, wherein the shared RAM comprises a BC instruction list area, a BC message block description area and a data area; the BC instruction list area is used for storing a plurality of arranged instructions, and each instruction consists of two words: an instruction code and a parameter word; an instruction code comprising: an operation code and an execution condition code; the BC message block description area stores the description of each BC message block; the sequencing of the BC message uses an instruction code list, and the starting address of the BC instruction list for controlling the sequencing of the BC message starts from a fixed position; the data area comprises a data word to be sent and a data word to be received, and the sizes of the data sending area and the data receiving area are configured through a configuration register.
3. The 1553B bus controller protocol processing IP core of claim 2, wherein the parameter word matches its instruction code, the parameter word comprising: time value, parameter value to set or clear flag bit, certain address pointer value of instruction list and memory pointer value of message block start address.
4. The 1553B bus controller protocol processing IP core of claim 2, wherein each instruction code is 16 bits: the most significant bit is a parity bit, a 5-bit opcode field, 5 bits are a validation field, and a 5-bit condition code field.
5. The 1553B bus controller protocol processing IP core of claim 4, wherein the instruction control logic unit, when processing the CPU message, fetches and executes an instruction code from a BC instruction list, with a pointer address pointing to the first word in a message block, a BC control word; when the message block is executed, the shared RAM space is opened up separately for storing the data to be sent or received, and after the execution is finished, the BC instruction list address pointer is updated according to the completion mark of the message.
6. The 1553B bus controller protocol processing IP core of claim 5, wherein when the instruction control logic unit obtains the instruction code for the one or more error conditions, the IP core immediately stops executing; the instruction code for the error condition includes: bit15 even parity, bit14-10 contains an undefined opcode and a validation field bits 9-5 not equal to 01010.
7. The 1553B bus controller protocol processing IP core of claim 5, wherein the messages received by the BC protocol processor comprise: BC to RT send messages, RT to BC send messages, RT to RT send messages, and broadcast messages.
8. The 1553B bus controller protocol processing IP core of claim 1, wherein the encoder performs Manchester encoding on data to be transmitted, and converts a unipolar code into a Manchester type II code transmitted on a 1553B bus; the decoder carries out Manchester decoding on data to be transmitted and converts a Manchester II type code transmitted by a 1553B bus into a unipolar code.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116232964A (en) * | 2023-03-07 | 2023-06-06 | 深圳市中航工控半导体有限公司 | Monitoring method for realizing RTMT function in 1553B bus communication network |
| CN117118828A (en) * | 2023-10-23 | 2023-11-24 | 上海芯联芯智能科技有限公司 | Protocol converter, electronic equipment and configuration method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1092584A (en) * | 1992-12-21 | 1994-09-21 | 索尼公司 | The sending method that is used for bidirectional bus system, method of reseptance and communication means and bidirectional bus system |
| EP1883193A2 (en) * | 2006-05-22 | 2008-01-30 | Edgewater Computer Systems, Inc. | Data communication system |
| CN102831096A (en) * | 2012-08-17 | 2012-12-19 | 中国科学院空间科学与应用研究中心 | 1553B bus protocol IP (Intellectual Property) core |
| CN102929836A (en) * | 2012-08-17 | 2013-02-13 | 中国科学院空间科学与应用研究中心 | Special ASIC (Application Specific Integrated Circuit) chip system for spaceflight |
| CN103235769A (en) * | 2013-03-27 | 2013-08-07 | 中国航天科技集团公司第九研究院第七七一研究所 | High speed 1553 bus protocol processor |
| CN103926846A (en) * | 2014-04-25 | 2014-07-16 | 哈尔滨工业大学 | System for simulating aviation ammunition and generating faults |
| CN110659242A (en) * | 2019-09-24 | 2020-01-07 | 中国电子科技集团公司第五十八研究所 | MIL-STD-1553B bus protocol controller |
-
2020
- 2020-08-21 CN CN202010847260.8A patent/CN114077562B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1092584A (en) * | 1992-12-21 | 1994-09-21 | 索尼公司 | The sending method that is used for bidirectional bus system, method of reseptance and communication means and bidirectional bus system |
| EP1883193A2 (en) * | 2006-05-22 | 2008-01-30 | Edgewater Computer Systems, Inc. | Data communication system |
| CN102831096A (en) * | 2012-08-17 | 2012-12-19 | 中国科学院空间科学与应用研究中心 | 1553B bus protocol IP (Intellectual Property) core |
| CN102929836A (en) * | 2012-08-17 | 2013-02-13 | 中国科学院空间科学与应用研究中心 | Special ASIC (Application Specific Integrated Circuit) chip system for spaceflight |
| CN103235769A (en) * | 2013-03-27 | 2013-08-07 | 中国航天科技集团公司第九研究院第七七一研究所 | High speed 1553 bus protocol processor |
| CN103926846A (en) * | 2014-04-25 | 2014-07-16 | 哈尔滨工业大学 | System for simulating aviation ammunition and generating faults |
| CN110659242A (en) * | 2019-09-24 | 2020-01-07 | 中国电子科技集团公司第五十八研究所 | MIL-STD-1553B bus protocol controller |
Non-Patent Citations (1)
| Title |
|---|
| 武瑞欢等: ""基于HOLT芯片的1553B总线通信接口的设计"", 《电脑知识与技术》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116232964A (en) * | 2023-03-07 | 2023-06-06 | 深圳市中航工控半导体有限公司 | Monitoring method for realizing RTMT function in 1553B bus communication network |
| CN116232964B (en) * | 2023-03-07 | 2024-05-03 | 深圳市中航工控半导体有限公司 | Monitoring method for realizing RTMT function in 1553B bus communication network |
| CN117118828A (en) * | 2023-10-23 | 2023-11-24 | 上海芯联芯智能科技有限公司 | Protocol converter, electronic equipment and configuration method |
| CN117118828B (en) * | 2023-10-23 | 2024-01-23 | 上海芯联芯智能科技有限公司 | Protocol converter, electronic equipment and configuration method |
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