CN114077562B - 1553B bus controller protocol processing IP core - Google Patents
1553B bus controller protocol processing IP core Download PDFInfo
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- CN114077562B CN114077562B CN202010847260.8A CN202010847260A CN114077562B CN 114077562 B CN114077562 B CN 114077562B CN 202010847260 A CN202010847260 A CN 202010847260A CN 114077562 B CN114077562 B CN 114077562B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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Abstract
The invention discloses a 1553B bus controller protocol processing IP core, which is arranged between a CPU and a 1553B bus, wherein the IP core comprises an AXI slave device interface, a register, a shared RAM, an instruction control logic unit, a RAM management unit, a BC protocol processor, an encoder, a decoder and a 1553B transceiver; the AXI slave device interface is used for realizing the initialization read-write operation of the CPU on the register and the shared RAM; the register is used for writing information through the CPU and configuring the IP address check 1553B bus data communication function; the method is also used for writing information through the BC protocol processor and recording the working state of the IP core; the shared RAM is used for storing a BC instruction list, a description of a BC message block and various data; the instruction control logic unit is used for controlling the message sequence of the message of the CPU; the method is also used for scheduling messages processed by the BC protocol processor based on the BC instruction list; and the BC protocol processor is used for analyzing and processing the received message and sending the processed data word to the encoder.
Description
Technical Field
The invention relates to the field of data communication, in particular to a 1553B bus controller protocol processing IP core.
Background
The 1553B bus is a time division multiplexed command/response half duplex data bus, the bus structure comprising: a/B buses, which are redundant backups to each other, have three terminal types attached to them: a Bus Controller (BC), a Remote Terminal (RT) and a Bus Monitor (BM). The bus controller plays an initial control role on all information transmission transactions on the bus, the remote terminal completes information transmission between BC and RT, the bus monitor does not participate in communication, and the monitoring function on the message transmission process on the 1553B bus is completed. There may be up to 1 bus controller, 31 remote terminals on the bus, and a bus monitor optional.
At present, internal protocol processing logic of a bus controller in China is relatively backward, the protocol processing is not flexible enough, the participation of a CPU is high, the message is required to be continuously configured on software, and the continuous participation of the CPU can realize the scheduling management of the message flow.
Disclosure of Invention
The invention aims to solve the technical problems of low flexibility of protocol processing and high participation of a CPU in the prior art, thereby providing a 1553B bus controller IP core with high flexibility.
To achieve the above object, the present invention provides a 1553B bus controller protocol processing IP core, disposed between a CPU and a 1553B bus, the IP core including an AXI slave interface, a register, a shared RAM, an instruction control logic unit, a RAM management unit, a BC protocol processor, an encoder, a decoder, and a 1553B transceiver;
The AXI slave device interface is used for connecting the IP core to the AMBAAXI bus so that the IP core works as a peripheral device of the AXI bus; the CPU is also used for initializing read-write operation of the register and the shared RAM;
the register is used for writing information through the CPU and configuring the IP card to realize a 1553B bus data communication function; the method is also used for writing information through the BC protocol processor and recording the working state of the IP core;
The shared RAM is used for storing a BC instruction list, a description of a BC message block and various data;
The instruction control logic unit is used for controlling the message sequence of the message of the CPU; the method is also used for scheduling messages processed by the BC protocol processor based on the BC instruction list;
The RAM management unit is used for managing the shared RAM and distributing the shared RAM for the instruction control logic unit and the BC protocol processor;
The BC protocol processor is used for analyzing and processing the received information and sending the processed data word to the encoder;
The decoder is used for decoding the data sent by the 1553B transceiver and sending the data to the BC protocol processor;
the encoder is used for encoding the data sent by the BC protocol processor and sending the data to the 1553B transceiver;
the 1553B transceiver is used for receiving the data word and the status word transmitted on the 1553B bus, forwarding the data word and the status word to the decoder, and also used for receiving the data output by the decoder and forwarding the data to the 1553B bus.
As an improvement of the above system, the shared RAM includes a BC instruction list area, a BC message block description area, and a data area; the BC instruction list area is used for storing a plurality of arranged instructions, and each instruction consists of two words: an instruction code and a reference number; an instruction code comprising: an operation code and an execution condition code; storing a description of each BC message block in the BC message block description field; the BC message ordering uses an instruction code list, and the BC instruction list starting address for controlling BC message ordering starts from a fixed position; the data area comprises a data word to be transmitted and a data word to be received, and the sizes of the data area to be transmitted and the data area to be received are configured through a configuration register.
As an improvement of the above system, the parameter words are matched with the instruction codes thereof, and the parameter words comprise: a time value, a parameter value of a set or clear flag bit, an address pointer value of an instruction list and a memory pointer value of a message block start address.
As an improvement of the above system, each instruction code is 16 bits: the most significant bits are the parity bits, the 5-bit opcode field, the 5-bit verify field, and the 5-bit condition code field.
As an improvement of the above system, the instruction control logic unit, when processing the CPU message, acquires and executes the instruction code from the BC instruction list, with the pointer address pointing to the first word in the message block, namely the BC control word; when the message block is executed, the data to be sent or received are independently opened up and stored in the shared RAM space, and after the execution is completed, the BC instruction list address pointer is updated according to the completion mark of the message.
As an improvement of the above system, when the instruction control logic unit acquires the instruction codes of one or more error conditions, the IP core immediately stops executing; the instruction code for the error condition includes: bit15 even parity, bit14-10 contains an undefined opcode and verify field bits 9-5 are not equal to 01010.
As an improvement of the above system, the message received by the BC protocol processor includes: BC to RT send message, RT to BC send message, RT to RT send message, and broadcast message.
As an improvement of the above system, the encoder performs manchester encoding on the data to be transmitted, and converts the unipolar code into a manchester ii code transmitted on the 1553B bus; the decoder performs Manchester decoding on data to be sent, and converts Manchester II codes transmitted by the 1553B bus into unipolar codes.
The advantages of this aspect are:
1. The invention adopts Manchester II type biphase coding scheme, thus improving the reliability of the transmission system;
2. The message sequence control scheme provided by the invention adopts an operation code mode to arrange the message sequence, and the functions of originally realizing message scheduling and message arrangement in software are realized in hardware, so that a bus controller can spontaneously arrange message flows, and the message processing is more flexible and intelligent; the processing workload of the CPU is greatly reduced;
3. the IP core has strong portability and can be transplanted into FPGA, ASIC, SOC chips.
Drawings
FIG. 1 is a block diagram of a 1553B bus controller protocol processing IP core of the present invention;
FIG. 2 is a schematic diagram of a shared RAM of the present invention;
FIG. 3 is a diagram of a BC instruction list in accordance with the present invention.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings.
As shown in fig. 1, a 1553B bus controller protocol processing IP core, disposed between a CPU and a 1553B bus, includes an AXI slave interface, a register, a shared RAM, an instruction control logic unit, a RAM management unit, a BC protocol processor, an encoder, a decoder, and a 1553B transceiver;
The AXI slave device interface is connected with the CPU through the AXI and is respectively connected with the shared RAM and the register; the AXI slave device interface is used for connecting the IP core to the AMBAAXI bus, so that the IP core works as a peripheral device of the AXI bus; the CPU is also used for initializing read-write operation of the register and the shared RAM;
The register is used for writing information through the CPU and configuring the IP address check 1553B bus data communication function; the method is also used for writing information through the BC protocol processor and recording the working state of the IP core;
The shared RAM comprises a BC instruction list area, a message block description area and a data area; the BC instruction list area is used for storing a plurality of arranged instructions, and each instruction consists of two words: an instruction code and a reference number; the parameter number is matched with the instruction code, and can be four parameters: (1) a time value, (2) a parameter value of a set or clear flag bit, (3) an address pointer value of an instruction list, (4) a memory pointer value of a message block start address; an instruction code comprising: the operation code is added with the execution condition code; storing a description of each BC message block in the message block description field; the BC message ordering uses an instruction code list, and the BC instruction list starting address for controlling BC message ordering starts from a fixed position; the data area comprises a data word to be transmitted and a data word to be received, and the sizes of the data area to be transmitted and the data area to be received are configured through a configuration register.
The contents of the instruction codes are shown in table 1:
TABLE 1
The instruction control logic unit is used for realizing message sequence control of the CPU: when processing CPU message, acquiring and executing instruction code from BC instruction list, and pointing the pointer address to the first word in message block, namely BC control word; when the message block is executed, the data to be sent or received are independently opened up to be stored in a shared RAM space, and after the execution is completed, the system can update the BC instruction list address pointer according to the completion mark of the message;
Each instruction code in the BC instruction list is 16 bits: the most significant bits are the parity bits, the 5-bit opcode field, the 5-bit verify field, and the 5-bit condition code field.
The contents of the 5-bit condition code field are shown in table 2:
TABLE 2
When the instruction code of the following one or more error conditions is acquired, the IP core immediately stops executing; the instruction code for the error condition includes: bit15 even parity, bit14-10 contains an undefined opcode and verify field bits 9-5 are not equal to 01010.
The instruction control logic unit is also used for scheduling messages processed by the BC protocol processor based on the BC instruction list;
Application example: a message is inserted. This example allows ordering a message to be inserted when BC processes the planned message frame, inserting the message frame at a specified location according to the conditions after the end of the preset message processing. After processing one or more insert messages, the previously scheduled message frame will be returned and the instruction list will continue to be executed where it left off.
TABLE 3 Table 3
The OPCODE instruction list is stored starting from a fixed address of 0x2000, one OPCODE instruction word plus one parameter word arrangement. The first instruction unconditional execution message has a value of 0-00001-01010-01111, i.e., 054F. And similarly, initializing an OPCODE instruction list according to the inserted message example arranged by the upper section, and the list is shown in table 4:
TABLE 4 Table 4
Four message blocks are initialized, and data to be initialized of the RAM in the bus controller are shown in table 5 in cooperation with OPCODE verification. The 2100 address begins to store message blocks, with each five words representing a message block. The first word control word, 0x0821, stored in 0x2101, indicates that BC sends 1 data word to RT1 sub-address 1, not RT-RT command, the second command word ignores, data pointer fetches data from 0000 to send, and state of RT return exists at 0300 address. 55AA is stored as the data word to be transmitted in the data word pointer addresses 0000 and 0001, and 1111, 2222, 3333 are stored as the data word to be transmitted beginning at address 0010.
TABLE 5
After initializing the instruction list, the message block and the data block, the bc_start is started to start executing the message. The order of message blocks in the instruction list is msg1-msg2-msg3-msg4. The command word data words sent by the bus controller on the A bus are Manchester codes, the sequences are 0821-55AA,1822-1111-2222, 3823-1111-2222-3333, 0821-55AA, the corresponding message block sequences are MSG1-MSG4-MSG2-MSG3, and two messages MSG3 and MSG4 are inserted between MSG1 and MSG 2.
The RAM management unit is used for managing and distributing the shared RAM to realize an arbitration function; the CPU can read and write the shared RAM through the AXI slave device interface, and the BC protocol processor can also read and write the RAM. In order to prevent the read-write collision, arbitration is needed. Through the VALID/READY handshake mechanism of the AXI bus, the BC protocol processor can wait if collision occurs, and the BC protocol processor has high priority and can interrupt the CPU read-write.
And the BC protocol processor is used for completing analysis and processing of the message, realizing protocol processing of four message formats, namely BC to RT transmission, RT to BC transmission, RT to RT transmission and broadcasting, and transmitting the processed data word to the encoder.
The decoder is respectively connected with the BC protocol processor and the 1553B transceiver and is used for converting the Manchester II type code transmitted on the received 1553B bus into a unipolar code and transmitting the unipolar code to the 1553B protocol processor for data processing. The module mainly completes decoding work of status words and data words transmitted on a bus.
The encoder is respectively connected with the BC protocol processor and the 1553B transceiver; the data to be transmitted is Manchester encoded to convert the unipolar code into Manchester code for transmission over the 1553B bus, and transmitted over the 1553B bus via the 1553B transceiver. The module mainly completes the coding work of command words and data words.
And the 1553B transceiver is used for receiving the data word and the status word transmitted on the 1553B bus and sending the command word, the data word and the status word output by the BC protocol processor to the 1553B bus. The 1553B transceiver uses HOLT company HI-1568 transceiver.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and are not limiting. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the appended claims.
Claims (7)
1. A 1553B bus controller protocol processing IP core arranged between a CPU and a 1553B bus, wherein the IP core comprises an AXI slave interface, a register, a shared RAM, an instruction control logic unit, a RAM management unit, a BC protocol processor, an encoder, a decoder and a 1553B transceiver;
The AXI slave device interface is used for connecting the IP core to the AMBAAXI bus so that the IP core works as a peripheral device of the AXI bus; the CPU is also used for initializing read-write operation of the register and the shared RAM;
the register is used for writing information through the CPU and configuring the IP card to realize a 1553B bus data communication function; the method is also used for writing information through the BC protocol processor and recording the working state of the IP core;
The shared RAM is used for storing a BC instruction list, a description of a BC message block and various data;
The instruction control logic unit is used for controlling the message sequence of the message of the CPU; the method is also used for scheduling messages processed by the BC protocol processor based on the BC instruction list;
The RAM management unit is used for managing the shared RAM and distributing the shared RAM for the instruction control logic unit and the BC protocol processor;
The BC protocol processor is used for analyzing and processing the received information and sending the processed data word to the encoder;
The decoder is used for decoding the data sent by the 1553B transceiver and sending the data to the BC protocol processor;
the encoder is used for encoding the data sent by the BC protocol processor and sending the data to the 1553B transceiver;
The 1553B transceiver is used for receiving the data word and the status word transmitted on the 1553B bus, forwarding the data word and the status word to the decoder, and receiving the data output by the decoder and forwarding the data to the 1553B bus;
The shared RAM comprises a BC instruction list area, a BC message block description area and a data area; the BC instruction list area is used for storing a plurality of arranged instructions, and each instruction consists of two words: an instruction code and a reference number; an instruction code comprising: an operation code and an execution condition code; storing a description of each BC message block in the BC message block description field; the BC message ordering uses an instruction code list, and the BC instruction list starting address for controlling BC message ordering starts from a fixed position; the data area comprises a data word to be transmitted and a data word to be received, and the sizes of the data area to be transmitted and the data area to be received are configured through a configuration register.
2. The 1553B bus controller protocol processing IP core of claim 1, wherein the parameter word matches its instruction code, the parameter word comprising: a time value, a parameter value of a set or clear flag bit, an address pointer value of an instruction list and a memory pointer value of a message block start address.
3. The 1553B bus controller protocol processing IP core of claim 1, wherein each instruction code is 16 bits: the most significant bits are the parity bits, the 5-bit opcode field, the 5-bit verify field, and the 5-bit condition code field.
4. The 1553B bus controller protocol processing IP core of claim 3, wherein said instruction control logic unit, when processing a CPU message, retrieves and executes an instruction code from a BC instruction list, the pointer address pointing to a first word in a message block, namely a BC control word; when the message block is executed, the data to be sent or received are independently opened up and stored in the shared RAM space, and after the execution is completed, the BC instruction list address pointer is updated according to the completion mark of the message.
5. The 1553B bus controller protocol processing IP core of claim 4, wherein when the instruction control logic unit obtains an instruction code for one or more error conditions, the IP core immediately stops executing; the instruction code for the error condition includes: bit15 even parity, bit14-10 contains an undefined opcode and verify field bits 9-5 are not equal to 01010.
6. The 1553B bus controller protocol processing IP core of claim 4, wherein the message received by the BC protocol processor comprises: BC to RT send message, RT to BC send message, RT to RT send message, and broadcast message.
7. The 1553B bus controller protocol processing IP core of claim 1, wherein said encoder manchester encodes the data to be transmitted to convert a unipolar code to a manchester ii code for transmission on the 1553B bus; the decoder performs Manchester decoding on data to be sent, and converts Manchester II codes transmitted by the 1553B bus into unipolar codes.
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