CN114071856A - Three-dimensional circuit board and preparation method thereof - Google Patents
Three-dimensional circuit board and preparation method thereof Download PDFInfo
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- CN114071856A CN114071856A CN202010760072.1A CN202010760072A CN114071856A CN 114071856 A CN114071856 A CN 114071856A CN 202010760072 A CN202010760072 A CN 202010760072A CN 114071856 A CN114071856 A CN 114071856A
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 16
- 238000003825 pressing Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000003475 lamination Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 258
- 229910000679 solder Inorganic materials 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 239000004642 Polyimide Substances 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000003365 glass fiber Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 239000005020 polyethylene terephthalate Substances 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011112 polyethylene naphthalate Substances 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000861 Mg alloy Inorganic materials 0.000 description 1
- 229910001297 Zn alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention provides a three-dimensional circuit board which comprises a second circuit board, a second insulating layer, a first circuit board, a first insulating layer and a conducting layer. The second insulating layer, the first circuit board and the first insulating layer are sequentially stacked and arranged on one side of the second circuit board. The first circuit board is provided with a first through hole, and the first insulating layer is filled in the first through hole and connected with the second insulating layer. The first insulating layer is provided with a groove corresponding to the first through hole, and the groove extends to the second insulating layer. The conductive layer comprises a first circuit pattern which is embedded in at least one of the first insulating layer and the second insulating layer and is exposed out of the groove. The invention also provides a preparation method of the three-dimensional circuit board.
Description
Technical Field
The invention relates to the field of circuit boards, in particular to a three-dimensional circuit board and a preparation method thereof.
Background
In recent years, electronic products are widely used in daily work and life, and demands for miniaturization, multi-functionalization, and high performance are increasing. The circuit board is a main component of the electronic product, and occupies a large space of the electronic product, so the volume of the circuit board greatly affects the volume of the electronic product. The mounting surface of the existing circuit board is usually positioned on the front surface or the back surface of the circuit board, so that the circuit board is difficult to realize miniaturization; and some products need to mount electronic components on the side of the circuit board or even buried in the circuit board, however, the circuit board cannot meet the requirement.
Disclosure of Invention
In view of the above, it is desirable to provide a three-dimensional circuit board and a method for manufacturing the same.
One embodiment of the present invention provides a three-dimensional circuit board, which includes a second circuit board, a second insulating layer, a first circuit board, a first insulating layer, and a conductive layer. The second insulating layer, the first circuit board and the first insulating layer are sequentially stacked and arranged on one side of the second circuit board. The first circuit board is provided with a first through hole, and the first insulating layer is filled in the first through hole and connected with the second insulating layer. The first insulating layer is provided with a groove corresponding to the first through hole, and the groove extends to the second insulating layer. The conductive layer comprises a first circuit pattern which is embedded in at least one of the first insulating layer and the second insulating layer and is exposed out of the groove.
Further, the groove includes a bottom wall and a side wall disposed around the bottom wall, and the first line pattern is located on the bottom wall and the side wall.
Further, the conductive layer further comprises a second circuit pattern, and the second circuit pattern is embedded in the first insulating layer and exposed from one side, away from the first circuit board, of the first insulating layer.
Further, the three-dimensional circuit board further comprises an electronic element disposed on the conductive layer and embedded in at least one of the first insulating layer and the second insulating layer.
Further, the three-dimensional circuit board further comprises a shielding layer, and the shielding layer is arranged on at least one side wall of the groove.
An embodiment of the present invention provides a method for manufacturing a three-dimensional circuit board, including: providing a die, wherein the die comprises a plate body part and a protruding part protruding and formed on one side of the plate body part; forming a conductive layer on the mold, the conductive layer including a first line pattern on the protruding portion and a second line pattern on the plate body portion; providing a first circuit board, a second circuit board, a first insulating layer and a second insulating layer, wherein the first circuit board is provided with a first through hole corresponding to the protruding portion, and the first insulating layer is provided with a second through hole corresponding to the protruding portion; stacking the second insulating layer, the first circuit board, the first insulating layer and the mold on one side of the second circuit board in sequence and pressing, wherein the protruding part penetrates through the second through hole and the first through hole in sequence and is abutted against the second insulating layer during stacking, after pressing, the first insulating layer and the second insulating layer are connected and cover one side of the mold together, the first circuit pattern is embedded in at least one of the first insulating layer and the second insulating layer, and the second circuit pattern is embedded in the first insulating layer; and removing the mold to expose the first circuit pattern from the groove formed after the protruding part is removed and expose the second circuit pattern from one side of the first insulating layer, which is far away from the first circuit board, so as to obtain the three-dimensional circuit board.
Further, before forming the conductive layer on the mold, the method further comprises the following steps: forming a metal layer on the mold, the conductive layer being formed on the metal layer.
Further, before forming the metal layer on the mold, the method further comprises the following steps: and forming a release layer on the mold, wherein the metal layer covers one side of the release layer, which deviates from the mold.
Further, the groove includes a bottom wall and a side wall disposed around the bottom wall, and the first line pattern is located on the bottom wall and the side wall.
Further, the method also comprises the following steps after the conducting layer is formed on the mould: and arranging an electronic element on the conductive layer, and embedding the electronic element into at least one of the first insulating layer and the second insulating layer after lamination.
Further, forming a conductive layer on the mold includes the steps of: and forming a shielding layer on at least one side surface of the protruding part, wherein the shielding layer is positioned on at least one side wall of the groove after pressing.
According to the three-dimensional circuit board and the preparation method thereof provided by the embodiment of the invention, the conducting layer is formed on the die, and the formed conducting layer is directly laminated on the first insulating layer and the second insulating layer after lamination to prepare the three-dimensional circuit board, so that the preparation process is simplified. In addition, the first circuit pattern is formed on the side wall and the bottom wall of the groove, so that the first circuit pattern is embedded in the three-dimensional circuit board, and size miniaturization is facilitated; and the electronic element can be directly arranged on the side wall and the bottom wall of the groove, so that the three-dimensional installation requirement of the electronic element is met.
Drawings
Fig. 1 is a schematic structural diagram of a mold according to an embodiment of the present invention.
Fig. 2 is a schematic view of a structure after a conductive layer is formed on the mold shown in fig. 1.
Fig. 3 is a schematic structural diagram of a first circuit board, a second circuit board, a first insulating layer, and a second insulating layer according to an embodiment of the present invention.
Fig. 4 is a schematic view of the structure shown in fig. 2 and the structure shown in fig. 3 pressed together.
Fig. 5 is a schematic view of the structure of fig. 4 with the mold removed.
Fig. 6 is a schematic view of the structure shown in fig. 5 after a solder mask layer is formed thereon.
Fig. 7 is a mold in which a shielding layer and an electronic component are formed according to another embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a three-dimensional circuit board according to another embodiment of the present invention.
Description of the main elements
Projecting part 13
First insulating layer 50
Second insulating layer 60
First through hole 31
Second through hole 52
Insulating layers 36, 44
Three-dimensional circuit board 100
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
An embodiment of the present invention provides a method for manufacturing a three-dimensional circuit board, including the steps of:
s1, providing a mold including a plate body and a protrusion formed at one side of the plate body;
s2, forming a conductive layer on the mold, the conductive layer including a first wiring pattern on the protruding portion and a second wiring pattern on the plate body portion;
s3, providing a first circuit board, a second circuit board, a first insulating layer and a second insulating layer, wherein the first circuit board is provided with a first through hole corresponding to the protruding portion, and the first insulating layer is provided with a second through hole corresponding to the protruding portion;
s4, stacking the second insulating layer, the first circuit board, the first insulating layer and the mold on one side of the second circuit board in sequence and pressing, wherein the protruding portion penetrates through the second through hole and the first through hole in sequence and abuts against the second insulating layer when the second insulating layer, after pressing, the first insulating layer and the second insulating layer are connected and cover one side of the mold together, the first circuit pattern is embedded in at least one of the first insulating layer and the second insulating layer, and the second circuit pattern is embedded in the first insulating layer;
and S5, removing the die to expose the first circuit pattern from the groove formed after the protrusion part is removed and expose the second circuit pattern from the side of the first insulating layer, which is far away from the first circuit board, so as to obtain the three-dimensional circuit board.
Referring to fig. 1, in step S1, a mold 10 is provided, where the mold 10 includes a plate portion 11 and a protrusion 13 protruding from one side of the plate portion 11.
The plate body 11 includes a first surface 111 and a second surface 113 which are oppositely arranged, and the protrusion 13 is formed to protrude from the second surface 113. The protrusion 13 includes a side surface 131 connected to the second surface 113 and a top surface 133 disposed away from the second surface 113.
The material of the mold 10 is an alloy, and the alloy is selected from one or more of stainless steel, aluminum alloy, copper alloy, zinc alloy and magnesium alloy.
Further, the following steps are also included after step S1: a release layer 12 and a metal layer 14 are sequentially formed on the mold 10. The release layer 12 has elasticity, and can protect the circuit board when the subsequent die 10 and the circuit board are pressed; and which facilitates subsequent removal of the mold 10. The metal layer 14 may be used for subsequent formation of a conductive layer. The release layer 12 and the metal layer 14 may be formed on the mold 10 by attaching or coating. The release layer 12 completely covers the second surface 113 of the board part 11 and the top surface 133 and the side surface 131 of the protrusion 13. The metal layer 14 completely covers the side of the release layer 12 facing away from the mold 10.
Referring to fig. 2, in step S2, a conductive layer 20 is formed on the mold 10, and the conductive layer 20 includes a first circuit pattern 22 on the protrusion 13 and a second circuit pattern 24 on the board portion 11.
In this embodiment, a plurality of second line patterns 24 are formed on the plate body portion 11, and the plurality of second line patterns 24 are distributed on the second surface 113 at intervals; a plurality of first circuit patterns 22 are formed on the protruding portion 13, and the plurality of first circuit patterns 22 are distributed on the side surface 131 and the top surface 133 at intervals.
The conductive layer 20 is made of copper, and can be formed by exposure and development, copper plating, stripping and other processes in the conventional technology.
In this embodiment, the conductive layer 20 is formed on the metal layer 14.
Referring to fig. 3, in step S3, a first circuit board 30, a second circuit board 40, a first insulating layer 50 and a second insulating layer 60 are provided, the first circuit board 30 is provided with a first through hole 31 corresponding to the protrusion 13, and the first insulating layer 50 is provided with a second through hole 52 corresponding to the protrusion 13.
The first circuit board 30 may be a single-layer board structure or a multi-layer board structure, and it may be a flexible board, a rigid board, or a rigid-flexible board. In the present embodiment, the first wiring board 30 is a hard board, and includes two conductive layers 34 and an insulating layer 36 interposed between the two conductive layers 34. The insulating layer 36 is made of Prepreg (prepeg, PP) containing glass fiber and epoxy resin. Alternatively, the number of the conductive layers 34 and the insulating layers 36 in the first circuit board 30 may be set according to actual requirements.
The first via 31 penetrates the insulating layer 36 and the two conductive layers 34. The first through hole 31 corresponds to the protrusion 13, which allows the protrusion 13 to pass through. The first through hole 31 may be formed by a punching method. In the present embodiment, the size of the first through hole 31 is larger than the size of the protrusion 13.
The first wiring board 30 further comprises a conductive structure 35 for electrically connecting the two conductive layers 34. Specifically, the conductive structure 35 penetrates two conductive layers 34 and the insulating layer 36, and electrically connects the two conductive layers 34.
The second circuit board 40 may be a single-layer board structure or a multi-layer board structure, and it may be a flexible board, a rigid board, or a rigid-flexible board. In the present embodiment, the second circuit board 40 is a flexible board, and includes two conductive layers 42 and an insulating layer 44 sandwiched between the two conductive layers 42. The insulating layer 44 is made of Polyimide (PI). Alternatively, the number of the conductive layers 42 and the insulating layers 44 in the second circuit board 40 may be set according to actual requirements.
The second through-hole 52 may be formed by a punching process, and has a size matched with that of the protrusion 13. In the present embodiment, the size of the second through hole 52 is the same as the size of the protrusion 13.
The first insulating layer 50 and the second insulating layer 60 may be made of one of Prepreg (prep, PP) containing glass fiber and epoxy resin, Polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). The material of the first insulating layer 50 and the material of the second insulating layer 60 may be the same or different. In this embodiment, the material of the first insulating layer 50 and the material of the second insulating layer 60 are both PP.
Referring to fig. 4, in step S4, the second insulating layer 60, the first circuit board 30, the first insulating layer 50 and the mold 10 are sequentially stacked on one side of the second circuit board 40 and pressed, when stacked, the protruding portion 13 sequentially passes through the second through hole 52 and the first through hole 31 and abuts against the second insulating layer 60, after pressing, the first insulating layer 50 and the second insulating layer 60 are connected and cover one side of the mold 10 together, the first circuit pattern 22 is embedded in at least one of the first insulating layer 50 and the second insulating layer 60, and the second circuit pattern 24 is embedded in the first insulating layer 50.
Specifically, when stacked, the second insulating layer 60 covers a side of the second circuit board 40, which is away from the insulating layer 44, of the conductive layer 42, the first circuit board 30 covers a side of the second insulating layer 60, which is away from the second circuit board 40, of the conductive layer 34, the first insulating layer 50 covers a side of the first circuit board 30, which is away from the insulating layer 36, of the other conductive layer 34, and the mold 10 covers a side of the first insulating layer 50, which is away from the first circuit board 30. Wherein the protruding portion 13 is received in the second through hole 52 and the first through hole 31, the first circuit pattern 22 disposed on the side surface 131 is located between the side walls of the first through hole 31 and the second through hole 52 and the side surface 131, and the first circuit pattern 22 disposed on the top surface 133 is located between the second insulating layer 60 and the top surface 133; the second line pattern 24 is located between the plate portion 11 and the first insulating layer 50.
In this embodiment, a hot pressing method is used for the pressing. When the first insulating layer 50 and the second insulating layer 60 are fused, the second wiring patterns 24 on the board portion 11 are directly embedded into the fused first insulating layer 50, and the first wiring patterns 22 on the top surfaces 133 of the protrusions 13 are directly embedded into the fused second insulating layer 60; and the melted portion of the first insulating layer 50 is filled into the first through hole 31, connected to the second insulating layer 60, and fills the gap between the sidewall of the first through hole 31 and the protrusion 13, so that the first line pattern 22 on the side 131 of the protrusion 13 is embedded in the first insulating layer 50.
After pressing, the first insulating layer 50 and the second insulating layer 60 are connected and together cover the side of the mold 10 where the protruding portion 13 is located. The first insulating layer 50 includes a first portion (not shown) on the first wiring board 30 and a second portion (not shown) filled in the second through hole 52 and connected to the second insulating layer 60. The second line pattern 24 is embedded in the first portion, the first line pattern 22 on the side surface 131 is embedded in the second portion, and the first line pattern 22 on the top surface 133 is embedded in the second insulating layer 60.
Referring to fig. 4 and 5, in step S5, the mold 10 is removed, the first circuit pattern 22 is exposed from the groove 53 formed after the protrusion 13 is removed, and the second circuit pattern 24 is exposed from the side of the first insulating layer 50 away from the first circuit board 30, so as to obtain the three-dimensional circuit board 100.
After the protruding portion 13 of the mold 10 is removed, a groove 53 surrounded by the first insulating layer 50 and the second insulating layer 60 is formed. The groove 53 is disposed corresponding to the first through hole 31. The groove 53 includes a bottom wall 533 and a side wall 531 disposed around the bottom wall 533. The side walls 531 correspond to the side surfaces 131 of the protrusion 13, so that the first wiring pattern 22 on the side surfaces 131 of the protrusion 13 is press-fitted on the side walls 531 of the groove 53. The bottom wall 533 corresponds to the top surface 133 of the protrusion 13, so that the first circuit pattern 22 on the top surface 133 of the protrusion 13 is press-fit on the bottom wall 533 of the groove 53. In this embodiment, the bottom wall 533 of the groove 53 is formed by the second insulating layer 60, and the sidewall 531 of the groove 53 is formed by the second insulating layer 60 and the first insulating layer 50.
After the plate body portion 11 of the mold 10 is removed, the second circuit pattern 24 is exposed from a side of the first insulating layer 50 facing away from the first wiring board 30. The side of the first insulating layer 50 facing away from the first wiring board 30 serves as the front or back side of the three-dimensional circuit board 100.
Both the first line pattern 22 and the second line pattern 24 may be used to mount electronic components such as resistors, capacitors, inductors, and the like.
When electronic components are mounted on the first circuit patterns 22, the electronic components are received in the grooves 53, that is, the electronic components are embedded in the three-dimensional circuit board 100, so that the three-dimensional circuit board 100 can be miniaturized. In addition, since the first circuit pattern 22 can be disposed on the sidewall 531 of the groove 53, it can meet the requirement of mounting electronic components on the side of the circuit board.
When the electronic component is mounted on the second circuit pattern 24, the electronic component is located on the front side or the back side of the three-dimensional circuit board 100, that is, the second circuit pattern 24 can meet the requirement of mounting the electronic component on the front side or the back side of the circuit board.
Step S5 specifically includes the following steps: the release layer 12 is torn off to remove the mold 10, the metal layer 14 is removed to expose the first circuit pattern 22 from the groove 53, and the second circuit pattern 24 is exposed from the side of the first insulating layer 50 away from the first circuit board 30, so as to obtain the three-dimensional circuit board 100. The metal layer 14 may be removed using an etching process.
Referring to fig. 6, after removing the mold 10, the method further includes the following steps: a solder mask layer 70 is formed on the first insulating layer 50. The solder mask layer 70 covers a side of the first insulating layer 50 away from the first circuit board 30, and the second circuit pattern 24 is exposed outside the solder mask layer 70 (alternatively, the first circuit pattern 22 on the side 131 of the protrusion 13 can be selectively covered by spraying). The solder mask layer 70 may be formed by printing or spraying an insulating ink.
Referring to fig. 7, in some embodiments, a shielding layer 80 may also be formed on the mold 10 when the conductive layer 20 is formed in step S2. The shielding layer 80 is made of metal for shielding external interference electromagnetic signals. In this embodiment, the shielding layer 80 is located on at least one side 131 of the protrusion 13, and the plurality of first line patterns 22 are located on the other side 131 and the top 133 of the protrusion 13. It is understood that the shielding layer 80 may completely or partially cover the side 131 of the protrusion 13. In this embodiment, the shielding layer 80 completely covers the side 131 of the protrusion 13.
Referring to fig. 7, after step S2, the method further includes the following steps: an electronic component 90 is mounted on the conductive layer 20. The electronic component 90 may be mounted on the conductive layer 20 by a surface mounting technique. The electronic component 90 may be a capacitor, a resistor, an inductor, or the like. In this embodiment, a part of the electronic components 90 is mounted on the first circuit pattern 22, and a part of the electronic components 90 is mounted on the second circuit pattern 24.
Referring to fig. 8, after the pressing, the shielding layer 80 is pressed on at least one sidewall 531 of the groove 53, and the first circuit pattern 22 on the other side 131 of the protrusion 13 is pressed on the other sidewall 531 of the groove 53. In this embodiment, the shielding layer 80 completely covers at least one sidewall 531 of the groove 53.
Referring to fig. 8, after lamination, the electronic component 90 is embedded in at least one of the first insulating layer 50 and the second insulating layer 60. In this embodiment, after the lamination, the electronic component 90 mounted on the second circuit pattern 24 is completely embedded in the first insulating layer 50, and the electronic component mounted on the first circuit pattern 22 is completely embedded in the second insulating layer 60.
In the preparation method of the three-dimensional circuit board 100 provided by the embodiment of the invention, the conductive layer 20 is formed on the mold 10, and after the lamination, the formed conductive layer 20 is directly laminated on the first insulating layer 50 and the second insulating layer 60 to prepare the three-dimensional circuit board 100, so that the preparation process is simplified. In addition, the first line pattern 22 is formed on the side wall 531 and the bottom wall 533 of the groove 53, so that the first line pattern 22 is buried in the three-dimensional circuit board 100, which is advantageous for size miniaturization; and the electronic components can be directly mounted on the side walls 531 and the bottom wall 533 of the groove 53, so as to meet the requirement of three-dimensional mounting of the electronic components.
Referring to fig. 6, an embodiment of the invention provides a three-dimensional circuit board 100, which includes a second circuit board 40, a second insulating layer 60, a first circuit board 30, a first insulating layer 50 and a conductive layer 20, the second insulating layer 60, the first wiring board 30 and the first insulating layer 50 are sequentially stacked on one side of the second wiring board 40, the first circuit board 30 is provided with a first through hole 31, the first insulating layer 50 is filled in the first through hole 31 and connected with the second insulating layer 60, a groove 53 is formed in the first insulating layer 50 corresponding to the first through hole 31, the groove 53 extends to the second insulating layer 60, the conductive layer 20 includes a first line pattern 22, and the first line pattern 22 is embedded in at least one of the first insulating layer 50 and the second insulating layer 60 and exposed from the groove 53.
The groove 53 includes a bottom wall 533 and a sidewall 531 disposed around the bottom wall 533, in this embodiment, the bottom wall 533 of the groove 53 is formed by the second insulating layer 60, and the sidewall 531 of the groove 53 is formed by the second insulating layer 60 and the first insulating layer 50. The first line pattern 22 is located on at least one of the bottom wall 533 and the side wall 531. In this embodiment, the first circuit patterns 22 are plural, and the plural first circuit patterns 22 are distributed on the bottom wall 533 and the side wall 531 of the groove 53 at intervals.
When electronic components (e.g., resistors, capacitors, inductors, etc.) are mounted on the first circuit patterns 22, the electronic components are received in the grooves 53, i.e., the electronic components are embedded in the three-dimensional circuit board 100, so that the three-dimensional circuit board 100 can be miniaturized. In addition, since the first circuit pattern 22 can be disposed on the sidewall 531 of the groove 53, it can meet the requirement of mounting electronic components on the side of the circuit board.
The conductive layer 20 further includes a second line pattern 24. The second circuit pattern 24 is embedded in the first insulating layer 50 and exposed from a side of the first insulating layer 50 facing away from the first wiring board 30. In this embodiment, the second circuit patterns 24 are a plurality of second circuit patterns 24, and the second circuit patterns 24 are distributed at intervals on a side of the first insulating layer 50 away from the first circuit board 30. The side of the first insulating layer 50 facing away from the first circuit board 30 serves as the front or back surface of the three-dimensional circuit board 100, and the second circuit patterns 24 can meet the requirement of mounting electronic components on the front or back surface of the circuit board.
The first circuit board 30 may be a single-layer board structure or a multi-layer board structure, and it may be a flexible board, a rigid board, or a rigid-flexible board. In the present embodiment, the first wiring board 30 is a hard board, and includes two conductive layers 34 and an insulating layer 36 interposed between the two conductive layers 34. The insulating layer 36 is made of Prepreg (prepeg, PP) containing glass fiber and epoxy resin. Alternatively, the number of the conductive layers 34 and the insulating layers 36 in the first circuit board 30 may be set according to actual requirements. The first via 31 penetrates the insulating layer 36 and the two conductive layers 34.
The first wiring board 30 further comprises a conductive structure 35 for electrically connecting the two conductive layers 34. Specifically, the conductive structure 35 penetrates two conductive layers 34 and the insulating layer 36, and electrically connects the two conductive layers 34.
The second circuit board 40 may be a single-layer board structure or a multi-layer board structure, and it may be a flexible board, a rigid board, or a rigid-flexible board. In the present embodiment, the second circuit board 40 is a flexible board, and includes two conductive layers 42 and an insulating layer 44 sandwiched between the two conductive layers 42. The insulating layer 44 is made of Polyimide (PI). Alternatively, the number of the conductive layers 42 and the insulating layers 44 in the second circuit board 40 may be set according to actual requirements.
The first insulating layer 50 is sandwiched between the conductive layer 20 and one conductive layer 34 of the first wiring board 30. The second insulating layer 60 is interposed between the other conductive layer 34 of the first wiring board 30 and the one conductive layer 42 of the second wiring board 40.
The first insulating layer 50 and the second insulating layer 60 may be made of one of Prepreg (preg, PP) containing glass fiber and epoxy resin, Polyimide (PI), Polyethylene Terephthalate (PET), and Polyethylene Naphthalate (PEN). The material of the first insulating layer 50 and the material of the second insulating layer 60 may be the same or different. In this embodiment, the material of the first insulating layer 50 and the material of the second insulating layer 60 are both PP.
The three-dimensional circuit board 100 further includes a solder mask layer 70. The solder mask layer 70 covers a side of the first insulating layer 50 away from the first circuit board 30, and the second circuit pattern 24 is exposed outside the solder mask layer 70. The solder mask 70 may be formed by printing using an insulating ink.
Referring to fig. 8, in some embodiments, the three-dimensional circuit board 100 further includes a shielding layer 80 and an electronic component 90. The shielding layer 80 is disposed on at least one sidewall 531 of the groove 53. In this embodiment, the shielding layer 80 completely covers at least one sidewall 531 of the groove 53. The shielding layer 80 is made of metal for shielding external interference electromagnetic signals.
The electronic element 90 is disposed on the conductive layer 20 and is completely embedded in at least one of the first insulating layer 50 and the second insulating layer 60. The electronic component 90 may be mounted on the conductive layer 20 by a surface mounting technique. The electronic component 90 may be a capacitor, a resistor, an inductor, or the like. In the present embodiment, a part of the electronic component 90 is mounted on the second circuit pattern 24 and embedded in the first insulating layer 50; a part of the electronic component 90 is mounted on the first circuit pattern 22 and embedded in the second insulating layer 60.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention.
Claims (10)
1. The utility model provides a three-dimensional circuit board, its characterized in that includes second circuit board, second insulating layer, first circuit board, first insulating layer and conducting layer, the second insulating layer first circuit board with first insulating layer stacks gradually and sets up one side of second circuit board, first through-hole has been seted up to first circuit board, first insulating layer fill in the first through-hole and with the second insulating layer is connected, first insulating layer corresponds first through-hole department sets up flutedly, the recess extends to the second insulating layer, the conducting layer includes first circuit pattern, first circuit pattern inlays to be located in the first insulating layer with in at least one of the second insulating layer and follow the recess exposes.
2. The three-dimensional circuit board of claim 1, wherein the recess includes a bottom wall and a side wall disposed around the bottom wall, the first wiring pattern being located on the bottom wall and the side wall.
3. The three-dimensional circuit board according to claim 1, wherein the conductive layer further comprises a second wiring pattern embedded in the first insulating layer and exposed from a side of the first insulating layer facing away from the first wiring board.
4. The three-dimensional circuit board of claim 1, further comprising an electronic component disposed on the conductive layer and embedded in at least one of the first insulating layer and the second insulating layer.
5. The three-dimensional circuit board of claim 1, further comprising a shielding layer disposed on at least one sidewall of the recess.
6. A method for preparing a three-dimensional circuit board comprises the following steps:
providing a die, wherein the die comprises a plate body part and a protruding part protruding and formed on one side of the plate body part;
forming a conductive layer on the mold, the conductive layer including a first line pattern on the protruding portion and a second line pattern on the plate body portion;
providing a first circuit board, a second circuit board, a first insulating layer and a second insulating layer, wherein the first circuit board is provided with a first through hole corresponding to the protruding portion, and the first insulating layer is provided with a second through hole corresponding to the protruding portion;
stacking the second insulating layer, the first circuit board, the first insulating layer and the mold on one side of the second circuit board in sequence and pressing, wherein the protruding part penetrates through the second through hole and the first through hole in sequence and is abutted against the second insulating layer during stacking, after pressing, the first insulating layer and the second insulating layer are connected and cover one side of the mold together, the first circuit pattern is embedded in at least one of the first insulating layer and the second insulating layer, and the second circuit pattern is embedded in the first insulating layer;
and removing the mold to expose the first circuit pattern from the groove formed after the protruding part is removed and expose the second circuit pattern from one side of the first insulating layer, which is far away from the first circuit board, so as to obtain the three-dimensional circuit board.
7. The method of manufacturing a three-dimensional circuit board according to claim 6, further comprising, before forming the conductive layer on the mold, the steps of: forming a metal layer on the mold, the conductive layer being formed on the metal layer.
8. The method of manufacturing a three-dimensional circuit board according to claim 7, further comprising, before forming the metal layer on the mold, the steps of: and forming a release layer on the mold, wherein the metal layer covers one side of the release layer, which deviates from the mold.
9. The method of manufacturing a three-dimensional circuit board according to claim 7, further comprising the step of, after forming the conductive layer on the mold: and arranging an electronic element on the conductive layer, and embedding the electronic element into at least one of the first insulating layer and the second insulating layer after lamination.
10. The method of manufacturing a three-dimensional circuit board according to claim 7, wherein forming a conductive layer on the mold comprises the steps of: and forming a shielding layer on at least one side surface of the protruding part, wherein the shielding layer is positioned on at least one side wall of the groove after pressing.
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| CN114071856B (en) | 2024-10-18 |
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