CN114070671A - Method for realizing dual Rapidio nodes of single processor - Google Patents

Abstract

The invention discloses a method for realizing a dual Rapidio node of a single processor, which comprises the following steps: step one, enabling a PowerPC processor to play the roles of two Rapidio nodes; step two, configuring the ID of the double Rapidio nodes on the single processor; step three, mutually identifying the double Rapidio nodes on the single processing; and step four, resource allocation of the double Rapidio nodes in a single processor. The invention greatly controls and reduces the early design cost on the premise of ensuring the stability and reliability of the network, and simultaneously facilitates the later network management and maintenance.

Description

Method for realizing dual Rapidio nodes of single processor

Technical Field

The invention belongs to the field of airborne communication, and particularly relates to a dual-satellite redundant Rapidio network architecture which can realize the role of one processor resource playing two Rapidio nodes.

Background

The RapidlO interconnection architecture is an open standard, is a high-performance point-to-point packet switching technology specially aiming at application requirements of high performance, low delay, low power consumption and the like, mainly provides high-speed reliable communication between system internal interconnection, chip-to-chip and board-to-board, has transmission performance reaching 1 Gb/s-60 Gb/s, is mainly applied to interconnection among systems or devices such as a memory mapping I/O device, a storage subsystem and a general computing platform in a multiprocessor, a memory and network equipment, and is the standard and development trend of a next generation embedded system communication bus.

The redundant architecture is mostly used in the field with very high reliability requirements, such as aerospace, telecommunication equipment, large data centers and the like, and in order to ensure the safety and stability of the system in the rapidio network, the redundant architecture is usually designed into a dual-star redundant architecture, so that the reconstruction of the system is guaranteed.

In the Rapidio network, the design of the traditional dual-star redundant architecture is basically realized by a processor serving as an EP node in the network together with a switch. Although the method solves the problem of network security and reliability, the increase of switches causes the network topology to become abnormally complex, and brings about not less challenges to later-stage development design and maintenance. Meanwhile, the design cost is greatly increased due to the increase of the number of Rapidio switches, so that the traditional double-star redundancy design brings certain inconvenience to early-stage cost control and later-stage development design.

Disclosure of Invention

The invention aims to provide a method for realizing a single-processor double Rapidio node on the basis of a double-star redundant architecture of an original Rapidio network, and aims to solve the problems of design cost and network design complexity reduction. Meanwhile, the external communication speed of the nodes can be improved, and flexible convenience is brought to Rapidio network design.

The invention aims to be realized by the following technical scheme:

a method for realizing a single-processor double Rapidio node comprises the following steps:

step one, enabling a PowerPC processor to play the roles of two Rapidio nodes;

step two, configuring the ID of the double Rapidio nodes on the single processor, wherein the configuration method comprises the following steps:

step 21, the processor acquires a service layer application software configuration starting double-node instruction, performs opening operation of two Rapidio controller ports through a serdes register set, and performs link state judgment, cpu state judgment and port bandwidth judgment of a local port;

step 22, setting deviceID of a Rapidio controller on a processor, wherein in the step, the Rapidio controller needs to be set to HOST, and meanwhile, the Rapidio controller needs to be set to be capable of responding to external data packets and being discovered by other nodes;

step 23, enabling register sets of SRIO _ P1ADIDCSR and SRIO _ P2 ADIDCSR;

and 24, respectively setting the IDs of the two Rapidio nodes to SRIO _ P1ADIDCSR and SRIO _ P2ADIDCSR register sets, and enabling the SRIO _ P1ADIDCSR and SRIO _ P2ADIDCSR register sets.

Step three, mutually identifying the double Rapidio nodes on the single processing, and realizing the following steps:

step 31, taking the previous deviceID as a MASK marking register, setting the value of the position of the large system ID in the MASK marking register as the slot number of the chassis or the ID of the single board, and setting the value of the position of the small system ID in the MASK marking register as the unique information which can be identified such as the port number of the switch;

and step 32, during route configuration, when configuring each Rapidio node, firstly recording the port number of the switch connected with the Rapidio node, then comparing the port number with the field where the deviceiD is located, if the port number is consistent with the field where the deviceiD is located, verifying the slot number or the single board ID, if the port number is consistent with the deviceiD, indicating that the configured node is one of the double nodes, and at the moment, acquiring the ID of the Rapidio node, so that the route of the Rapidio node is configured to the switch.

Step four, resource allocation of the double Rapidio nodes in a single processor, wherein the allocation steps are as follows:

step 41, starting a DPAA framework of the processor, respectively allocating DPAA resources to the two Rapidio nodes, respectively opening up RMAN, BMAN and QMAN resources, and aligning according to a specified length;

42, hanging two packet-type interrupt callback functions of Rapidio nodes respectively, so that when a DPAA qportal interrupt is triggered, data required by Rapidio in the DPAA can be analyzed through callback;

step 43, creating IBCU in RMAN about each data packet format, and writing the IBCU into DPAA;

step 44, reserving a certain virtual address for each node in the MMU, so that the node can perform maintenance or DIO operation with the outside;

and step 45, opening up a maintenance window and a DIO window for each node, and if the node passes through a hypervisor, allocating a logic LIODN serial number to each window and opening up a PAMU window so that the peripheral can have the authority when accessing the local address resource.

Drawings

Fig. 1 is a schematic diagram of a conventional dual-star redundancy structure.

Fig. 2 is a schematic diagram of a dual star redundancy structure of a processor implementing dual Rapidio nodes.

FIG. 3T2080 schematic diagram of rapidio architecture.

FIG. 4 is an exemplary diagram of a dual node mutual identification.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

In the current radio navigation system, most of processors (especially a main control processor) are PowerPCs (taking T2080 as an example), the series of processors integrate two serial RapidlO controllers, the performance can reach 5Gbaud per lane, and good performance support is provided for external RapidlO high-speed interface equipment.

The method for implementing a dual Rapidio node of a single processor shown in this embodiment includes the following steps:

step one, double-star redundancy design of single-processor double Rapidio nodes

As a simple conventional dual-star redundancy architecture as shown in fig. 1, EP1, EP2 and SW1 are basic structures, and EP1 ', EP2 ' and SW1 ' are redundant designs. In this design, each EP node is actually implemented by cooperating with a switch chip, which directly leads to an increase in cost, as previously described. Because one more switch can be used to connect one EP node with two switches, when configuring a route, there will be more stages, and so on, the route configuration of the whole network will be increased a lot, resulting in high complexity of the network.

For this, implementing one PowerPC processor may play the role of two Rapidio nodes based on the PowerPC processor.

As shown in fig. 2, EP1, EP2 and SW1 are basic structures, and EP1 ', EP2 ' and SW1 ' are redundant designs. But each EP node saves the cost of one switch compared to the design in fig. 1. In terms of network complexity, for example, routing information between the CPU1 and the CPU2, in fig. 1, data of the CPU1 needs to pass through three switches to reach the CPU2, while in fig. 2, only one switch is needed to perform data exchange, which greatly increases network complexity.

Step two, configuring the ID of the double Rapidio nodes on the single processor

In conventional designs, the device ID of each node in the Rapidio network is configured through a Base device ID command and status register (SRIO _ BDIDCSR) register as specified by the Rapidio protocol. Due to protocol specification, on the premise that the PowerPC processor is provided with two Rapidio controllers, the T2080 processor can be used as a Rapidio network node in normal use.

In this embodiment, the SRIO _ P1ADIDCSR and SRIO _ P2ADIDCSR registers specified by the non-protocol are started to replace the previous SRIO _ BDIDCSR to configure the deviceID. The configuration method mainly comprises the following steps:

step 21, a processor T2080 obtains a command for configuring and starting a service layer application software, performs opening operation on two Rapidio controller ports through a serdes register set, and performs link state judgment, cpu state judgment and port bandwidth judgment on a local port;

step 22, setting the deviceID of the T2080 Rapidio controller, in this step, firstly, setting the Rapidio controller to HOST, and simultaneously, setting the Rapidio controller to be capable of responding to external data packets and being discovered by other nodes;

step 23, enabling register sets SRIO _ P1ADIDCSR and SRIO _ P2ADIDCSR to replace deviceID specified by the Rapidio protocol;

and 24, respectively setting the IDs of the two Rapidio nodes to SRIO _ P1ADIDCSR and SRIO _ P2ADIDCSR register groups, wherein the original deviceID value is invalid, and enabling the deviceID of the register group.

Step three, mutually identifying double Rapidio nodes on single processing

In the traditional Rapidio network, the configuration of network routing is initiated by a main control node through a configuration table specified in advance to carry out network-by-network configuration; or the master control node obtains a routing table through algorithms such as depth priority and the like and then configures the routing table to the switch. However, each mode is configured one by one, and the identification number is found to determine whether the switching device or the node is the switching device, and after the node is found, the node ID is directly obtained from the register where the deviceID specified by the Rapidio protocol is located through the maintenance operation. Therefore, a problem is faced, that is, in the processor of the dual node, the location of the register specified by rapidio is not the true ID of the node, so that the mutual identification of the dual node is required.

The mutual identification of the double nodes is mainly realized by the following steps: (the network topo in FIG. 4 is illustrated above, where T2080 has two Rapidio nodes, each connected to a different switch)

Step 31, taking the previous deviceID as a MASK marking register, setting the value of the position of the large system ID in the MASK marking register as the slot number of the chassis or the ID of the single board, and setting the value of the position of the small system ID in the MASK marking register as the unique information which can be identified such as the port number of the switch;

and step 32, during route configuration, when configuring each Rapidio node, firstly recording the port number of the switch connected with the Rapidio node, then comparing the port number with the field where the deviceiD is located, if the port number is consistent with the field where the deviceiD is located, verifying the slot number or the single board ID, if the port number is consistent with the deviceiD, indicating that the configured node is one of the double nodes, and at the moment, acquiring the ID of the Rapidio node, so that the route of the Rapidio node is configured to the switch. For example, when the node with ID 1 in T2080 in fig. 4 is configured, the value in the register 0x60 is first maintained and read, if the value of the small system ID bit is 2 (port 2 of SW 1), the value of the large system field is confirmed, if the value is the chassis position, the node is one of the two nodes, otherwise, the node is a single node.

Step four, resource allocation of double Rapidio nodes in single processor

After the network configuration of the dual Rapidio nodes is realized, corresponding resources need to be allocated to each Rapidio node in the processor for the Rapidio node to communicate with an external node. The effect to be achieved is that in a Rapidio network they are the same as all other nodes in the network and that two Rapidio nodes can communicate with each other. After the effect is achieved, the two Rapidio nodes in the T2080 may be two independent EPs in the network, or may be a whole transparent to each other, and all their resources may be shared, or may communicate through messages.

The resource allocation steps of the double nodes mainly comprise the following steps:

in step 41, since the T2080 integrates a data accelerated channel (DPAA) architecture, the DPAA architecture is started, so as to achieve the purpose of releasing the cpu. Respectively allocating DPAA resources to the two Rapidio nodes, respectively opening up RMAN, BMAN and QMAN resources, and aligning according to a specified length;

42, hanging interruption callback functions of packet types such as DOORBELL and MESSAGE of the two Rapidio nodes respectively, so that when the interruption of the DPAA quantum is triggered, data required by Rapidio in the DPAA can be analyzed by callback;

step 43, creating IBCU in RMAN about each data packet format and writing the IBCU into DPAA;

step 44, reserving a certain virtual address for each node in the MMU, so that the node can perform maintenance or DIO operation with the outside;

and step 45, opening up a maintenance window and a DIO window for each node, and if the node passes through a hypervisor, allocating a logic LIODN serial number to each window and opening up a PAMU window so that the peripheral can have the authority when accessing the local address resource.

In view of the design method of the conventional double-star redundant Rapidio network, although the hot backup between the nodes can be supported, the dynamic node reconstruction can also be realized. However, the design cost of the prior art, whether the processor chip or the switch chip, is inevitably increased greatly; meanwhile, in the later network development design and management, a large workload is increased, and the labor cost is increased unnecessarily.

The method for realizing the double nodes by the single processor in the Rapidio network greatly controls and reduces the early design cost on the premise of ensuring the stability and reliability of the network, and facilitates later network management and maintenance. Meanwhile, after the design of the invention is used, the communication bandwidth can be doubled by some nodes with larger requirements on external communication bandwidth.

The design method provides a feasible idea for designers in the early stage of the network and the designers in the later stage of the network in the design of the Rapidio network, and can be used as reference by other designers of hardware and software engaged in the Rapidio network.

Claims (3)

1. A method for realizing a single-processor double Rapidio node comprises the following steps:

step one, enabling a PowerPC processor to play the roles of two Rapidio nodes;

step two, configuring the ID of the double Rapidio nodes on the single processor, wherein the configuration method comprises the following steps:

step 21, the processor acquires a service layer application software configuration starting double-node instruction, performs opening operation of two Rapidio controller ports through a serdes register set, and performs link state judgment, cpu state judgment and port bandwidth judgment of a local port;

step 22, setting deviceID of a Rapidio controller on a processor, wherein in the step, the Rapidio controller needs to be set to HOST, and meanwhile, the Rapidio controller needs to be set to be capable of responding to external data packets and being discovered by other nodes;

step 23, enabling register sets of SRIO _ P1ADIDCSR and SRIO _ P2 ADIDCSR;

and 24, respectively setting the IDs of the two Rapidio nodes to SRIO _ P1ADIDCSR and SRIO _ P2ADIDCSR register sets, and enabling the SRIO _ P1ADIDCSR and SRIO _ P2ADIDCSR register sets.

2. The method of claim 1, further comprising:

step three, mutually identifying the double Rapidio nodes on the single processing, and realizing the following steps:

step 31, taking the previous deviceID as a MASK marking register, setting the value of the position of the large system ID in the MASK marking register as the slot number of the chassis or the ID of the single board, and setting the value of the position of the small system ID in the MASK marking register as the unique information which can be identified such as the port number of the switch;

and step 32, during route configuration, when configuring each Rapidio node, firstly recording the port number of the switch connected with the Rapidio node, then comparing the port number with the field where the deviceiD is located, if the port number is consistent with the field where the deviceiD is located, verifying the slot number or the single board ID, if the port number is consistent with the deviceiD, indicating that the configured node is one of the double nodes, and at the moment, acquiring the ID of the Rapidio node, so that the route of the Rapidio node is configured to the switch.

3. The method of claim 2, further comprising:

step four, resource allocation of the double Rapidio nodes in a single processor, wherein the allocation steps are as follows:

step 41, starting a DPAA framework of the processor, respectively allocating DPAA resources to the two Rapidio nodes, respectively opening up RMAN, BMAN and QMAN resources, and aligning according to a specified length;

42, hanging two packet-type interrupt callback functions of Rapidio nodes respectively, so that when a DPAA qportal interrupt is triggered, data required by Rapidio in the DPAA can be analyzed through callback;

step 43, creating IBCU in RMAN about each data packet format, and writing the IBCU into DPAA;

step 44, reserving a certain virtual address for each node in the MMU, so that the node can perform maintenance or DIO operation with the outside;

and step 45, opening up a maintenance window and a DIO window for each node, and if the node passes through a hypervisor, allocating a logic LIODN serial number to each window and opening up a PAMU window so that the peripheral can have the authority when accessing the local address resource.

Images