CN114070446B - Data synchronous transmission method, device, equipment and storage medium - Google Patents
Data synchronous transmission method, device, equipment and storage medium Download PDFInfo
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- CN114070446B CN114070446B CN202111349956.9A CN202111349956A CN114070446B CN 114070446 B CN114070446 B CN 114070446B CN 202111349956 A CN202111349956 A CN 202111349956A CN 114070446 B CN114070446 B CN 114070446B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
Abstract
The application discloses a method, a device, equipment and a storage medium for synchronously transmitting data, wherein the method comprises the following steps: step S1, acquiring a data packet sent by a host device, wherein the data in the data packet comprises: raw data, host clock and host timestamp; step S2, comparing the slave clock with the host clock when judging that the slave time stamp is different from the host time stamp; step S3, generating a new slave time stamp according to a comparison result of the slave clock and the master clock; and S4, comparing whether the new slave time stamp is identical with the master time stamp, if so, outputting the original data, otherwise, comparing the new slave clock corresponding to the new slave time stamp with the master clock, and returning to the step S3 until the new slave time stamp is identical with the master time stamp. The technical problems that when existing data are transmitted, the master-slave machine is required to support the IEEE1588 protocol simultaneously in synchronization of the master-slave clock, the clock is difficult to synchronize and the data transmission efficiency is poor due to poor compatibility are solved.
Description
Technical Field
The present disclosure relates to the field of ethernet technologies, and in particular, to a method, an apparatus, a device, and a storage medium for synchronous data transmission.
Background
With the continuous development of telecommunication technology, the data transmission speed of the ethernet is increasing. Meanwhile, the requirements of the network on the time synchronization performance of the device are also more and more strict, and the IEEE1588 standard is generated as a clock synchronization standard. The standard can realize microsecond-level high-precision clock synchronization in an IP network with dispersed regions, the core idea is to encode time information by adopting a master-slave clock mode, and the synchronization of master-slave clocks is realized by utilizing the symmetry of the network and a delay measurement technology.
The IEEE1588 PTP time synchronization system can be applied to any multicast network, but a master-slave machine is required to simultaneously support an IEEE1588 protocol, so that the compatibility is poor, clocks are difficult to synchronize, and the data transmission efficiency is poor.
Disclosure of Invention
In view of this, the application provides a data synchronous transmission method, device, equipment and storage medium, which solve the technical problems that when the existing data is transmitted, a master-slave machine is required to support an IEEE1588 protocol simultaneously for synchronization of master-slave clocks, the compatibility is poor, the clocks are difficult to synchronize, and the data transmission efficiency is poor.
The first aspect of the present application provides a method for synchronously transmitting data, including:
step S1, acquiring a data packet sent by a host device, wherein the data in the data packet comprises: raw data, host clock and host timestamp;
s2, comparing a slave clock with the host clock when judging that the slave time stamp is different from the host time stamp;
step S3, generating a new slave time stamp according to a comparison result of the slave clock and the master clock;
and S4, comparing whether the new slave time stamp is identical with the master time stamp, if so, outputting the original data, otherwise, comparing a new slave clock corresponding to the new slave time stamp with the master clock, and returning to the step S3 until the new slave time stamp is identical with the master time stamp.
Preferably, the step S2 specifically includes:
judging whether the slave time stamp is the same as the master time stamp;
when judging that the slave time stamp is different from the master time stamp, comparing a slave clock corresponding to the slave time stamp with the master clock;
and outputting the original data when judging that the slave time stamp is the same as the master time stamp.
Preferably, determining whether the slave timestamp and the master timestamp are the same specifically includes:
generating a slave clock corresponding to the slave device;
analyzing the data packet based on the slave clock and generating a corresponding slave time stamp;
and judging whether the slave time stamp is identical to the master time stamp.
Preferably, comparing the slave clock with the master clock specifically includes:
and comparing the phase of the master clock with the phase of the slave clock.
Preferably, the step S3 specifically includes:
acquiring a phase difference between the master clock and the slave clock;
based on the phase difference, a new slave timestamp is generated.
Preferably, generating a new slave timestamp based on the phase difference specifically includes:
generating a new slave clock based on the phase difference;
and analyzing the data packet based on the new slave clock and generating a new slave time stamp.
A second aspect of the present application provides a data synchronous transmission device, including:
an obtaining unit, configured to obtain a data packet sent by a host device, where data in the data packet includes: raw data, host clock and host timestamp;
the first comparison unit is used for comparing the slave clock with the host clock when judging that the slave time stamp is different from the host time stamp;
the generating unit is used for generating a new slave time stamp according to the comparison result of the slave clock and the master clock;
and the second comparison unit is used for comparing whether the new slave machine time stamp is the same as the master machine time stamp, if so, outputting the original data, otherwise, comparing the new slave machine clock corresponding to the new slave machine time stamp with the master machine clock, and triggering the generation unit until the new slave machine time stamp is the same as the master machine time stamp.
Preferably, the first comparing unit specifically includes:
a judging subunit, configured to judge whether the slave timestamp and the master timestamp are the same;
the comparison subunit is used for comparing the slave clock corresponding to the slave time stamp with the host clock when judging that the slave time stamp is different from the host time stamp;
and the output subunit is used for outputting the original data when the slave time stamp is judged to be the same as the master time stamp.
A third aspect of the present application provides a data synchronous transmission device, the device comprising a processor and a memory;
the memory is used for storing program codes and transmitting the program codes to the processor;
the processor is configured to execute the data synchronous transmission method according to the first aspect according to an instruction in the program code.
A fourth aspect of the present application provides a storage medium for storing program code for executing the data synchronous transmission method according to the first aspect.
From the above technical solutions, the embodiments of the present application have the following advantages:
the application provides a data synchronous transmission method, which comprises the following steps: step S1, acquiring a data packet sent by a host device, wherein the data in the data packet comprises: raw data, host clock and host timestamp; step S2, comparing the slave clock with the host clock when judging that the slave time stamp is different from the host time stamp; step S3, generating a new slave time stamp according to a comparison result of the slave clock and the master clock; and S4, comparing whether the new slave time stamp is identical with the master time stamp, if so, outputting the original data, otherwise, comparing the new slave clock corresponding to the new slave time stamp with the master clock, and returning to the step S3 until the new slave time stamp is identical with the master time stamp. According to the method, the marking byte of the time stamp is added on the basis of the conventional gigabit network UDP protocol, secondary handshake protocol authentication is not needed, compatibility of the gigabit Ethernet bandwidth is improved, the problem of large delay in the data transmission process is effectively solved for synchronizing the master clock and the slave clock, and the technical problems that the master clock and the slave clock simultaneously support the IEEE1588 protocol in the existing data transmission process, the compatibility is poor, the clocks are difficult to synchronize and the data transmission efficiency is poor are solved.
Drawings
Fig. 1 is a flowchart of a first embodiment of a data synchronous transmission method in the embodiment of the present application;
FIG. 2 is a schematic diagram of phase difference in an embodiment of the present application;
fig. 3 is a flowchart of a second embodiment of a data synchronous transmission method according to an embodiment of the present application;
fig. 4 is a process schematic diagram of a data synchronous transmission method in an embodiment of the application
FIG. 5 is a graph showing the effect of aligning the phases of the master clock and the slave clock of FIG. 4;
fig. 6 is a schematic structural diagram of an embodiment of a data synchronization transmission device in the embodiment of the present application.
Detailed Description
The embodiment of the application provides a data synchronous transmission method, a device, equipment and a storage medium, which solve the technical problems that when the existing data is transmitted, a master-slave machine is required to support an IEEE1588 protocol simultaneously for synchronization of master-slave clocks, the compatibility is poor, the clocks are difficult to synchronize, and the data transmission efficiency is poor.
In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In a first embodiment of a data synchronization transmission method in this embodiment, please refer to fig. 1.
A flow chart of an embodiment of a data synchronous transmission method in this embodiment includes:
The timestamp in this embodiment may be "understood" as a synchronization signal, specifically referring to the number of clocks of the master and the number of clocks of the slave in the T time. For example, within 10us, 100M clock cycles are 10ns, then the number of cycles within 10us is 10us/10 ns=1000, it being understood that 1 us=1000 ns.
As shown in fig. 2, the master clock m_clk and the slave clock s_clk cause delay in data decoding due to the transmission link, and the worst result decoded data is erroneous, resulting in a final result and an expected inconsistency. To solve this problem: the code clock and the code clock are guaranteed to be synchronous clocks, namely, the phases are consistent. Thus, the data has little delay or smaller delay in decoding, and the final output result is not affected.
It can be understood that the data packet can be obtained through a network cable, so that the method is supported on links connected through a network port, and compatibility of other application products is further improved.
It should be noted that, the data synchronous transmission method in this embodiment is applied to the slave device.
And 102, comparing the slave clock with the master clock when judging that the slave time stamp is different from the master time stamp.
When the slave time stamp is inconsistent with the master time stamp, the clocks of the slave equipment and the master equipment are not synchronous, and the clocks are required to be synchronized at the moment so as to ensure that the decoded data in the data transmission process are normal.
When judging that the slave time stamp is different from the master time stamp, generating a new slave time stamp, and judging and implementing clock synchronization through the new slave time stamp.
When the slave time stamp is consistent with the master time stamp, the clock synchronization of the master clock and the slave clock is indicated, and the original data sent by the host equipment can be output at the moment.
In this embodiment, on the basis of the conventional gigabit network UDP protocol, the marking byte of the timestamp is added, so that secondary handshake protocol authentication is not required, compatibility of the device to other application products is increased, the utilization rate of gigabit ethernet bandwidth is effectively improved, the problem of large delay in the data transmission process is reduced for master-slave clock synchronization, and the technical problems that the master-slave machine is required to support the IEEE1588 protocol simultaneously during the existing data transmission, the compatibility is poor, the clocks are difficult to synchronize, and the data transmission efficiency is poor are solved.
The foregoing is a first embodiment of a data synchronization transmission method provided by the embodiments of the present application, and the following is a second embodiment of a data synchronization transmission method provided by the embodiments of the present application.
Referring to fig. 3, a flowchart of an embodiment of a data synchronization transmission method in an embodiment of the present application includes:
In this embodiment, step 301 is the same as step 101 in the first embodiment, and specific reference may be made to the description of step 101, which is not repeated here.
It should be noted that, whether the slave timestamp and the master timestamp are the same or not specifically includes:
generating a slave clock corresponding to the slave equipment;
analyzing the data packet based on the slave clock and generating a corresponding slave time stamp;
it is determined whether the slave timestamp and the master timestamp are the same.
And 303, comparing the slave clock corresponding to the slave timestamp with the master clock when judging that the slave timestamp is different from the master timestamp.
It should be noted that, comparing the slave clock with the master clock specifically includes:
the phase of the master clock is compared with the phase of the slave clock.
And 304, outputting the original data when judging that the slave time stamp is the same as the master time stamp.
It can be appreciated that, based on the phase difference, generating a new slave timestamp specifically includes:
generating a new slave clock based on the phase difference;
the data packet is parsed based on the new slave clock and a new slave timestamp is generated.
Due to different sources of clocks of a master and a slave in a transmission link, a certain physical delay exists due to inconsistent transmission paths. This would result in the slave being unequal in number of clocks in time T (i.e., timestamp) and in time T (i.e., timestamp) at the master. Therefore, in this embodiment, after knowing the clock number difference Δt between the slave and the master, the Δt difference is output to the peripheral circuit DA chip (may be a CS4344+osc crystal oscillator chip). The digital signal is accurately converted into an analog signal by the peripheral circuit DA chip, and then the oscillator OSC chip is driven to generate the same number of slave clocks (control the slave clock frequency) as the master clock in the T time. Meanwhile, in the embodiment, the processing of the data is clock rising edge sampling, so that the same phase is ensured under the condition that the clock frequencies of the master computer and the slave computer are consistent. Thus, the clocks of the master and the slaves can be considered to be clocks with different sources and the same phase and frequency. Step 307, comparing whether the new slave time stamp is the same as the master time stamp, if yes, outputting the original data, otherwise, comparing the new slave clock corresponding to the new slave time stamp with the master clock, and returning to step 305 until the new slave time stamp is the same as the master time stamp.
In this embodiment, on the basis of the conventional gigabit network UDP protocol, the marking byte of the timestamp is added, so that secondary handshake protocol authentication is not required, compatibility of the device to other application products is increased, the utilization rate of gigabit ethernet bandwidth is effectively improved, the problem of large delay in the data transmission process is reduced by synchronizing the master-slave design clock, and the technical problems that the master-slave clock is required to simultaneously support the IEEE1588 protocol during the existing data transmission, the compatibility is poor, the clock is difficult to synchronize and the data transmission efficiency is poor are solved.
Referring to fig. 4, for convenience of understanding, the above-mentioned data synchronous transmission method is described with reference to a specific process schematic diagram in this embodiment.
1) The Master (host device) sends the data packet to generate a time stamp, mclk (host clock), and follows the data packet to transmit through the network line.
2) Slaver generates a local clock sclk (slave clock) to parse the master packet content and generate a timestamp.
3) And comparing the timestamp generated by the Slaver with the master timestamp.
4) If the two are inconsistent, the slave phase discriminates mclk from sclk, and the phase difference of the discrimination is used for reproducing sclk, and then sclk is used for resolving master packet content again and generating a time stamp.
5) And comparing with the master time stamp until the master time stamp is the same, and outputting the master data packet content.
Referring to fig. 5, fig. 5 is an effect diagram obtained by the above-mentioned data synchronous transmission method. M_clk is a master clock, m_data is master data, s_clk is a slave clock, and s_data is slave data. At this time, the slave clock and the master clock are identical in phase and frequency, and at this time, the data can be considered to be transmitted with low delay.
The foregoing is a second embodiment of a data synchronization transmission method provided in the embodiments of the present application, and the following is an embodiment of a data synchronization transmission device provided in the embodiments of the present application.
Referring to fig. 6, a schematic structural diagram of an embodiment of a desktop display controller according to an embodiment of the present application includes:
an obtaining unit, configured to obtain a data packet sent by a host device, where data in the data packet includes: raw data, host clock and host timestamp;
the first comparison unit is used for comparing the slave clock with the host clock when judging that the slave time stamp is different from the host time stamp;
the generating unit is used for generating a new slave time stamp according to the comparison result of the slave clock and the master clock;
and the second comparison unit is used for comparing whether the new slave machine time stamp is the same as the master machine time stamp, if so, outputting the original data, otherwise, comparing the new slave machine clock corresponding to the new slave machine time stamp with the master machine clock, and triggering the generation unit until the new slave machine time stamp is the same as the master machine time stamp.
Specifically, the first contrast unit specifically includes:
a judging subunit, configured to judge whether the slave timestamp and the master timestamp are the same;
the comparison subunit is used for comparing the slave clock and the host clock corresponding to the slave timestamp when judging that the slave timestamp and the host timestamp are different;
and the output subunit is used for outputting the original data when judging that the slave time stamp is the same as the master time stamp.
It can be understood that determining whether the slave timestamp and the master timestamp are the same specifically includes:
generating a slave clock corresponding to the slave equipment;
analyzing the data packet based on the slave clock and generating a corresponding slave time stamp;
it is determined whether the slave timestamp and the master timestamp are the same.
Specifically, the method for comparing the slave clock with the master clock specifically comprises the following steps:
the phase of the master clock is compared with the phase of the slave clock.
Further, the generating unit specifically includes:
an acquisition subunit, configured to acquire a phase difference between a master clock and a slave clock;
and the generating subunit is used for generating a new slave time stamp based on the phase difference.
Specifically, generating a new slave timestamp based on the phase difference specifically includes:
generating a new slave clock based on the phase difference;
the data packet is parsed based on the new slave clock and a new slave timestamp is generated.
In this embodiment, on the basis of the conventional gigabit network UDP protocol, the marking byte of the timestamp is added, so that secondary handshake protocol authentication is not required, compatibility of the device to other application products is increased, the utilization rate of gigabit ethernet bandwidth is effectively improved, the problem of large delay in the data transmission process is reduced for master-slave clock synchronization, and the technical problems that the master-slave machine is required to support the IEEE1588 protocol simultaneously during the existing data transmission, the compatibility is poor, the clocks are difficult to synchronize, and the data transmission efficiency is poor are solved.
The embodiment of the application also provides a data synchronous transmission device, which comprises a processor and a memory; the memory is used for storing the program codes and transmitting the program codes to the processor; the processor is configured to execute the data synchronous transmission method according to the first or second embodiments according to an instruction in the program code.
The embodiment of the application also provides a storage medium, which is used for storing program codes, and the program codes are used for executing the data synchronous transmission method of the first embodiment or the second embodiment.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
The terms "first," "second," "third," "fourth," and the like in the description of the present application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be capable of operation in sequences other than those illustrated or described herein, for example. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in this application, "at least one" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: u disk, mobile hard disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.
The above embodiments are merely for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (7)
1. The data synchronous transmission method is characterized by being applied to slave equipment and comprising the following steps of:
step S1, acquiring a data packet sent by a host device, wherein the data in the data packet comprises: raw data, host clock and host timestamp;
s2, when judging that the slave time stamp is different from the master time stamp, comparing the phase of the slave clock with the phase of the master clock;
step S3, generating a new slave time stamp according to a comparison result of the slave clock and the master clock;
step S4, comparing whether the new slave time stamp is the same as the master time stamp, if so, outputting the original data, otherwise, comparing a new slave clock corresponding to the new slave time stamp with the master clock, and returning to step S3 until the new slave time stamp is the same as the master time stamp;
the step S3 specifically comprises the steps of obtaining a phase difference between the master clock and the slave clock, and generating a new slave time stamp based on the phase difference;
based on the phase difference, generating a new slave time stamp, specifically including:
generating a new slave clock based on the phase difference;
and analyzing the data packet based on the new slave clock and generating a new slave time stamp.
2. The method for synchronous data transmission according to claim 1, wherein the step S2 specifically includes:
judging whether the slave time stamp is the same as the master time stamp;
when judging that the slave time stamp is different from the master time stamp, comparing a slave clock corresponding to the slave time stamp with the master clock;
and outputting the original data when judging that the slave time stamp is the same as the master time stamp.
3. The method for synchronously transmitting data according to claim 2, wherein determining whether the slave time stamp and the master time stamp are identical comprises:
generating a slave clock corresponding to the slave device;
analyzing the data packet based on the slave clock and generating a corresponding slave time stamp;
and judging whether the slave time stamp is identical to the master time stamp.
4. A data synchronous transmission apparatus, comprising:
an obtaining unit, configured to obtain a data packet sent by a host device, where data in the data packet includes: raw data, host clock and host timestamp;
the first comparison unit is used for comparing the phase of the slave clock with the phase of the host clock when judging that the slave time stamp is different from the host time stamp;
the generating unit is used for generating a new slave time stamp according to the comparison result of the slave clock and the master clock;
the second comparison unit is used for comparing whether the new slave machine time stamp is the same as the master machine time stamp, if so, outputting the original data, otherwise, comparing a new slave machine clock corresponding to the new slave machine time stamp with the master machine clock, and triggering the generation unit until the new slave machine time stamp is the same as the master machine time stamp;
the generating unit is specifically configured to obtain a phase difference between the master clock and the slave clock, and generate a new slave timestamp based on the phase difference;
the generation unit includes:
an acquisition subunit, configured to acquire a phase difference between a master clock and a slave clock;
a generation subunit for generating a new slave timestamp based on the phase difference;
the generating subunit is specifically configured to:
generating a new slave clock based on the phase difference;
the data packet is parsed based on the new slave clock and a new slave timestamp is generated.
5. The apparatus according to claim 4, wherein the first comparing unit specifically comprises:
a judging subunit, configured to judge whether the slave timestamp and the master timestamp are the same;
the comparison subunit is used for comparing the slave clock corresponding to the slave time stamp with the host clock when judging that the slave time stamp is different from the host time stamp;
and the output subunit is used for outputting the original data when the slave time stamp is judged to be the same as the master time stamp.
6. A data synchronous transmission device, characterized in that the device comprises a processor and a memory;
the memory is used for storing program codes and transmitting the program codes to the processor;
the processor is configured to execute the data synchronous transmission method according to any one of claims 1 to 3 according to instructions in the program code.
7. A storage medium storing program code for performing the data synchronous transmission method of any one of claims 1 to 3 when executed by a processor.
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| CN107749788A (en) * | 2017-09-29 | 2018-03-02 | 郑州云海信息技术有限公司 | A kind of method, apparatus and equipment for improving clock synchronization accuracy |
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| US6804318B1 (en) * | 1999-10-12 | 2004-10-12 | Globespanvirata, Inc | System and method for using a network timing reference circuit as a phase detector in a synchronization loop |
| CN1281022C (en) * | 2001-12-04 | 2006-10-18 | 中兴通讯股份有限公司 | Method and apparatus for transmitting network synchronous clock in point to multi-point wireless system |
| JP5354474B2 (en) * | 2007-09-14 | 2013-11-27 | 日本電気株式会社 | Clock synchronization system, method thereof and program thereof |
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