CN117879747A

CN117879747A - Method, device, equipment and storage medium for acquiring message time stamp

Info

Publication number: CN117879747A
Application number: CN202311833964.XA
Authority: CN
Inventors: 易湘嵘; 宣学雷; 曾智鸣; 袁思凯; 李宁
Original assignee: Shenzhen Pango Microsystems Co Ltd
Current assignee: Shenzhen Pango Microsystems Co Ltd
Priority date: 2023-12-27
Filing date: 2023-12-27
Publication date: 2024-04-12

Abstract

The invention discloses a method, a device, equipment and a storage medium for acquiring a message time stamp, wherein the method comprises the following steps: determining a target offset of a preset zone bit of a message on a physical medium connection side in target data transmitted by a target clock signal, wherein the target data comprises data in the message, and the target offset is a bit difference value between the preset zone bit and a first bit of the target data; determining a target time stamp corresponding to the preset marker bit according to the target clock signal and the target offset; determining the time difference between the preset flag bit and the frame start symbol flag bit of the message; and acquiring the actual time stamp of the frame start symbol marker bit according to the target time stamp and the time gap. The method disclosed by the invention can solve the problem of poor accuracy of the obtained message timestamp in the prior art.

Description

Method, device, equipment and storage medium for acquiring message time stamp

Technical Field

The invention belongs to the technical field of semiconductors, and relates to a method, a device, equipment and a storage medium for acquiring a message time stamp.

Background

In order to synchronize the clock of the slave device with the reference clock of the master device under ethernet, it is necessary to determine the time delay between the clock of the slave device and the reference clock of the master device. In PTP (Precision Time Protocol, high precision time synchronization) protocol, a method for measuring a time Delay is defined, and assuming that a link between a master device and a slave device is symmetrical to a link between a slave device and a master device, a value of the time Delay may be obtained by subtracting t2 from t1 and subtracting an MPD (Mean Path Delay), where the MPD is an average value of a difference between t1 and t2 and a difference between t4 and t3, where t1 is a time when a message is sent from the master device, t2 is a time point when a message is received from the slave device, t3 is a time point when a Delay request message is sent from the slave device, and t4 is a time point when the master device receives the Delay request message.

Therefore, to correct the slave clock so that the slave clock is synchronized with the reference clock of the master, the above-mentioned time stamps t1, t2, t3, and t4 of the messages need to be determined. The ethernet is generally divided into a MAC (Medium Access Control ) layer, a PCS (Physical Coding Sublayer, physical coding sublayer) layer and a PMA (Physical Medium Attachment, physical medium connection) sublayer, and theoretically, the closer the timestamp is to the line side timestamp, the more accurate the timestamp is, the closer to the actual value is, therefore, in the prior art, the timestamp is usually printed on a mii (Media Independent Interface, medium independent interface) interface, and the mii interface is a MAC interface and a PCS interface, but because the PCS processing modes of the respective rates are different, the processing is different, and the asynchronous FIFO (First in, first out, first in First out) introduced during rate switching also causes jitter of the timestamp.

In view of the foregoing, there is a need in the art for a method for obtaining accurate message timestamps.

Disclosure of Invention

The invention provides a method, a device, equipment and a storage medium for acquiring a message timestamp, which are used for solving the problem of poor accuracy of the acquired message timestamp in the prior art.

In order to solve the above technical problems, in a first aspect, the present invention provides a method for obtaining a message timestamp, where the method includes:

determining a target offset of a preset zone bit of a message on a physical medium connection side in target data transmitted by a target clock signal, wherein the target data comprises data in the message, and the target offset is a bit difference value between the preset zone bit and a first bit of the target data;

determining a target time stamp corresponding to the preset marker bit according to the target clock signal and the target offset;

determining the time difference between the preset flag bit and the frame start symbol flag bit of the message;

and acquiring the actual time stamp of the frame start symbol marker bit according to the target time stamp and the time gap.

Optionally, when sending the message, the preset flag bit is a frame start symbol flag bit.

Optionally, in the target data transmitted by the target clock signal, determining the target offset of the preset flag bit of the packet on the physical medium connection side includes:

when receiving a message, determining a target offset of a preset flag bit of the message on a physical medium connection side in target data transmitted by a target clock signal aiming at the message without alignment characters, wherein the preset flag bit is a fixed flag bit which is periodically set.

when receiving a message, determining a target offset of a preset zone bit of the message on a physical medium connection side in target data transmitted by a target clock signal aiming at the message with the alignment character, wherein the preset zone bit is a position which is N bits away from the zone bit of the alignment character.

Optionally, after the acquiring the actual timestamp of the frame initiator flag bit, the method further includes:

calculating a first time difference value between a first time stamp of a target message sent by a master device and a second time stamp of a target message received by a slave device, wherein the first time stamp and the second time stamp are actual time stamps of frame start symbol mark bits;

determining a second time difference value between the first time difference value and a preset average path delay;

determining the second time difference value as an actual clock delay of the master device and the slave device;

and correcting the clock of the slave device according to the actual clock delay by taking the clock of the master device as a reference clock.

Optionally, the determining, according to the target clock signal and the target offset, a target timestamp corresponding to the preset flag bit includes:

determining a third timestamp of the target clock signal corresponding to the first bit of the target data;

and determining a target timestamp corresponding to the preset marker bit according to the target offset and the third timestamp.

Optionally, the determining the time difference between the preset flag bit and the frame start symbol flag bit of the message includes:

determining first data of a frame start symbol zone bit of the message and a first clock signal for transmitting the first data;

determining a first number of clock signals that differ between the target clock signal and the first clock signal;

when the message is transmitted from a preset flag bit to a frame start symbol flag bit, determining a first offset of the message transmitted in the target data and a second offset of the message transmitted in the first data;

and determining the time sum of the first time corresponding to the first offset, the second time corresponding to the second offset and the third time corresponding to the first number of clock signals as the time difference between the preset flag bit and the frame start symbol flag bit.

In a second aspect, the present invention provides a device for acquiring a message timestamp, where the device includes:

the first determining module is used for determining a target offset of a preset zone bit of a message on a physical medium connection side in target data transmitted by a target clock signal, wherein the target data comprises data in the message, and the target offset is a bit number difference value between the preset zone bit and a first bit of the target data;

the second determining module is used for determining a target timestamp corresponding to the preset marker bit according to the target clock signal and the target offset;

a third determining module, configured to determine a time gap between the preset flag bit and a frame start symbol flag bit of the message;

and the acquisition module is used for acquiring the actual time stamp of the frame start symbol zone bit according to the target time stamp and the time gap.

In a third aspect, the present invention provides a device for obtaining a timestamp of a message, including a memory and a processor, where:

the memory is used for storing a computer program;

the processor is configured to read the program in the memory and execute the steps of a method for obtaining a message timestamp provided in the first aspect.

In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon a readable computer program which when executed by a processor performs the steps of a method for obtaining a message timestamp as provided in the first aspect above.

Compared with the prior art, the method for acquiring the message time stamp has the following beneficial effects:

according to the invention, the offset of the preset marker bit in the target data of the PMA side is determined in real time, the time stamp of the preset marker bit in the PMA side can be obtained, the offset can be understood to be changed in real time when the Ethernet speed is changed, so that the time stamp of the preset marker bit finally obtained in the PMA side is ensured to be the real-time stamp, the problem of jitter of the time stamp caused by the Ethernet speed change after the time stamp is stamped is avoided, the accuracy of the obtained time stamp of the preset marker bit can be effectively improved, the PMA side is the line side, the accuracy of the obtained time stamp of the preset marker bit can be further improved when the time stamp of the preset marker bit is obtained in the PMA side, and thus the time distance between the preset marker bit and the SFD (Start frame delimiter, frame initiator) marker bit is determined, and the accuracy of the obtained time stamp of the SFD marker bit is also effectively improved when the time stamp of the SFD marker bit is obtained based on the time stamp of the preset marker bit and the time distance.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present invention, but not all embodiments, and other drawings obtained according to these drawings without inventive effort to those skilled in the art are all within the scope of the protection of the present application.

Fig. 1 is a flowchart of a method for obtaining a message timestamp according to an embodiment of the present application;

fig. 2 is a flowchart of another method for obtaining a message timestamp according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a device for acquiring a message timestamp according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a device for acquiring a message timestamp according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a computer readable storage medium according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

In order that the present disclosure may be more fully described and fully understood, the following description is provided by way of illustration of embodiments and specific examples of the present invention; this is not the only form of practicing or implementing the invention as embodied. The description covers the features of the embodiments and the method steps and sequences for constructing and operating the embodiments. However, other embodiments may be utilized to achieve the same or equivalent functions and sequences of steps. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.

In the description of the embodiments of the present invention, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; the text "and/or" is merely an association relation describing the associated object, and indicates that three relations may exist, for example, a and/or B may indicate: in addition, in the description of the embodiments of the present application, "a plurality" means two or more, and other words and the like, it is to be understood that the preferred embodiments described herein are merely for illustrating and explaining the present invention, and are not intended to limit the present invention, and that the embodiments of the present application and the features of the embodiments may be combined with each other without conflict.

Fig. 1 is a flowchart of a method for obtaining a message timestamp according to an embodiment of the present invention, which includes the following steps.

Step S101, determining a target offset of a preset flag bit of a message on a PMA side in target data transmitted by a target clock signal.

The target data comprises data in the message, and the target offset is a bit difference value between the preset flag bit and the first bit of the target data.

Specifically, the process of transmitting the message may be a process of transmitting the message or a process of receiving the message. It will be appreciated that the target data is data that is transmitted as a clock signal when the message is transmitted to the PMA side.

It should be noted that the target clock signal may be one of a plurality of clock signals when transmitting a packet, and the clock signal may be generated by a clock generator; it should be further noted that, the target data transferred in the target clock signal may be transferred through the data bus, and the number of bits of the target data transferred in the data bus under the target clock signal may be determined according to the specific requirements of the application, for example, the number of bits of the target data may be 128 bits, 256 bits, or the like.

It should be noted that, the preset flag bit in this step may be any bit in the target data, and may specifically be set according to specific needs in application, for example, the preset flag bit may be the first bit in the target data, may be the last bit in the target data, or may be the middle bit in the target data.

As a specific example, for example, if the preset flag bit is the 56 th bit in the target data, it can be understood that the difference between the number of bits of the preset flag bit and the first bit of the target data is 55, and the target offset is 55.

Step S102, determining a target timestamp corresponding to the preset flag bit according to the target clock signal and the target offset.

It can be understood that, in this step, the manner of determining the target timestamp corresponding to the preset flag bit according to the target clock signal and the target offset may be any manner that can be implemented. For example, an initial time at which the target clock signal starts may be determined, and a unit time corresponding to the unit target offset may be determined, and then the target time stamp corresponding to the preset flag bit is a sum of the initial time and a product of the target offset multiplied by the unit time, and the unit time corresponding to the unit target offset may be set specifically empirically when applied.

Step S103, determining the time difference between the preset flag bit and the SFD flag bit of the message.

Specifically, the manner of determining the time difference between the preset flag bit and the SFD flag bit of the message may be any manner. For example, the oscillograph can output the waveform of the data during message transmission, and further the phase difference between the preset flag bit and the SFD flag bit can be determined through the waveform, and the time difference between the preset flag bit and the SFD flag bit can be obtained by converting the phase difference into the time difference.

Step S104, according to the target time stamp and the time gap, acquiring the actual time stamp of the SFD zone bit.

It is understood that the actual timestamp of the SFD flag bit is the sum of the target timestamp and the time gap.

Therefore, the offset of the preset marker bit in the target data of the PMA side can be determined in real time, the time stamp of the preset marker bit in the PMA side can be obtained, the offset can be understood to change in real time when the Ethernet speed is changed, the time stamp of the preset marker bit finally obtained in the PMA side is guaranteed to be the real-time stamp, the problem that the time stamp is dithered due to the Ethernet speed change after the time stamp is stamped in the prior art is avoided, the accuracy of the obtained time stamp of the preset marker bit can be effectively improved, the PMA side is the line side, the accuracy of the obtained time stamp of the preset marker bit can be further improved when the time stamp of the preset marker bit is obtained in the PMA side, and the accuracy of the obtained time stamp of the SFD marker bit can be effectively improved when the time distance between the preset marker bit and the SFD marker bit is determined based on the time stamp of the preset marker bit and the time distance.

In an optional implementation manner, when the message is sent, the preset flag bit is an SFD flag bit.

It should be noted that, when sending a message, the SFD flag bit of the message may be found at the PMA side, so, in order to save a flow, an actual timestamp corresponding to the SFD flag bit may be obtained quickly, and a preset flag bit may be set as the SFD flag bit.

It can be understood that when the preset flag bit is an SFD flag bit, the time difference between the preset flag bit and the SFD flag bit is 0, i.e., the target timestamp of the determined preset flag bit is the actual timestamp of the SFD flag bit.

In an optional implementation manner, in the target data transmitted by the target clock signal, determining a target offset of a preset flag bit of the message on the PMA side includes:

when receiving a message, determining a target offset of a preset zone bit of the message on a PMA side in target data transmitted by a target clock signal aiming at the message without alignment characters.

The preset flag bit is a fixed flag bit which is set periodically.

It will be appreciated that the preset flag bit is set so-called periodically for the clock signal at the time of message transmission.

For example, the message without the AM (alignment) character may be a message transmitted under 10G-bit ethernet, and the message with the AM character may be a message transmitted under 40G-bit ethernet, 50G-bit ethernet, or 100G-bit ethernet.

Specifically, when the preset flag bit is set periodically, the set period may be any number of times corresponding to clock signals, for example, the period may be one time corresponding to one clock signal, that is, one preset flag bit is set in each clock signal, and for example, the period may be 100 times corresponding to clock signals.

It should be noted that, the target clock signal in this implementation manner is a clock signal corresponding to the target data where the preset flag bit nearest to the PMA side is located when the message is transmitted.

It will be understood that the preset flag bit being a fixed flag bit means that the preset flag bit is a fixed bit in data sent under a clock signal, and the number of bits in the data of the fixed bit may be set according to specific needs, which is not specifically limited herein.

It should be noted that, when receiving a message, a series of pre-processing needs to be performed when searching for the SFD flag bit, which leads to the situation that the SFD flag bit is missed at the PMA side, so that the flag bit can be preset, and because the preset flag bit is a fixed flag bit which is periodically set, the preset flag bit can be found at the PMA side, and further, the timestamp of the preset flag bit which is relatively accurate can be determined at the PMA side, so that after the SFD flag bit is found, the timestamp of the SFD flag bit which is relatively accurate can be obtained based on the timestamp of the preset flag bit after the time distance between the SFD flag bit and the preset flag bit is determined.

when receiving a message, determining a target offset of a preset flag bit of the message on a PMA side in target data transmitted by a target clock signal aiming at the message with the AM character.

The preset flag bit is a position which is separated from the flag bit of the AM character by N bits.

It should be noted that, N in this implementation manner is a positive integer, and a specific value of N in this implementation manner may be set according to specific requirements in application, for example, N may be 1 or 2, and when N is 1, the preset flag bit may be a later bit of the AM character.

It should be noted that, the AM character is a character set for alignment in the message, and the character is usually set in the PCS layer, and the character may be knocked out when the message is transmitted to the MAC layer, so that in this implementation manner, the preset flag bit is set at a position N bits away from the AM character, so that on one hand, the preset flag bit may not be knocked out, and on the other hand, the preset flag bit may be set by means of the AM character included in the message body, and compared with the case that the message without the AM character needs to periodically set the preset flag bit, the resource for setting the preset flag bit is effectively saved.

In an alternative implementation, after the obtaining the actual timestamp of the SFD flag bit, the method further includes:

calculating a first time difference value between a first time stamp of a target message sent by a master device and a second time stamp of a target message received by a slave device, wherein the first time stamp and the second time stamp are actual time stamps of SFD (small form factor) zone bits;

It should be noted that, the first time difference value is a value obtained by subtracting the first time stamp from the second time stamp; the second time difference is the value obtained by subtracting the average path delay from the first time difference.

It should be noted that, the method for acquiring the first timestamp corresponding to the target message sent by the master device and the method for acquiring the second timestamp of the target message received by the slave device may refer to the method for acquiring the actual timestamp of the SFD flag bit of the message in the above time methods.

It should be noted that, in this implementation manner, the average path delay may be calculated by using the following manner, where MPD is an average value of a difference value of t1 minus t2 and a difference value of t4 minus t3, where t1 is a time when a message is sent from a master device, t2 is a time point when a message is received from a slave device, t3 is a time point when a delay request message is sent from the slave device, and t4 is a time point when the master device receives the delay request message, and it is understood that the time stamps t1 to t4 may all correspond to time stamps of SFD flag bits. It may be understood that the message for calculating the average path delay may be consistent with the target message in the present implementation manner, or may be inconsistent with the target message in the present implementation manner, and may be specifically set according to the specific needs of the application, which is not specifically limited herein.

It should be noted that, in the foregoing implementation manner, the corresponding timestamp is obtained based on the clock signal set in the present implementation manner, if the clocks of the master device and the slave device are required to be made to be based on the global universal clock, the corresponding relationship between the clock signal and the global universal clock (for example, beijing time) may be determined, and when determining the timestamp under the clock signal, the timestamp may be converted into the standard timestamp under the global universal clock according to the corresponding relationship between the clock signal and the global universal clock.

In an optional implementation manner, the determining, according to the target clock signal and the target offset, a target timestamp corresponding to the preset flag bit includes:

It is understood that the third timestamp of the target clock signal corresponding to the first bit of the target data is the start time of the target clock signal.

It can be understood that the ratio of the time corresponding to the target clock signal to the number of the target data bits under the target clock signal is the unit time of transmitting one bit of data by the data bus, so that the time distance corresponding to the target offset can be obtained by the product of the target offset and the unit time, and then the time distance is added on the basis of the third time stamp, so that the target time stamp corresponding to the preset flag bit can be obtained.

In an alternative implementation manner, as shown in fig. 2, a flowchart of a method for obtaining a message timestamp according to another embodiment of the present invention is provided, and the step S103 includes:

step S1031, determining first data where the SFD flag bit of the message is located and a first clock signal for transmitting the first data;

step S1032, determining a first number of clock signals differing between the target clock signal and the first clock signal;

step S1033, when the message is transmitted from a preset flag bit to an SFD flag bit, determining a first offset of the message transmitted in the target data and a second offset of the message transmitted in the first data;

step S1034, determining a time sum of the first time corresponding to the first offset, the second time corresponding to the second offset, and the third time corresponding to the first number of clock signals as a time gap between the preset flag bit and the SFD flag bit.

It should be noted that, in the actual transmission process of the message, the SFD flag bit may be in front of the preset flag bit in time sequence, or may be behind the preset flag bit, and when the SFD flag bit is in front of the preset flag bit, the first offset is a difference value between the bits of the preset flag bit and the first bit of the target data in the target data, and the second offset is a difference value between the bits of the SFD flag bit and the last bit of the first data in the first data; when the SFD zone bit is behind the preset zone bit, the first offset is the difference value of the number of bits of the preset zone bit and the last bit of the target data in the target data, and the second offset is the difference value of the number of bits of the SFD zone bit and the first bit of the first data in the first data.

It should be noted that, the method for determining the first number of clock signals different between the target clock signal and the first clock signal may be any method, for example, the first number corresponding to the clock signals different between the target clock signal and the first clock signal may be obtained by counting the clock signals different between the target clock signal and the first clock signal through a counter, for example, if the preset flag bit is set periodically, the number of clock signals corresponding to one period may be calculated first, so as to determine the time of the corresponding clock signal in one period, and further determine the number of preset flag bits passing from the preset flag bit to the SFD flag bit, where the number is multiplied by the time corresponding to the first number of clock signals. Further, the unit time corresponding to each clock signal may be preset, so the third time corresponding to the first number of clock signals is a product of the unit time corresponding to the clock signal and the first number.

It should be noted that, the manner of obtaining the first time corresponding to the first offset and the second time corresponding to the second offset may refer to the description of determining the time corresponding to the target offset in the foregoing implementation manner, which is not repeated herein.

Based on the method for acquiring the message timestamp, the embodiment of the invention provides a device for acquiring the message timestamp, as shown in fig. 3, which comprises:

a first determining module 310, configured to determine, in target data transmitted by a target clock signal, a target offset of a preset flag bit of a packet on a PMA side, where the target data includes data in the packet, and the target offset is a bit number difference between the preset flag bit and a first bit of the target data;

a second determining module 320, configured to determine, according to the target clock signal and the target offset, a target timestamp corresponding to the preset flag bit;

a third determining module 330, configured to determine a time gap between the preset flag bit and the SFD flag bit of the packet;

and an obtaining module 340, configured to obtain an actual timestamp of the SFD flag bit according to the target timestamp and the time gap.

For other details of implementing the above technical solution by each module in the device for acquiring a packet timestamp, reference may be made to the description in the method for acquiring a packet timestamp provided in the embodiment of the present invention, which is not repeated herein.

Based on the above method for acquiring the message timestamp, as shown in fig. 4, the embodiment of the invention further provides a schematic structural diagram of a device for acquiring the message timestamp, where the identifying device includes a processor 41 and a memory 42 coupled to the processor 41. The memory 42 stores a computer program which, when executed by the processor 41, causes the processor 41 to perform the steps of the method for acquiring a message timestamp in the above-described embodiment.

For other details of the implementation of the foregoing technical solution by the processor 41 in the apparatus for acquiring a packet timestamp, reference may be made to the description of the method for acquiring a packet timestamp provided in the foregoing embodiment of the present invention, which is not repeated herein.

Wherein the processor 41 may also be referred to as a central processing unit (Central Processing Unit, CPU), the processor 41 may be an integrated circuit chip with signal processing capability; the processor 41 may also be a general purpose processor, which may be a microprocessor or the processor 41 may also be any conventional processor, etc., a digital signal processor (Digital Signal Process, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.

As shown in fig. 5, an embodiment of the present invention further provides a schematic structural diagram of a computer-readable storage medium, on which a readable computer program 51 is stored; the computer program 51 may be stored in the storage medium in the form of a software product, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a mobile hard disk, a magnetic disk or a compact disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), or a terminal device such as a computer, a server, a mobile phone, a tablet, etc.

In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.

The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium, or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The foregoing has described in detail the technical solutions provided herein, and specific examples have been used to illustrate the principles and embodiments of the present application, where the above examples are only used to help understand the methods and core ideas of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the one or more processes and-

Or a block diagram of one or more of the functions specified in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. The method for acquiring the message time stamp is characterized by comprising the following steps:

2. The method for obtaining a message timestamp according to claim 1, wherein the preset flag bit is a frame start symbol flag bit when the message is sent.

3. The method for obtaining a message timestamp according to claim 1, wherein determining a target offset of a preset flag bit of a message on a physical medium connection side in target data transmitted by a target clock signal includes:

4. The method for obtaining a message timestamp according to claim 1, wherein determining a target offset of a preset flag bit of a message on a physical medium connection side in target data transmitted by a target clock signal includes:

5. The method for obtaining a message timestamp according to claim 1, further comprising, after the obtaining the actual timestamp of the frame start symbol flag bit:

6. The method for obtaining a message timestamp according to claim 1, wherein determining the target timestamp corresponding to the preset flag bit according to the target clock signal and the target offset includes:

7. The method for obtaining a message timestamp according to claim 1, wherein determining the time difference between the preset flag bit and the frame start symbol flag bit of the message comprises:

8. An apparatus for obtaining a message timestamp, comprising:

9. The device for acquiring the message time stamp is characterized by comprising a memory and a processor, wherein:

the memory is used for storing a computer program;

the processor is configured to read the computer program in the memory and execute the steps of the method for obtaining a message timestamp according to any of claims 1-7.

10. A computer readable storage medium, characterized in that a readable computer program is stored thereon, which program, when being executed by a processor, implements the steps of the method of retrieving a message timestamp according to any of claims 1-7.