CN114070244A - Silicon back etching FBAR resonator and preparation method thereof - Google Patents
Silicon back etching FBAR resonator and preparation method thereof Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 48
- 239000010703 silicon Substances 0.000 title claims abstract description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 47
- 238000005530 etching Methods 0.000 title claims abstract description 10
- 238000002360 preparation method Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims description 218
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 38
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 17
- 235000012239 silicon dioxide Nutrition 0.000 claims description 17
- 238000011068 loading method Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 238000003780 insertion Methods 0.000 abstract description 5
- 230000037431 insertion Effects 0.000 abstract description 5
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- 238000001755 magnetron sputter deposition Methods 0.000 description 3
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
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- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02007—Details of bulk acoustic wave devices
- H03H9/02015—Characteristics of piezoelectric layers, e.g. cutting angles
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02007—Details of bulk acoustic wave devices
- H03H9/02086—Means for compensation or elimination of undesirable effects
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
- H03H2003/023—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the membrane type
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Abstract
The invention provides a silicon back etching FBAR resonator and a preparation method thereof, wherein the resonator sequentially comprises a silicon substrate, a supporting layer and a piezoelectric layer from bottom to top; a cavity is formed below the support layer, the support layer is partially exposed in the cavity, and the side wall of the cavity is formed by the silicon substrate; a lower electrode layer is arranged between the supporting layer and the piezoelectric layer, and an upper electrode layer is arranged above the piezoelectric layer; the resonator further comprises an upper load layer and a lower load layer; the upper load layer and the lower load layer are respectively arranged along the edges of the upper electrode layer and the lower electrode layer in a surrounding mode, and the lower load layer penetrates through the supporting layer and extends into the cavity; the upper load layer and the lower load layer are distributed up and down symmetrically. The invention can reduce the acoustic wave energy consumption of the transverse mode in the piezoelectric layer by adopting the design of the symmetrical load layer, effectively reduce the parasitic waveform of the FBAR resonator at the position of the resonance peak, and is beneficial to constructing a high-quality bulk acoustic wave filter with low insertion loss.
Description
Technical Field
The invention relates to the technical field of bulk acoustic wave resonators, in particular to a silicon back etching FBAR resonator and a preparation method thereof.
Background
The filter is mainly used for selectively filtering the transceiving signals of a specific frequency band and reducing the influence of interference signals. Low frequency Surface Acoustic Wave (SAW) filters and bulky dielectric filters cannot meet the requirements of mobile phone terminals, micro base stations and the like on high frequency and micro size at all. The Film Bulk Acoustic Resonator (FBAR) filter has the advantages of small volume, low loss, integration, high quality factor, high out-of-band rejection, high working frequency, high power bearing capacity and the like, and is the only 5G radio frequency filter which can meet the 5G high-frequency requirement and can meet the radio frequency front-end modular integration at present. The FBAR bulk acoustic wave filter is an irreplaceable core element of a radio frequency communication front end, plays a role in main filtering and frequency selection, is one of key devices in the field of mobile communication, and is also one of the most promising third-generation semiconductor devices generally accepted in the industry.
The currently mainstream cavity-type FBAR resonators have the following disadvantages: (1) the parasitic coupling phenomenon is severe and interferes with the normal main resonance peak curve. (2) The filter composed of the common cavity type FBAR resonators has serious in-band insertion loss, and the process device result is not accordant with simulation.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a silicon back etching FBAR resonator and a preparation method thereof, and solves the problems of parasitic resonance, low quality factor and large insertion loss of the existing single crystal film bulk acoustic resonator. The technical scheme of the invention is as follows:
in a first aspect, the invention provides a silicon back-etched FBAR resonator, which sequentially comprises a silicon substrate, a supporting layer and a piezoelectric layer from bottom to top; a cavity is formed below the support layer, the support layer is partially exposed in the cavity, and the side wall of the cavity is formed by the silicon substrate; a lower electrode layer is arranged between the supporting layer and the piezoelectric layer, and an upper electrode layer is arranged above the piezoelectric layer;
the resonator further comprises an upper load layer and a lower load layer; the upper load layer and the lower load layer are respectively arranged along the edges of the upper electrode layer and the lower electrode layer in a surrounding mode, and the lower load layer penetrates through the supporting layer and extends into the cavity; the upper load layer and the lower load layer are distributed up and down symmetrically.
Furthermore, the thickness of the silicon substrate is 575 mu m, and the cross section of the silicon substrate is of an inverted right-angled trapezoid structure.
Furthermore, the supporting layer is made of silicon dioxide and has a thickness of 2-3.5 μm.
Furthermore, the piezoelectric layer is made of AlN and has the thickness of 500 nm-4 μm.
Furthermore, the upper electrode layer and the lower electrode layer are made of any one of Mo, Pt, Ti and Au, and the thickness is 50 nm-1 μm.
Furthermore, the upper load layer and the lower load layer are made of any one of Mo, Pt, Ti and Au, the thickness is 50 nm-2 μm, and the width is 50 nm-10 μm.
Furthermore, the number of the upper load layer and the lower load layer is 1 or more, and the upper load layer and the lower load layer are in a polyhedral frame structure.
Further, when the number of the upper load layer and the lower load layer is plural, the plural polyhedral frame structures are respectively arranged in a nested manner of surrounding one by one, adjacent polyhedral frame structures are spaced at a certain distance, the outermost polyhedral frame structure is respectively arranged along the edges of the upper electrode layer and the lower electrode layer in a surrounding manner, and other layers of polyhedral frame structures are respectively arranged on the upper electrode layer and the lower electrode layer.
Further, the polyhedral frame structure is a regular pentahedral frame structure.
In a second aspect, the invention provides a method for manufacturing a silicon back-etched FBAR resonator, comprising the following steps:
step S1, depositing a support layer on the silicon substrate;
step S2, growing a lower electrode metal film on the supporting layer based on the step S1 and carrying out graphical processing to obtain a lower electrode layer;
step S3, based on step S2, a piezoelectric film is epitaxially grown on the lower electrode layer and is subjected to photoetching and patterning treatment to obtain a piezoelectric layer;
step S4, continuing to grow an upper electrode metal film on the piezoelectric layer based on step S3 and performing a patterning process to obtain an upper electrode layer;
step S5, preparing an upper loading layer on the piezoelectric layer based on step S4, so that the upper loading layer is surrounded along the edge of the upper electrode layer;
step S6, growing a silicon dioxide passivation layer on the upper electrode layer and the upper loading layer based on step S5;
step S7, removing silicon in the working area of the silicon substrate resonator by adopting a back etching process to form a cavity and partially expose the supporting layer;
step S8, preparing a lower load layer on the support layer based on the step S7, wherein one end of the lower load layer is arranged along the edge of the lower electrode layer in a surrounding mode, and the other end of the lower load layer extends into the cavity;
and step S9, removing the top silicon dioxide protective layer to obtain the FBAR bulk acoustic wave resonator.
Further, the method for depositing the support layer in step S1 is a plasma enhanced chemical vapor deposition method (PECVD).
Further, the method for growing the lower electrode metal film in step S2 is deposition or sputtering, preferably magnetron sputtering.
Optionally, the method for growing the piezoelectric thin film in step S3 includes one or more of PVD, MOCVD, PLD, and ALD.
Further, the method for growing the upper electrode metal film in step S4 is deposition or sputtering, preferably magnetron sputtering.
The resonator of the invention forms a piezoelectric oscillation sandwich structure through the upper electrode, the piezoelectric layer and the lower electrode together, and can reduce the performance loss introduced by an external circuit. And the design of the symmetrical load layer can reduce the energy consumption of the sound wave in the transverse mode in the piezoelectric layer, and the sound wave in the transverse mode in the piezoelectric layer is reflected back to the interior of the piezoelectric oscillation stack from the edge of the device, so that the parasitic waveform of the FBAR resonator at the position of a resonance peak is effectively reduced, and the construction of a high-quality bulk acoustic wave filter with low insertion loss is facilitated. The loading layer can be arranged into a one-step or multi-step complex layer array to further balance stray factors introduced by the loading layer. The cavity is arranged to effectively form total reflection of the bulk acoustic wave by utilizing the characteristic that air and the piezoelectric material have different acoustic impedances. In addition, the invention only needs to prepare the load layer with the same material on the upper electrode and the lower electrode, and does not need to prepare a functional film layer or externally connect a capacitor resistor, thereby reducing the preparation difficulty and further reducing the preparation cost.
Drawings
Fig. 1 is a schematic structural diagram of a supporting layer deposited on a silicon substrate in step S1 in the process of manufacturing an FBAR resonator according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of the step S2 of growing the lower electrode on the supporting layer in the FBAR resonator manufacturing process according to the embodiment of the present invention.
Fig. 3 is a schematic structural diagram of the silicon substrate, the supporting layer, the piezoelectric layer, and the bottom electrode in step S3 in the FBAR resonator manufacturing process according to the embodiment of the present invention.
Fig. 4 is a schematic structural diagram of the silicon substrate, the supporting layer, the piezoelectric layer, the lower electrode, and the upper electrode in step S4 in the FBAR resonator manufacturing process according to the embodiment of the present invention.
Fig. 5 is a schematic structural diagram of the upper loading layer prepared in step S5 in the FBAR resonator preparation process according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of step S6 of growing a silicon dioxide passivation layer on the upper electrode layer and the upper load layer in the FBAR resonator manufacturing process according to an embodiment of the invention.
Fig. 7 is a schematic structural diagram of the cavity formed in step S7 in the FBAR resonator manufacturing process according to the embodiment of the present invention.
Fig. 8 is a schematic structural diagram of the FBAR resonator manufacturing process in which the lower electrode loading layer is formed in step S8 according to the embodiment of the present invention.
Fig. 9 is a schematic structural diagram of a silicon back-etched FBAR resonator of the present invention.
Fig. 10 is a schematic top view of a load layer of the present invention, with an electrode layer enclosed in the middle, here shown with a white background to prevent confusion.
Fig. 11 is a schematic structural view of an FBAR resonator using 2 sets of upper and lower loading layers according to the present invention.
FIG. 12 is a schematic top view of the present invention employing multiple upper and lower load layers.
Fig. 13 is an admittance curve of the resonator obtained in example 1 of the present invention.
Fig. 14 is an admittance curve of the resonator obtained in example 2 of the present invention.
Fig. 15 is an admittance curve of the resonator obtained in comparative example 1 of the present invention.
Fig. 16 is an admittance curve of the resonator obtained in comparative example 2 of the present invention.
The reference numerals of FIGS. 1-8 illustrate: 101 a silica support layer; 102 a silicon substrate; 103 a lower electrode layer; 104 a piezoelectric layer; 105 an upper electrode layer; 106 an upper load layer; 107 silicon dioxide protective layer; 108 a lower load layer; 109 cavity.
Detailed Description
In the description of the present invention, it is to be noted that those whose specific conditions are not specified in the examples are carried out according to the conventional conditions or the conditions recommended by the manufacturers. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
The present invention will be described in further detail with reference to specific embodiments thereof to assist those skilled in the art in providing a more complete, accurate and thorough understanding of the inventive concept and aspects thereof, and the scope of the present invention includes, but is not limited to, the following examples, and any modifications in the details and form of the technical aspects thereof that fall within the spirit and scope of the present application are intended to be included therein.
Example 1
As shown in fig. 9 to 10, the present embodiment provides a silicon back-etched FBAR resonator comprising a high-silicon substrate 102, a silicon dioxide support layer 101, and an AlN single-crystal piezoelectric thin film layer 104; a cavity 109 is formed below the silicon dioxide support layer 101, and the silicon dioxide support layer 101 is partially exposed in the cavity 109, and the side wall of the cavity 109 is formed by the silicon substrate 102; a lower electrode layer 103 is arranged between the silicon dioxide supporting layer 101 and the single crystal piezoelectric thin film layer 104, and an upper electrode layer 105 is arranged above the single crystal piezoelectric thin film layer 104; the upper electrode layer 105 and the lower electrode layer 103 are respectively surrounded by an upper load layer 106 and a lower load layer 108 along the edges of the upper electrode layer 105 and the lower electrode layer 103; and the lower loading layer 108 extends through the silicon dioxide support layer 101 into the cavity 109; the upper load layer 106 and the lower load layer 108 are distributed symmetrically up and down.
Specifically, in the embodiment, the upper load layer 106 and the lower load layer 108 are made of Mo, the number of the upper load layer and the lower load layer is 1, the upper load layer and the lower load layer are in a regular pentahedron frame structure, the width of the upper load layer and the lower load layer is set to be 1.25 μm, the width is obtained by analyzing each sound wave scattering in the resonator according to a simulation calculation result, and a quarter wavelength of a transversely transmitted sound wave wavelength obtained by analyzing each sound wave scattering in the resonator is taken as the width of the load layer, and the thickness is 50 nm.
Specifically, in this embodiment, the thickness of the silicon dioxide support layer 101 is 2 μm. The thickness of the single crystal piezoelectric thin film layer 104 is 2 μm, and the high-quality AlN piezoelectric thin film 104 can be better applied to a frequency band of 3GHz or more. . The thickness of the silicon substrate 102 is 575 μm, and the cross section of the silicon substrate is in an inverted right trapezoid structure. The upper electrode layer 105 and the lower electrode layer 103 of the resonator are made of Mo, and the thickness of the Mo is 300 nm.
The preparation method of the resonator comprises the following steps:
step S1, selecting a high-resistance Si substrate as an epitaxial substrate, carrying out acid washing and organic cleaning on the epitaxial substrate to clean the surface of the substrate, and preparing a silicon dioxide supporting layer on the substrate by using a PECVD method; as shown in fig. 1.
Step S2, sputtering or evaporating a lower electrode metal film on the supporting layer based on the step S1, and carrying out graphical processing to obtain a lower electrode layer which is in a pentagonal structure; as shown in fig. 2.
Step S3, on the basis of the step S2, a piezoelectric film is sputtered on the lower electrode layer by utilizing a PVD technology, and photoetching patterning processing is carried out to obtain a piezoelectric layer; as shown in fig. 3.
Step S4, continuing to perform magnetron sputtering on the upper electrode metal film on the piezoelectric layer on the basis of the step S3, and performing graphical processing to obtain an upper electrode layer; as shown in fig. 4.
Step S5, preparing an upper loading layer on the piezoelectric layer based on step S4, so that the upper loading layer is surrounded along the edge of the upper electrode layer; as shown in fig. 5.
Step S6, growing a silicon dioxide passivation layer on the upper electrode layer and the upper loading layer based on step S5; as shown in fig. 6.
Step S7, removing silicon in the working area of the silicon substrate resonator by adopting a back etching process (ICP) to form a cavity and partially expose the supporting layer; as shown in fig. 7.
Step S8, preparing a lower load layer on the support layer based on the step S7, wherein one end of the lower load layer is arranged along the edge of the lower electrode layer in a surrounding mode, and the other end of the lower load layer extends into the cavity; as shown in fig. 8.
Step S9, removing the silicon dioxide protective layer on the top, etching the electrode connecting through hole by using an ICP etching technique, and performing electrical connection by evaporating metal to obtain the FBAR bulk acoustic resonator of the present embodiment.
Fig. 13 is the resonator admittance curve of example 1, without spurious peaks in the resonance region. The parasitic parameters are smaller. The resonance points of the resonator are 2306MHz and 2400MHz, and the quality factor is 1472.
Example 2
As shown in fig. 9 to 10, the present embodiment provides a silicon back-etched FBAR resonator, which is different from embodiment 1 in that: the thickness of the silica support layer 101 is 3.5 μm, and the thickness of the upper support layer 108 is 500 nm; the thickness of the lower supporting layer 106 is 500 nm; the thickness of the single crystal piezoelectric thin film layer 104 is 500 nm. The thickness of the silicon substrate 102 is 575 μm, the thickness of the resonator upper electrode 105 is 800nm, and the thickness of the resonator lower electrode 103 is 800 nm. The upper electrode and the lower electrode are made of Pt, and the upper load layer and the lower load layer are made of Pt.
Fig. 14 is the resonator admittance curve of example 2, without spurious peaks in the resonance region. The parasitic parameters are smaller. The resonance points of the resonator are 4503MHz and 4621MHz, and the quality factor is 1590.
Example 3
This embodiment provides a silicon back-etched FBAR resonator, which is different from embodiment 1 in that: the number of the upper load layers and the number of the lower load layers are respectively 2, the upper load layers and the lower load layers are respectively arranged in a nested mode of surrounding one by one, the interval between adjacent polyhedral frame structures is 0.25 mu m, and the innermost polyhedral frame structure is respectively arranged along the edges of the upper electrode layer and the lower electrode layer in a surrounding mode. The schematic structure is shown in fig. 11 and 12. The resonator obtained by the embodiment adopts 2 load layers, so that the parasitic waveform of the resonance peak can be effectively reduced, and the quality factor is improved.
Comparative example 1
This comparative example differs from example 1 in that the bottom has no cavity. The resonator without the cavity has poor sound reflection capability and cannot form an effective resonance point. As shown in fig. 15, no resonance point is generated in the resonator admittance curve.
Comparative example 2
This comparative example differs from example 1 in that there are no upper and lower support layers. Fig. 16 is a graph of the admittance of the resonator of comparative example 1, as shown, more spurious interference occurs near the resonance point.
In conclusion, the resonator of the invention forms a piezoelectric oscillation sandwich structure through the upper electrode, the piezoelectric layer and the lower electrode, and can reduce the performance loss introduced by an external circuit. And the design of the symmetrical load layer can reduce the energy consumption of the sound wave in the transverse mode in the piezoelectric layer, and the sound wave in the transverse mode in the piezoelectric layer is reflected back to the interior of the piezoelectric oscillation stack from the edge of the device, so that the parasitic waveform of the FBAR resonator at the position of a resonance peak is effectively reduced, and the construction of a high-quality bulk acoustic wave filter with low insertion loss is facilitated. In addition, the invention only needs to prepare the load layer with the same material on the upper electrode and the lower electrode, and does not need to prepare a functional film layer or externally connect a capacitor resistor, thereby reducing the preparation difficulty and further reducing the preparation cost.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A silicon back etched FBAR resonator is characterized in that: the piezoelectric ceramic comprises a silicon substrate, a supporting layer and a piezoelectric layer in sequence from bottom to top; a cavity is formed below the support layer, the support layer is partially exposed in the cavity, and the side wall of the cavity is formed by the silicon substrate; a lower electrode layer is arranged between the supporting layer and the piezoelectric layer, and an upper electrode layer is arranged above the piezoelectric layer; the resonator further comprises an upper load layer and a lower load layer; the upper load layer and the lower load layer are respectively arranged along the edges of the upper electrode layer and the lower electrode layer in a surrounding mode, and the lower load layer penetrates through the supporting layer and extends into the cavity; the upper load layer and the lower load layer are distributed up and down symmetrically.
2. The silicon back-etched FBAR resonator of claim 1, wherein: the thickness of the silicon substrate is 575 mu m, and the cross section of the silicon substrate is of an inverted right trapezoid structure.
3. The silicon back-etched FBAR resonator of claim 1, wherein: the supporting layer is made of silicon dioxide and has a thickness of 2-3.5 μm.
4. The silicon back-etched FBAR resonator of claim 1, wherein: the piezoelectric layer is made of AlN and has the thickness of 500 nm-4 mu m.
5. The silicon back-etched FBAR resonator of claim 1, wherein: the upper electrode layer and the lower electrode layer are made of any one of Mo, Pt, Ti and Au, and the thickness of the upper electrode layer and the lower electrode layer is 50 nm-1 mu m.
6. The silicon back-etched FBAR resonator of claim 1, wherein: the upper load layer and the lower load layer are made of any one of Mo, Pt, Ti and Au, the thickness is 50 nm-2 μm, and the width is 50 nm-10 μm.
7. The silicon back-etched FBAR resonator of claim 6, wherein: the number of the upper load layers and the number of the lower load layers are both 1 or more, and the upper load layers and the lower load layers are in a polyhedral frame structure.
8. The silicon back-etched FBAR resonator of claim 7, wherein: when the number of the upper load layers and the lower load layers is multiple, the polyhedral frame structures are respectively arranged in a nested manner of surrounding one by one, the adjacent polyhedral frame structures are spaced at a certain distance, the outermost layer of the polyhedral frame structures are respectively arranged along the edges of the upper electrode layer and the lower electrode layer in a surrounding manner, and the other layers of the polyhedral frame structures are respectively arranged on the upper electrode layer and the lower electrode layer.
9. A silicon back-etched FBAR resonator as claimed in claim 7 or 8, wherein: the polyhedral frame structure is a regular pentahedral frame structure.
10. The method for manufacturing a silicon back-etched FBAR resonator as claimed in any one of claims 1 to 9, wherein: the method comprises the following steps:
step S1, depositing a support layer on the silicon substrate;
step S2, growing a lower electrode metal film on the supporting layer based on the step S1 and carrying out graphical processing to obtain a lower electrode layer;
step S3, based on step S2, a piezoelectric film is epitaxially grown on the lower electrode layer and is subjected to photoetching and patterning treatment to obtain a piezoelectric layer;
step S4, continuing to grow an upper electrode metal film on the piezoelectric layer based on step S3 and performing a patterning process to obtain an upper electrode layer;
step S5, preparing an upper loading layer on the piezoelectric layer based on step S4, so that the upper loading layer is surrounded along the edge of the upper electrode layer;
step S6, growing a silicon dioxide passivation layer on the upper electrode layer and the upper loading layer based on step S5;
step S7, removing silicon in the working area of the silicon substrate resonator by adopting a back etching process to form a cavity and partially expose the supporting layer;
step S8, preparing a lower load layer on the support layer based on the step S7, wherein one end of the lower load layer is arranged along the edge of the lower electrode layer in a surrounding mode, and the other end of the lower load layer extends into the cavity;
and step S9, removing the top silicon dioxide protective layer to obtain the FBAR bulk acoustic wave resonator.
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| WO2024044926A1 (en) * | 2022-08-30 | 2024-03-07 | 京东方科技集团股份有限公司 | Bulk acoustic resonator and manufacturing method therefor, and filter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024044926A1 (en) * | 2022-08-30 | 2024-03-07 | 京东方科技集团股份有限公司 | Bulk acoustic resonator and manufacturing method therefor, and filter |
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