CN114068810A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN114068810A CN114068810A CN202010742498.4A CN202010742498A CN114068810A CN 114068810 A CN114068810 A CN 114068810A CN 202010742498 A CN202010742498 A CN 202010742498A CN 114068810 A CN114068810 A CN 114068810A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
Abstract
The present application provides a semiconductor structure and a method of forming the same, the semiconductor structure comprising: a substrate including a chip region and a scribe line region; a first plate on the substrate; the second metal adhesion layer is positioned on the surface of the first polar plate; the dielectric layer is positioned on the surface of the second metal adhesion layer; and the second polar plate is positioned on the surface of the dielectric layer, wherein part of the second polar plate positioned in the cutting channel area is in contact with the second metal adhesion layer. According to the semiconductor structure and the forming method thereof, after the dielectric layer is formed, part of the dielectric layer in the cutting channel area is etched to expose the metal adhesion layer, so that the second plate formed subsequently can be in contact with the metal adhesion layer, charges are taken away, the phenomenon that the charges are accumulated on the surface of the dielectric layer to form an arc discharge defect is avoided, and the yield and the reliability of the capacitor are improved.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The capacitor is a passive element commonly used in a very large scale integrated circuit, and mainly includes Polysilicon-Insulator-Polysilicon (PIP), Metal-Insulator-Silicon (MIS), Metal-Insulator-Metal (MIM), and the like. The MIM capacitor has a minimum disturbance to the transistor and provides better Linearity and Symmetry, and thus is more widely used.
However, the current MIM capacitor still has a serious problem of arcing defect during fabrication, and therefore, there is a need to provide a more reliable and efficient solution.
Disclosure of Invention
The application provides a semiconductor structure and a forming method thereof, which can reduce the arc discharge defect of a capacitor and improve the yield and reliability of capacitor products.
One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a chip area and a cutting path area; forming a first polar plate on the substrate; forming a second metal adhesion layer on the surface of the first polar plate; forming a dielectric layer on the surface of the second metal adhesion layer; etching part of the dielectric layer in the cutting path area until the second metal adhesion layer is exposed; and forming a second polar plate on the surface of the dielectric layer and the surface of the exposed second metal adhesion layer.
In some embodiments of the present application, a method of etching a portion of a dielectric layer in a scribe line region to expose a second metal adhesion layer includes: forming a patterned photoresist layer on the surface of the dielectric layer, wherein the patterned photoresist layer defines the position of the second metal adhesion layer to be exposed; etching the dielectric layer by using the patterned photoresist layer as a mask until the second metal adhesion layer is exposed to form an opening; and removing the patterned photoresist layer.
In some embodiments of the present application, the opening is located at a position of a test pad pre-designed in the scribe line region.
In some embodiments of the present application, a proportion of a total area of the openings to a total area of the substrate is equal to or greater than 0.1%.
In some embodiments of the present application, the second metal adhesion layer includes a titanium metal layer on the surface of the first plate and a titanium nitride layer on the surface of the titanium metal layer.
In some embodiments of the present application, the titanium metal layer has a thickness of 40 to 60 angstroms and the titanium nitride layer has a thickness of 400 to 600 angstroms.
In some embodiments of the present application, a bottom surface of the opening is no more than 150 angstroms below a bottom surface of the second metal adhesion layer.
Another aspect of the present application provides a semiconductor structure comprising: a substrate including a chip region and a scribe line region; a first plate on the substrate; the second metal adhesion layer is positioned on the surface of the first polar plate; the dielectric layer is positioned on the surface of the second metal adhesion layer of the chip area and the surface of the second metal adhesion layer of the partial cutting path area; and the second polar plate is positioned on the surface of the dielectric layer and the surface of the second metal adhesion layer which is not covered by the dielectric layer and is positioned in the cutting path area.
In some embodiments of the present application, the position where the second plate and the second metal adhesion layer contact is located at the position of a test pad designed in advance in the dicing lane region.
In some embodiments of the present application, a ratio of a total area of the second plate and the second metal adhesion layer in contact to a total area of the substrate is equal to or greater than 0.1%.
According to the semiconductor structure and the forming method thereof, after the dielectric layer is formed, part of the dielectric layer in the cutting channel area is etched to expose the metal adhesion layer, so that the second plate formed subsequently can be in contact with the metal adhesion layer, charges are taken away, the phenomenon that the charges are accumulated on the surface of the dielectric layer to form an arc discharge defect is avoided, and the yield and the reliability of the capacitor are improved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 12 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
FIG. 1 is a schematic diagram of a semiconductor structure.
Referring to fig. 1, the semiconductor structure includes a substrate 100, and a first metal adhesion layer 110, a first plate 120, a second metal adhesion layer 130, a dielectric layer 140, a second plate 150 and a third metal adhesion layer 160 are sequentially formed on the substrate 100.
A sputtering Physical Vapor Deposition (PVD) process is usually used to form the second plate 150 on the surface of the dielectric layer 140, but during the sputtering PVD process, an arc discharge defect (arcing defect) is generated on the wafer surface. Due to the presence of the dielectric layer 140, charges are more likely to accumulate on the surface of the dielectric layer 140, thereby causing the arcing defects to be more serious. The arc discharge defect can cause the problems of short circuit between circuits and capacitor failure, and the product yield and reliability are seriously influenced.
Arc discharge defects are difficult to completely eliminate in a sputtering physical vapor deposition process, and in some semiconductor structure forming methods, arc discharge defects are reduced or alleviated by monitoring plasma in the sputtering physical vapor deposition and adjusting deposition power and deposition rate, but experiments show that the method has no improvement effect on defects of a capacitor. For a product with a metal-dielectric-metal Capacitor (MIM Capacitor) with a high wafer defect level requirement and a large chip size, the conventional method for forming a semiconductor structure cannot meet the requirements for chip yield and reliability.
In order to solve the above problems, the present application provides a method for forming a semiconductor structure, after a dielectric layer is formed, a portion of the dielectric layer located in a scribe line region is etched to expose a metal adhesion layer, so that a second plate formed subsequently can contact the metal adhesion layer, thereby taking away charges, preventing the charges from accumulating on the surface of the dielectric layer to form an arc discharge defect, and improving the yield and reliability of a capacitor.
Fig. 2 to 12 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure. The method for forming the semiconductor structure according to the present application is described in detail below with reference to the accompanying drawings.
Referring to fig. 2 and 3, wherein fig. 2 is a cross-sectional view of the substrate 200 in fig. 3 along a dotted line XY direction, and fig. 3 is a top view of the substrate 200, the substrate 200 is provided, and the substrate 200 includes a chip region 201 and a scribe line region 202.
In some embodiments of the present application, the substrate 200 may include, but is not limited to, a semiconductor substrate and corresponding active devices (e.g., metal interconnect layers, etc.) formed on the semiconductor substrate.
Referring to fig. 3, the scribe line region 202 surrounds the chip region 201.
Referring to fig. 4, a first metal adhesion layer 210 is formed on a surface of the substrate 200. The first metal adhesion layer 210 may improve adhesion between the substrate 200 and a subsequently formed first plate 220.
In some embodiments of the present application, the method of forming the first metal adhesion layer 210 comprises a sputter physical vapor deposition process.
In some embodiments of the present application, the material of the first metal adhesion layer 210 includes titanium, titanium nitride, tantalum nitride, and the like.
In some embodiments of the present application, the first metal adhesion layer 210 includes a titanium metal layer on the surface of the substrate 200 and a titanium nitride layer on the surface of the titanium metal layer, wherein the titanium metal layer has a thickness of 150 angstroms to 250 angstroms and the titanium nitride layer has a thickness of 200 angstroms to 300 angstroms.
Referring to fig. 5, a first plate 220 is formed on the surface of the first metal adhesion layer 210. The first plate 220 is a lower electrode of the capacitor.
In some embodiments of the present application, the method of forming the first plate 220 comprises a sputter physical vapor deposition process.
In some embodiments of the present application, the material of the first plate 220 includes aluminum or copper, etc.
In some embodiments of the present application, the first plate 220 has a thickness of 2500 to 3000 angstroms, such as 2500 angstroms, 2800 angstroms, 3000 angstroms, 3200 angstroms, 3500 angstroms, or the like.
Referring to fig. 6, a second metal adhesion layer 230 is formed on the surface of the first plate 220. The second metal adhesion layer 230 may increase adhesion between the first plate 220 and a subsequently formed dielectric layer.
In some embodiments of the present application, the method of forming the second metal adhesion layer 230 comprises a sputter physical vapor deposition process.
In some embodiments of the present application, the material of the second metal adhesion layer 230 includes titanium, titanium nitride, tantalum nitride, and the like.
In some embodiments of the present application, the second metal adhesion layer 230 includes a titanium metal layer on the surface of the first plate 210 and a titanium nitride layer on the surface of the titanium metal layer, wherein the thickness of the titanium metal layer is 40 to 60 angstroms, and the thickness of the titanium nitride layer is 400 to 600 angstroms.
Referring to fig. 7, a dielectric layer 240 is formed on the surface of the second metal adhesion layer 230. The dielectric layer 240 serves as an insulating layer between the upper and lower electrodes of the capacitor.
In some embodiments of the present application, the method for forming the dielectric layer 240 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the material of the dielectric layer 240 includes a low-k dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride.
In some embodiments of the present application, the thickness of the dielectric layer 240 is 400 to 500 angstroms, such as 400, 420, 440, 460, 480, or 500 angstroms.
Referring to fig. 8 to 10, a portion of the dielectric layer 240 in the scribe line region 202 is etched until the second metal adhesion layer 230 is exposed. Exposing the second metal adhesion layer 230 can enable a subsequently formed second electrode plate to contact the second metal adhesion layer 230 to carry away charges generated when the second electrode plate is formed, so that the electric arc discharge defect caused by the accumulation of the charges on the surface of the dielectric layer 240 is avoided, and the yield and the reliability of the capacitor are improved.
In some embodiments of the present application, the method of etching the portion of the dielectric layer 240 in the scribe line region 202 to expose the second metal adhesion layer 230 includes: referring to fig. 8, a patterned photoresist layer 250 is formed on the surface of the dielectric layer 240, and the patterned photoresist layer 250 defines the position of the second metal adhesion layer 240 to be exposed; referring to fig. 9, the dielectric layer 240 is etched using the patterned photoresist layer 250 as a mask until the second metal adhesion layer 230 is exposed to form an opening 260; the patterned photoresist layer 250 is removed.
Referring to fig. 8, a method of forming the patterned photoresist layer 250 may include: forming a photoresist layer on the surface of the dielectric layer 240; and developing the photoresist layer.
Referring to fig. 9, a method of etching the dielectric layer 240 includes wet etching or dry etching. The second metal adhesion layer 230 may serve as an etch stop layer for etching the dielectric layer 240 to prevent excessive etching from damaging the first plate 220.
It should be noted that in the actual etching process, since the etching process is not easy to control, the etching may not stop completely on the surface of the second metal adhesion layer 230, but may etch away a portion of the second metal adhesion layer 230. Thus, in some embodiments, the bottom surface of the opening 260 is coplanar with the top surface of the second metal adhesion layer 230; in other embodiments, the bottom surface of the opening 260 may be lower than the top surface of the second metal adhesion layer 230, and the bottom surface of the opening 260 is not more than 150 angstroms lower than the bottom surface of the second metal adhesion layer 230.
In some embodiments of the present application, the opening 260 is located at a position of a test pad previously designed in the scribe line region 202. The opening 260 is located on the scribe line region 202, and does not affect the structure of the chip region 201; further, the opening 260 is located at a position of a test pad pre-designed in the scribe line region 202, and is compatible with a process of forming a test pad in the scribe line region 202 in a subsequent process, and does not affect other positions of the scribe line region 202.
In some embodiments of the present application, the total area of the openings 260 accounts for 0.1% or more of the total area of the substrate 200. If the number and area of the openings 260 are too small, there may still be charges in the areas of the substrate 200 where the density of the openings 260 is low, resulting in arcing defects, and therefore, the number and area of the openings 260 on the substrate 200 are sufficient.
Referring to fig. 11, a second plate 270 is formed on the surface of the dielectric layer 240 and the exposed surface of the second metal adhesion layer 230. The second plate 270 serves as an upper electrode of the capacitor.
In some embodiments of the present application, the method of forming the second plate 270 includes a sputter physical vapor deposition process. Because a part of the second plate 270 is in contact with the second metal adhesion layer 230, charges generated in the process of forming the second plate 270 can be taken away by the second metal adhesion layer 230, so that the charges are prevented from accumulating on the surface of the dielectric layer 240 to form an arc discharge defect, and the yield and the reliability of the capacitor are improved.
In some embodiments of the present application, the material of the second plate 270 includes aluminum or copper.
In some embodiments of the present application, the first plate 270 has a thickness of 1000 angstroms to 1500 angstroms, such as 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, or the like.
Referring to fig. 12, a third metal adhesion layer 280 is formed on the surface of the second plate 270. The third metal adhesion layer 280 may increase adhesion between the second plate 280 and other film layers that are formed later.
In some embodiments of the present application, the method of forming the third metal adhesion layer 280 comprises a sputter physical vapor deposition process.
In some embodiments of the present application, the material of the third metal adhesion layer 280 includes titanium nitride, tantalum nitride, and the like.
In some embodiments of the present application, the material of the third metal adhesion layer 280 is titanium nitride, and the thickness of the third metal adhesion layer 280 is 600 angstroms to 700 angstroms, such as 620 angstroms, 640 angstroms, 660 angstroms, or 680 angstroms.
According to the forming method of the semiconductor structure, after the dielectric layer is formed, part of the dielectric layer located in the cutting channel area is etched until the metal adhesion layer is exposed, so that the second plate formed subsequently can be in contact with the metal adhesion layer, charges are taken away, the phenomenon that the charges are accumulated on the surface of the dielectric layer to form an arc discharge defect is avoided, and the yield and the reliability of the capacitor are improved.
Embodiments of the present application also provide a semiconductor structure, referring to fig. 12, comprising: a substrate 200, wherein the substrate 200 comprises a chip region 201 and a dicing street region 202; a first plate 220 on the substrate 200; a second metal adhesion layer 230 on the surface of the first plate 220; a dielectric layer 240 on the surface of the second metal adhesion layer 230 of the chip region 201 and on the surface of the second metal adhesion layer 230 of the partial dicing lane region 202; a second plate 270 on the surface of the dielectric layer 240 and the surface of the second metal adhesion layer 230 on the scribe line region 202 not covered by the dielectric layer 240.
In some embodiments of the present application, the substrate 200 may include, but is not limited to, a semiconductor substrate and corresponding active devices (e.g., metal interconnect layers, etc.) formed on the semiconductor substrate.
The first metal adhesion layer 210 may improve adhesion between the substrate 200 and the first plate 220.
In some embodiments of the present application, the material of the first metal adhesion layer 210 includes titanium, titanium nitride, tantalum nitride, and the like.
In some embodiments of the present application, the first metal adhesion layer 210 includes a titanium metal layer located on the surface of the substrate 200 and a titanium nitride layer located on the surface of the titanium metal layer, wherein the thickness of the titanium metal layer is 150 angstroms to 250 angstroms, and the thickness of the titanium nitride layer is 200 angstroms to 300 angstroms.
In some embodiments of the present application, the material of the first plate 220 includes aluminum or copper, etc.
In some embodiments of the present application, the first plate 220 has a thickness of 2500 to 3000 angstroms, such as 2500 angstroms, 2800 angstroms, 3000 angstroms, 3200 angstroms, 3500 angstroms, or the like.
The second metal adhesion layer 230 may increase adhesion between the first plate 220 and a subsequently formed dielectric layer.
In some embodiments of the present application, the material of the second metal adhesion layer 230 includes titanium, titanium nitride, tantalum nitride, and the like.
In some embodiments of the present application, the second metal adhesion layer 230 includes a titanium metal layer on the surface of the first plate 210 and a titanium nitride layer on the surface of the titanium metal layer, wherein the thickness of the titanium metal layer is 40 to 60 angstroms, and the thickness of the titanium nitride layer is 400 to 600 angstroms.
In some embodiments of the present application, the material of the dielectric layer 240 includes a low-k dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride.
In some embodiments of the present application, the thickness of the dielectric layer 240 is 400 to 500 angstroms, such as 400, 420, 440, 460, 480, or 500 angstroms.
In some embodiments of the present application, the material of the second plate 270 includes aluminum or copper.
In some embodiments of the present application, the first plate 270 has a thickness of 1000 angstroms to 1500 angstroms, such as 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, or the like.
Because a part of the second plate 270 is in contact with the second metal adhesion layer 230, charges generated in the process of forming the second plate 270 can be taken away by the second metal adhesion layer 230, so that the charges are prevented from accumulating on the surface of the dielectric layer 240 to form an arc discharge defect, and the yield and the reliability of the capacitor are improved.
In some embodiments of the present application, the position where the second plate 270 and the second metal adhesion layer 230 contact is located at the position of a test pad previously designed in the scribe line region 202. The contact position of the second plate 270 and the second metal adhesion layer 230 is located on the dicing street region 202, and the structure of the chip region 201 is not affected; further, the position where the second plate 270 contacts the second metal adhesion layer 230 is located at the position of the pre-designed test pad in the scribe line region 202, which is compatible with a process of forming a test pad in the scribe line region 202 in a subsequent process, and does not affect other positions of the scribe line region 202.
In some embodiments of the present application, a ratio of a total area of the second plate 270 and the second metal adhesion layer 230 in contact with each other to a total area of the substrate is equal to or greater than 0.1%. If the contact area between the second plate 270 and the second metal adhesion layer 230 is too small, charges may still exist in the area of the substrate 200 where the second plate 270 and the second metal adhesion layer 230 are not in contact, and arcing defects may occur, so that the contact area between the second plate 270 and the second metal adhesion layer 230 is sufficient.
The third metal adhesion layer 280 may increase adhesion between the second plate 280 and other film layers that are formed later.
In some embodiments of the present application, the material of the third metal adhesion layer 280 includes titanium nitride, tantalum nitride, and the like.
In some embodiments of the present application, the material of the third metal adhesion layer 280 is titanium nitride, and the thickness of the third metal adhesion layer 280 is 600 angstroms to 700 angstroms, such as 620 angstroms, 640 angstroms, 660 angstroms, or 680 angstroms.
According to the semiconductor structure, the second plate can be in contact with the metal adhesion layer, so that charges are taken away, the phenomenon that the charges are accumulated on the surface of the dielectric layer to form an arc discharge defect is avoided, and the yield and the reliability of the capacitor are improved.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, as the terminology or phraseology of the present specification is to be interpreted by those skilled in the relevant art in light of the teachings of the present specification.
The term "low k" as used herein refers to a low dielectric constant. In the field of semiconductor device structures and fabrication processes, low-k refers to less than SiO2A dielectric constant of (e.g., less than 3.9).
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.
Claims (10)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a chip area and a cutting path area;
forming a first polar plate on the substrate;
forming a second metal adhesion layer on the surface of the first polar plate;
forming a dielectric layer on the surface of the second metal adhesion layer;
etching part of the dielectric layer in the cutting path area until the second metal adhesion layer is exposed;
and forming a second polar plate on the surface of the dielectric layer and the surface of the exposed second metal adhesion layer.
2. The method of forming a semiconductor structure of claim 1, wherein etching a portion of the dielectric layer in the scribe line region to expose the second metal adhesion layer comprises:
forming a patterned photoresist layer on the surface of the dielectric layer, wherein the patterned photoresist layer defines the position of the second metal adhesion layer to be exposed;
etching the dielectric layer by using the patterned photoresist layer as a mask until the second metal adhesion layer is exposed to form an opening;
and removing the patterned photoresist layer.
3. The method of claim 2, wherein the opening is located at a pre-designed test pad in the scribe line region.
4. The method of forming a semiconductor structure according to claim 3, wherein a ratio of a total area of the openings to a total area of the substrate is 0.1% or more.
5. The method of claim 1, wherein the second metal adhesion layer comprises a titanium metal layer on the surface of the first plate and a titanium nitride layer on the surface of the titanium metal layer.
6. The method for forming a semiconductor structure according to claim 5, wherein the titanium metal layer has a thickness of 40 to 60 angstroms, and the titanium nitride layer has a thickness of 400 to 600 angstroms.
7. The method of forming a semiconductor structure of claim 6, wherein a bottom surface of said opening is no more than 150 angstroms below a bottom surface of said second metal adhesion layer.
8. A semiconductor structure, comprising:
a substrate including a chip region and a scribe line region;
a first plate on the substrate;
the second metal adhesion layer is positioned on the surface of the first polar plate;
the dielectric layer is positioned on the surface of the second metal adhesion layer of the chip area and the surface of the second metal adhesion layer of the partial cutting path area;
and the second polar plate is positioned on the surface of the dielectric layer and the surface of the second metal adhesion layer which is not covered by the dielectric layer and is positioned in the cutting path area.
9. The semiconductor structure of claim 8, wherein the second plate and the second metal adhesion layer contact at a location of a pre-designed test pad in the scribe line region.
10. The semiconductor structure of claim 8, wherein a ratio of a total area of the second plate in contact with the second metal adhesion layer to a total area of the substrate is 0.1% or more.
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