CN114068557A

CN114068557A - Memory device

Info

Publication number: CN114068557A
Application number: CN202111392290.5A
Authority: CN
Inventors: 赖惠先; 林昭维; 朱家仪; 童宇诚
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-01-21
Filing date: 2020-01-21
Publication date: 2022-02-18
Also published as: CN111640752A; CN111640752B

Abstract

The invention provides a memory. The memory may be provided with isolation pillars of different heights, for example, a higher first isolation pillar may be provided between two node contacts arranged at the outermost edge and in close proximity, the height of the isolation pillar may be reduced for a node contact inside the memory region, and isolation pillars of different heights may be provided in the peripheral region.

Description

Memory device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a memory.

Background

A Memory, such as a Dynamic Random Access Memory (DRAM), generally has a Memory cell array including a plurality of Memory cells arranged in an array. And the memory further comprises a storage capacitor for storing charge representing stored information, and the memory cells may be electrically connected to the storage capacitor through a node contact, thereby implementing the storage function of each memory cell. However, the structure of the current memory still needs to be further optimized.

Disclosure of Invention

The invention aims to provide a memory so as to optimize the structure of the memory.

To solve the above technical problem, the present invention provides a memory, including:

the device comprises a substrate, a first memory region and a peripheral region, wherein the memory region and the peripheral region are defined on the substrate, and the peripheral region is positioned outside the memory region;

a plurality of isolation pillars formed on the substrate and defining a plurality of node contact windows in the memory region of the substrate; and the number of the first and second groups,

a plurality of node contacts filling the node contact windows;

the isolation columns used for separating the adjacent node contact parts comprise a first isolation column and a second isolation column, and isolation columns formed in the peripheral area form a third isolation column, the top surface of the first isolation column is higher than that of the second isolation column, the top surface of the second isolation column is higher than that of at least part of the third isolation column, and the first isolation column, the second isolation column and the third isolation column are made of the same material.

Optionally, in the third isolation pillar in the peripheral region, a top surface of a part of the third isolation pillar is flush with a top surface of the first isolation pillar.

Optionally, in the third isolation pillar in the peripheral region, a top surface of a part of the third isolation pillar is flush with a top surface of the second isolation pillar.

Optionally, an insulating packed column is arranged between adjacent third isolation columns.

Optionally, the memory further includes: and an electrically conductive layer formed on at least a portion of the third isolation pillar, wherein a top surface of the portion of the third isolation pillar covered by the electrically conductive layer is flush with a top surface of the first isolation pillar.

Optionally, a top surface of the second isolation pillar is lower than a top surface of the node contact.

Optionally, the memory further includes a first shielding layer, and the first shielding layer is at least filled between adjacent independent contacts and located on the second isolation pillar.

The present invention also provides another memory comprising:

and the isolation columns are formed on the substrate and comprise a first isolation column with a first height, a second isolation column with a second height and a third isolation column with a third height, wherein the first isolation column, the second isolation column and the third isolation column are made of the same material, the first height is higher than the second height, and the second height is higher than the third height.

Optionally, the first isolation pillar falls in the memory region.

Optionally, the second isolation pillar falls in the memory region, and the third isolation pillar falls in the peripheral region.

Optionally, the first isolation pillar and the second isolation pillar define a plurality of node contact windows in the memory region. And, the memory further comprises: the node contact windows are filled with a plurality of node contact parts which are arranged in a plurality of rows, each row of node contact parts is filled at the edge of the node contact window, two adjacent node contact parts are connected with each other, the two connected node contact parts form a combined contact part, and the isolation columns arranged at intervals between the two node contact parts in the combined contact part form first isolation columns.

Optionally, node contact portions of the plurality of node contact portions located on a side of the combined contact portion away from the peripheral region constitute independent contact portions, isolation pillars spaced between adjacent independent contact portions constitute second isolation pillars, and a first shielding layer is further formed on top surfaces of the second isolation pillars.

Optionally, two node contacts of the combined contacts are connected at the top of the first isolation pillar and cover the top surface of the first isolation pillar.

Optionally, the top of the third isolation pillar is further covered with a passivation layer.

Optionally, an electrically conductive layer is further formed on a portion of the third isolation pillar, and the passivation layer covers the electrically conductive layer.

In the memory provided by the invention, the device structure of the memory is optimized by arranging the isolation columns with different heights. For example, a higher first isolation pillar may be disposed between two most-edge and immediately adjacent node contacts, the height of the isolation pillar may be reduced for the node contacts inside the memory region, and isolation pillars of different heights may be disposed in the peripheral region.

Drawings

FIG. 1a is a cross-sectional view of a memory device with an isolation pillar and a node contact according to a first embodiment of the present invention;

FIG. 1b is a cross-sectional view of a memory device with a shielding layer according to a first embodiment of the present invention;

FIG. 2 is a flow chart illustrating a method for forming a memory according to a first embodiment of the invention;

FIGS. 3a to 3e are schematic structural diagrams of a memory in a first embodiment of the invention during a manufacturing process thereof;

FIG. 4 is a diagram illustrating a memory structure according to a second embodiment of the present invention;

fig. 5 is a schematic structural diagram of a memory according to a third embodiment of the invention.

Wherein the reference numbers are as follows:

100-a substrate;

100A-memory region;

100B-peripheral zone;

110-a first trench isolation structure;

120-a second trench isolation structure;

210-a combined contact;

220-individual contacts;

200 a-a first conductive layer;

200 b-a second conductive layer;

200 c-a third conductive layer;

300-an isolation column;

310-a first isolation column;

320-a second isolation column;

330-a third isolation column;

400-insulating packed column;

510-a first shielding layer;

520-a second shielding layer;

520' -an isolation sidewall;

530' -an insulating film layer;

610-combined contact window;

620-independent contacts;

630-a peripheral contact;

710-a first graphic;

720-a second graphic;

730-a third graphic;

800-a layer of conductive material;

900-passivation layer.

Detailed Description

The memory and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 1a is a schematic cross-sectional view illustrating a memory device according to a first embodiment of the present invention, wherein an isolation pillar and a node contact are formed, and fig. 1b is a schematic cross-sectional view illustrating a memory device according to a first embodiment of the present invention, wherein a shielding layer is formed. As shown in connection with fig. 1a and 1b, the memory comprises: the semiconductor device includes a substrate 100, a plurality of pillars 300 formed on the substrate 100, and a plurality of node contacts.

Specifically, a plurality of active regions are formed in the substrate 100, and the active regions are arranged in an array, for example, adjacent active regions may be separated from each other by using the first trench isolation structure 110, and memory cells are formed on the active regions based on the active regions. Wherein the active region arranged at the edge position constitutes a first active region AA1, and the active region surrounded by the first active region AA1 constitutes a second active region AA 2.

It should be noted that, due to the limitation of the conventional semiconductor manufacturing process, the quality of the active region (for example, the first active region AA1) arranged at the edge position among the plurality of active regions to be formed is low, and if a memory cell is further manufactured on the active region with low quality, the device performance of the memory cell formed based on the active region at the edge position is affected, so that the memory cell with performance defect needs to be discarded, and at this time, the cost is inevitably wasted.

Based on this, in the present embodiment, at least the active region located at the edge position may be defined as a non-functional active region which is not used to form the memory cell, that is, the non-functional active region includes the first active region AA 1. And a second active region AA2 surrounded by the first active region AA1 is at least partially defined as a functional active region for forming an effective memory cell.

With continued reference to fig. 1a, in the present embodiment, a memory region 100A and a peripheral region 100B located outside the memory region 100A are defined on the substrate 100, and the plurality of active regions are formed in the memory region 100A. A second trench isolation structure 120 is formed in a region where the peripheral region 100B meets the memory region 100A, so as to isolate the semiconductor devices in the memory region 100A from the semiconductor devices in the peripheral region 100B. It should be appreciated that the first active region AA1 arranged at the edge position among the plurality of active regions is correspondingly close to the peripheral region 100B.

It may be considered that an active area of the plurality of active areas closest to the peripheral area 100B constitutes the first active area AA1, and an active area of the plurality of active areas located on a side of the first active area AA distant from the peripheral area 100B constitutes the second active area AA 2.

With continued reference to fig. 1a, a plurality of isolation pillars 300 are formed on the substrate 100 and located in the memory region 100A for defining a plurality of node contacts on the substrate 100, and the plurality of node contacts are aligned in a plurality of rows in a predetermined direction. It is considered that the isolation pillars 300 include an isolation pillar partially extending along a first direction and another isolation pillar partially extending along a second direction, so that the node contact windows can be surrounded by the isolation pillars intersecting in different directions.

Further, in the plurality of isolation pillars 300, the isolation pillars extending along the first direction and the isolation pillars extending along the second direction are, for example, perpendicular to each other, so that the plurality of node contact windows defined by the isolation pillars are aligned in both the first direction and the second direction. At this time, it can be considered that the plurality of node contact windows are arranged in a plurality of rows in both the first direction and the second direction.

With continued reference to fig. 1a, the node contacts fill the node contact windows and are correspondingly arranged in a plurality of rows, and the node contacts are electrically connected to the corresponding active regions. Wherein, two node contacts of the two node contacts filling the most marginal and adjacent node contacts of each row are connected with each other.

As described above, in this embodiment, at least the active region located at the edge position is defined as the nonfunctional active region, and in this case, the node contact located at the edge position and connected to the nonfunctional active region may be correspondingly defined as the nonfunctional contact. Therefore, even if two node contacts at the edge are connected to each other, the device performance of the entire memory is not affected.

In this embodiment, two node contacts which fill the two most marginal node contacts in each row and are connected to each other are defined as a combined contact 210, and a node contact which is located on the side of the combined contact 210 away from the peripheral region 100B in each row is defined as an independent contact 220, and each independent contact 220 fills one node contact.

That is, the combined contact 210, which is formed of the node contacts connected to each other, has a width dimension larger than that of the individual contact 220. For example, the width dimension D1 of the combined contact 210 may be greater than 2 times the width dimension D2 of the individual contacts 220 (i.e., D1 > 2 × D2).

It should be noted that, in the conventional process, when the same conductive material layer is patterned to divide the conductive material layer to form node contacts that are separated from each other, the node contacts located at the edge are usually subjected to a large etching attack, so that the node contacts located at the edge are easily corroded by a large amount to be deformed. Based on this, in the present embodiment, the active region at the edge position is defined as a non-functional active region, and the node contacts at the edge position are connected to form the combined contact 210 with a larger size, so that even if the combined contact 210 is subjected to a larger etching attack, the profile of the combined contact 210 can be ensured. Moreover, under the barrier protection of the combined contact part 210 with a larger width dimension, the problem that the independent contact part 220 adjacent to the combined contact part 210 is excessively corroded can be effectively relieved.

Further, the node contact includes a first conductive layer 200a, a second conductive layer 200b, and a third conductive layer 200 c. The first conductive layer 200a is filled at the bottom of the node contact, and the second conductive layer 200b is located between the first conductive layer 200a and the third conductive layer 200c and covers the bottom surface and at least part of the sidewall of the third conductive layer 200 c.

It should be appreciated that the isolation pillars 300 are used to surround the node contact windows, and the isolation pillars 300 are spaced between the adjacent node contacts. Specifically, the isolation pillars 300 spaced between two node contacts in the combined contacts 210 constitute first isolation pillars 310, and two node contacts in the combined contacts 210 cover the first isolation pillars 310 and are connected to each other on the top surfaces of the first isolation pillars 310. In the present embodiment, in the combined contact 210, two second conductive layers 200b of two node contacts are connected to each other on the top surface of the first isolation pillar 310, and two third conductive layers 200c of two node contacts are connected to each other above the first isolation pillar 310.

And, the isolation pillars 300 spaced between the adjacent independent contacts 220 constitute second isolation pillars 320, and the top surfaces of the second isolation pillars 320 are lower than the top surfaces of the independent contacts 220. In this embodiment, the top surface of second isolation pillar 320 is also lower than the top surface of first isolation pillar 310.

In the present embodiment, as shown in fig. 1a and 1b, the top surfaces of the independent contact 220 and the combined contact 210 are flush, and in this case, the independent contact 220 and the combined contact 210 are both protruded relative to the second isolation pillar 320. Based on this, the memory in this embodiment further includes a first shielding layer 510, where the first shielding layer 510 is at least filled between adjacent independent contacts 220 and located on the second isolation pillar 320. Further, the first shielding layer 510 is also spaced between the individual contact 220 and the combined contact 210.

In addition, the isolation pillar 300 may be further formed in the peripheral region 100B to form a third isolation pillar 330, and at this time, for example, a periphery contact window may be defined in the peripheral region 100B. And, the peripheral contact window is filled with the insulating filling pillars 400, in other words, the insulating filling pillars 400 are spaced between the adjacent third isolation pillars 330.

Optionally, the memory further includes an electrically conductive layer 230, and the electrically conductive layer 230 is formed on at least a portion of the third isolation pillar 330. Wherein the top surface of the portion of the third isolation pillar covered by the electrically conductive layer 230 is higher than the top surface of another portion of the third isolation pillar not covered by the electrically conductive layer 230. In this embodiment, the electrically conductive layer 230 covers the top surface of the third isolation pillar 330 and also extends to cover the adjacent insulated contact pillar 400, and the top surfaces of the third isolation pillar and the insulated contact pillar covered by the electrically conductive layer 230 are higher than the top surfaces of the third isolation pillar and the insulated contact pillar that are not covered by the electrically conductive layer 230.

In this embodiment, the electrically conductive layer 230 closest to the memory region 100A and the combined contact 210 are spaced apart from each other, and the top surfaces of the third isolation pillar 330 and the insulating fill pillar 400 between the electrically conductive layer 230 and the combined contact 210 are recessed with respect to the top surface of the node contact to define a recess between the electrically conductive layer 230 and the combined contact 210. More specifically, the top surfaces of the third isolation pillars 330 and the insulating filler pillars 400, which are located between the electrically conductive layer 230 and the combined contact 210, are more depressed with respect to the top surfaces of the third isolation pillars 330 and the insulating filler pillars 400 covered by the electrically conductive layer 230.

It should be noted that the number of the third isolation pillars 330 and the number of the insulating filling pillars 400 between the electrically conductive layer 230 and the combined contact 210 may be adjusted according to actual conditions (i.e., the number of the third isolation pillars 330 and the number of the insulating filling pillars 400 corresponding to the grooves may be adjusted according to actual conditions). For example, in the present embodiment, two third isolation pillars 330 and two insulation filling pillars 400 are provided between the electrically conductive layer 230 and the combined contact 210. And the number of the third isolation pillars and the insulating filling pillars covered by the electrically conductive layer 230 can be adjusted to 1 or more accordingly. In this embodiment, the electrically conductive layer 230 is covered with 2 third isolation pillars and 1 insulating filling pillar.

Specifically, the top surfaces of the third isolation pillars 330 and the insulated contact pillars 400, which are not covered by the electrically conductive layer 230, may be flush with the top surfaces of the second isolation pillars 320, for example. And, the top surfaces of the third isolation pillar 330 and the insulated contact pillar 400 covered by the electrically conductive layer 230 may be, for example, flush with the top surface of the first isolation pillar 310.

With continued reference to fig. 1a and 1b, the electrically conductive layer 230 includes a first electrically conductive layer and a second electrically conductive layer, and the first electrically conductive layer and the second electrically conductive layer are sequentially stacked on the third isolation pillar 330 and the insulating packed pillar 400.

The second conductive layer 300b and the third conductive layer 300c in the electrically conductive layer 230 and in the node contact portion can be simultaneously formed by a patterning process based on the same conductive material layer. The method of forming the electrically conductive layer 230 and the node contact will be described in detail below.

With continued reference to fig. 1b, the memory further comprises a second shielding layer 520, wherein the second shielding layer 520 at least fills the groove between the electrically conductive layer 230 and the combined contact 210.

In a further aspect, a plurality of electrically conductive layers 230 may be formed in the peripheral region 100B, and the heights of the third isolation pillars 330 and the insulating filling pillars 400 located between adjacent electrically conductive layers 230 are also correspondingly lower, based on which the second shielding layer 520 is also filled between adjacent electrically conductive layers 230.

The method for forming the memory device according to the present embodiment will be described in detail with reference to fig. 2 and fig. 3a to 3 e. Fig. 2 is a schematic flow chart of a method for forming a memory according to a first embodiment of the invention, and fig. 3a to 3e are schematic structural diagrams of the memory according to the first embodiment of the invention during a manufacturing process thereof.

In step S100, referring to fig. 3a specifically, a substrate 100 is provided, a memory region 100A and a peripheral region 100B are defined on the substrate 100, and the peripheral region 100B is located outside the memory region 100A.

Specifically, a plurality of active regions are formed in the memory region 100A of the substrate 100, and adjacent active regions may be separated from each other by a first trench isolation structure 110, for example. Wherein, an active region arranged at an edge position among the plurality of active regions constitutes a first active region AA1, and an active region located at a side of the first active region AA1 away from the peripheral region constitutes a second active region AA 2.

In this embodiment, the active region at the edge position may be defined as a non-functional active region which is not used to form the memory cell, i.e., the non-functional active region includes the first active region AA 1. And a second active region AA2 surrounded by the first active region AA1 is at least partially defined as a functional active region for forming a memory cell.

Further, a second trench isolation structure 120 may be formed in the substrate at the periphery of the active area array, so as to isolate the active area array in the memory area 100A from the devices in the peripheral area 100B.

In step S200, with continued reference to fig. 3a, a plurality of isolation pillars 300 are formed on the substrate 100, and a plurality of node contact windows are defined on the substrate 100, and the node contact windows are aligned in a plurality of rows in a predetermined direction. In this embodiment, the plurality of node contacts are formed in the memory region 100A.

As described above, the isolation pillars 300 may include an isolation pillar partially extending along a first direction and another isolation pillar partially extending along a second direction, so that the node contact windows may be surrounded by the isolation pillars intersecting in different directions. The isolation pillars extending along the first direction and the isolation pillars extending along the second direction are, for example, perpendicular to each other, so that the plurality of node contact windows defined can be aligned in both the first direction and the second direction. At this time, it can be considered that the plurality of node contact windows are arranged in a plurality of rows in both the first direction and the second direction.

In this embodiment, two node contacts located at the edge most and adjacent to each other in each row of node contacts are jointly defined as a combined contact 610, and a node contact located at a side of the combined contact 610 away from the peripheral region 100B in each row is defined as an independent contact 620.

With continued reference to FIG. 3a, a plurality of isolation pillars 300 are formed in the memory region 100A to define a plurality of node contacts (including a combination contact 610 and an independent contact 620) in the memory region 100A, and the isolation pillars 300 are also formed in the periphery region 100B to define a periphery contact 630 in the periphery region 100B. Further, in this step, the top surfaces of the plurality of isolation pillars 300 (including the isolation pillars formed in the memory region 100A and the isolation pillars formed in the peripheral region 100B) are flush.

In a further embodiment, as shown in fig. 3b, the peripheral contact 630 is further filled with an insulating filling pillar 400.

In this embodiment, after defining the node contact, further etching the bottom of the node contact so that the bottom of the node contact further extends into the active region of the substrate 100.

In step S300, referring specifically to fig. 3c to 3d, a plurality of node contacts are formed, the node contacts fill the node contact windows and are arranged in a plurality of rows, and two node contacts of each row, which fill the two node contact windows that are most edge-most and adjacent, are connected to each other.

In this embodiment, two node contacts that are filled with the two most marginal node contacts in each row and are connected to each other are jointly defined as a combined contact 210, and a node contact located on a side of the combined contact 210 away from the peripheral region 100B in each row is defined as an independent contact 220, and each independent contact 220 is filled with one node contact. It is also understood that the two node contacts filled in the combined contact 610 are connected to each other to constitute the combined contact 210, and the node contacts filled in the individual contacts 620 constitute the individual contacts 220.

With continued reference to fig. 3d, the node contact includes a first conductive layer 200a, a second conductive layer 200b, and a third conductive layer 200 c. The first conductive layer 200a is filled at the bottom of the node contact to be electrically connected to the active region. The second conductive layer 200b covers the top surface of the first conductive layer 200a and the sidewalls of the node contact windows. The third conductive layer 200c is formed on the second conductive layer 200b and fills the node contact, and the third conductive layer 200c further extends upward beyond the node contact to protrude from the node contact.

Specifically, the method for forming the node contact portion includes the following steps.

In a first step, as shown in fig. 3c, a first conductive layer 200a is formed on the bottom of the node contact. The material of the first conductive layer 200a includes, for example, polysilicon.

A second step, continuing to refer to fig. 3c, forming a conductive material layer 800, wherein the conductive material layer 800 fills the node contact window and covers the top surface of the isolation pillar 300. In this embodiment, the conductive material layer 800 is formed not only in the memory region 100A but also in the peripheral region 100B to cover the isolation pillars 300 and the insulating filling pillars 400 in the peripheral region 100B.

The conductive material layer 800 may specifically include a lower conductive material layer and an upper conductive material layer stacked up and down. Specifically, the material of the lower conductive material layer includes, for example, titanium nitride, the material of the upper conductive material layer is, for example, a metal layer, and further, the material of the metal layer may include tungsten.

In this embodiment, the conductive material layer 800 may be a planarized film layer, so as to utilize the patterning precision of the conductive material layer 800.

In a third step, continuing with reference to fig. 3c, a patterned mask layer is formed on the conductive material layer 800. Wherein, the patterned mask layer is, for example, a patterned photoresist layer.

Specifically, the patterned mask layer includes at least a first pattern 710 and a second pattern 720, and both the first pattern 710 and the second pattern 720 are formed in the memory region 100A. The first pattern 710 covers the top of the combined contact to define a pattern of the combined contact, and at this time, the first pattern 710 also covers the isolation pillar 300 between two node contacts in the combined contact correspondingly. And, the second pattern 720 covers the isolated contact window to define the pattern of the isolated contact.

Further, the width dimension of the first graphic 710 is correspondingly greater than the width dimension of the second graphic 720 (e.g., the width dimension of the first graphic 710 is greater than 2 times the width dimension of the second graphic 720).

It should be noted that, when forming the patterned mask layer, the first pattern 710 at the edge position also has the problem of being over-developed, thereby affecting the pattern accuracy of the first pattern 710. In contrast, in the present embodiment, the width of the first pattern 710 is larger than the width of the second pattern 720, so that the first pattern 710 can be ensured to meet the size requirement even after being over-developed. And, under the blocking protection of the first pattern 710 with a larger width dimension, the over-development of the second pattern 720 is avoided, and the pattern precision of the second pattern 720 is ensured.

Optionally, the patterned mask layer further includes a third pattern 730, and the third pattern 730 is formed in the peripheral region 100B to define a pattern of an electrically conductive layer in the peripheral region 100B.

A fourth step, specifically referring to fig. 3d, etching the conductive material layer 800 by using the patterned mask layer as a mask, so as to separate the conductive material layers corresponding to different node contact windows from each other, thereby forming a combined contact 210 and an independent contact 220 separated from each other. At this time, the width dimension of the combined contact 210 is correspondingly greater than the width dimension of the individual contacts 220, for example, the width dimension D1 of the combined contact 210 may be greater than 2 times the width dimension D2 of the individual contacts 220 (i.e., D1 > 2 × D2).

Also, when the conductive material layer 800 is etched, the node contact at the edge position may be subjected to a large etching attack, so that the node contact at the edge position may be easily deformed by being greatly corroded. Based on this, in the present embodiment, two adjacent node contacts located at the edge are connected to form the combined contact 210 with a larger size, so that even if the combined contact 210 is subjected to a larger etching attack, the profile of the combined contact 210 can be ensured. Moreover, under the barrier protection of the combined contact part 210 with a larger width dimension, the problem that the independent contact part 220 adjacent to the combined contact part 210 is excessively corroded can be effectively relieved.

In this embodiment, when the patterned mask layer is used as a mask to etch the conductive material layer 800, an electrically conductive layer 230 corresponding to the third pattern 730 is formed in the peripheral region 100B.

Referring to fig. 3e, in a further embodiment, after etching the conductive material layer to expose the isolation pillars 300, the method further includes: the pillars 300 are etched to a predetermined depth. By further etching the isolation pillars 300 between adjacent node contacts, the conductive material between adjacent node contacts can be effectively removed to ensure the mutual separation between adjacent node contacts.

In the present embodiment, the isolation pillars 300 between the adjacent independent contacts 220 are exposed, the isolation pillars 300 between the combined contact 210 and the adjacent independent contacts 220 are also exposed, and the isolation pillars between two node contacts in the combined contact 210 are not exposed. Based on this, when the isolation pillars 300 are etched, the heights of the isolation pillars 300 between the adjacent independent contacts 220 and the isolation pillars 300 between the combined contact 210 and the adjacent independent contacts 220 are all reduced, and a second isolation pillar 320 can be formed; and, the isolation pillar between the two node contacts in the combined contact 210 is not etched, and constitutes a first isolation pillar 310 with a higher height.

With continued reference to fig. 3e, in the peripheral region 100B, the electrically conductive layer 230 covers a portion of the isolation pillar and also extends to cover the adjacent insulating filled pillar 400. Accordingly, when the isolation pillars 300 are etched, the isolation pillars and the insulating filling pillars 400 that are not covered by the electrically conductive layer 230 are also simultaneously etched, so that the heights of the isolation pillars and the insulating filling pillars 400 that are not covered by the electrically conductive layer 230 are correspondingly reduced. Wherein the isolation pillars in the peripheral region 100B constitute third isolation pillars 330.

Further, after etching the isolation pillars 300, a first shielding layer 510 is formed between the independent contacts 220, and also between the independent contacts 220 and the combined contact 210.

In this embodiment, when the first shielding layer 510 is formed, a second shielding layer 520 is further formed, and the second shielding layer 520 is at least filled between the electrically conductive layer 230 and the combined contact 210. It should be appreciated that when a plurality of electrically conductive layers 230 are formed in the peripheral region 100B, the second shielding layer 520 also fills between adjacent electrically conductive layers 230.

Example two

The difference from the first embodiment is that, in the embodiment, in the groove between the combined contact portion and the electrically conductive layer, an isolation sidewall is formed on the sidewall of the groove, so that the isolation sidewall at least covers the sidewall of the combined contact portion near the peripheral region.

Fig. 4 is a schematic structural view of a memory according to a second embodiment of the invention, and as shown in fig. 4, the top surfaces of the third isolation pillars and the insulating filling pillars between the electrically conductive layer 230 and the combined contact 210 are lower, so as to define a groove between the electrically conductive layer 230 and the combined contact 210. At this time, a portion of the sidewall of the combined contact portion 210 facing the peripheral region is exposed to the groove. And, the sidewall spacers 520 'are formed on the sidewalls of the grooves, so that the sidewall spacers 520' correspondingly cover at least a portion of the sidewalls of the combined contact portions 210.

Further, an insulating film 530 ' is formed on the bottom wall of the groove, and the insulating film 530 ' covers the top surface of the third isolation pillar and the top surface of the insulating filled pillar in the groove and is connected to the bottom of the isolation sidewall 520 '.

The isolation sidewall 520 'and the insulating film 530' may be formed simultaneously with the first shielding layer 510 formed in the memory region 100A. Specifically, the forming method of the first shielding layer 510, the isolation sidewall spacers 520 'and the insulating film layer 530' includes the following steps, for example.

A first step of forming an insulating material layer filling the gaps between adjacent individual contacts 220 and filling the gaps between the individual contacts 220 and the combined contact 210 and also filling at least the recess between the combined contact 210 and the electrically conductive layer 230, and the top surface of the insulating material layer also protruding upwards above the node contact top surface.

A second step of performing an etch-back process to remove portions of the insulating material layer above the node contacts and to leave portions of the insulating material layer filled between adjacent individual contacts 220 and portions filled between the individual contacts 220 and the combined contacts 210, so as to form a first shielding layer 510; and, by the etching back process, partially removing the insulating material layer in the groove to form the isolation sidewall 520 'on the sidewall of the groove, and leaving a portion of the insulating material layer at the bottom of the groove to form an insulating film 530'.

In an optional scheme, after the forming of the isolation sidewall spacers 520', the method further includes: a passivation layer 900 is formed, and the passivation layer 900 fills the groove to correspondingly cover the isolation sidewall 520 'and the insulating film 530'. And, the passivation layer 900 may also be made to cover the first shielding layer 510 and the node contact in the memory region 100A.

EXAMPLE III

The difference from the second embodiment is that in the embodiment, in the groove not covered by the electrically conductive layer, the top surface of the third isolation pillar covered by the isolation sidewall is higher than the top surface of the third isolation pillar not covered by the isolation sidewall.

Fig. 5 is a schematic structural diagram of a memory according to a third embodiment of the present invention, and as shown in fig. 5, the isolation side wall 520 'is formed on the side wall of the groove, and the bottom of the isolation side wall 520' further partially covers the third isolation pillar 330 located in the groove. Wherein, in the groove, the top surface of the third isolation pillar covered by the isolation sidewall 520 'is higher than the top surface of the third isolation pillar not covered by the isolation sidewall 520'.

That is, the plurality of different pillars in the present embodiment have at least three different heights. Wherein in the peripheral region, a top surface of a portion of the third isolation pillars is flush with a top surface of the first isolation pillars; a top surface of a portion of the third isolation pillar is flush with a top surface of the second isolation pillar; and, a portion of the top surface of the third isolation pillar is more sunken relative to the top surface of the second isolation pillar.

Specifically, in the present embodiment, the top position of the first isolation pillar 310 located between two node contacts in the combined contact 220 is located at the first height position H1, and the top position of the third isolation pillar covered by the electrically conductive layer 230 in the peripheral region 100B is also located at the first height position H1. And, a groove is formed in a region of the peripheral region 100B not covered by the electrically conductive layer 230, and a top position of a third isolation pillar covered by the isolation sidewall 520' in the groove is located at a second height position H2, and a top position of the second isolation pillar 320 in the memory region 100A is also located at a second height position H2. Further, the top position of the third isolation pillar not covered by the isolation sidewall 520' in the groove is located at a third height position H3. Wherein the first height position H1 is higher than the second height position H2, the second height position H2 is higher than the third height position H3.

In this embodiment, in the groove not covered by the electrically conductive layer 230, not only the third isolation pillar but also the insulating filling pillar 400 are exposed from the isolation sidewall 520'. At this time, similar to the third isolation pillar, in the groove, the top surface of the insulating filled pillar covered by the isolation sidewall 520 'is higher than the top surface of the insulating filled pillar not covered by the isolation sidewall 520'. That is, the plurality of different insulating packed columns in this embodiment also have at least three different heights, respectively.

Further, similar to the second embodiment, the isolation sidewall spacers 520' and the first shielding layer 510 formed in the memory region 100A may be formed at the same time. Specifically, when the etch-back process is performed, a portion of the insulating material layer covering the bottom of the groove may be completely removed to form the isolation sidewall spacers 520', and expose the third isolation pillar and the insulating material layer. And after exposing the third isolation pillars and the insulating material layer, further etching the third isolation pillars and the insulating material layer to reduce the height of the third isolation pillars and the insulating material layer, which are not covered by the isolation spacers 520', to a third height position H3.

It should be noted that the groove in this embodiment and the groove in the second embodiment have different opening sizes, for example (specifically, the opening size of the groove in this embodiment may be larger than the opening size of the groove in the second embodiment). Thus, when performing the etch-back process to remove the portion of the insulating material layer higher than the node contact portion, the isolation sidewall 520' can be formed for the recess with a larger opening size, and the insulating material layer at the bottom of the recess can be completely removed; and, for the groove with smaller opening size, a part of the insulating material layer may still remain on the bottom of the groove to form the insulating film 530'.

Similarly, after the isolation sidewall spacers 520 'are formed, a passivation layer 900 may be further formed to fill the grooves to correspondingly cover the isolation sidewall spacers 520', the third isolation pillars, and the insulation filling pillars.

In summary, in the memory as described above, the two node contacts filled in the two node contacts closest to each other at the edge of each row are connected to each other to form a combined contact. In this case, it is equivalent to make the width dimension of the combined contact portion at the edge position larger than the width dimension of the individual contact portions arranged inside. Therefore, when the node contact parts are prepared, even if the combined contact parts at the edge positions are easily corroded by a large amount, the appearance of the combined contact parts can be still ensured, and under the blocking protection of the combined contact parts with larger widths, the situation that other node contact parts are corroded by a large amount can be avoided, the appearance precision of the independently arranged node contact parts is improved, and the improvement of the device performance of the formed memory is facilitated.

In a further aspect, the active region at the edge position may be further defined as a non-functional active region, and the node contact at the edge position may also be correspondingly connected to the non-functional active region, in this case, the node contact at the edge position may be defined as a non-functional contact. Based on this, even if the two node contacts located at the edge position are connected to each other, the device performance of the entire memory is not affected.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A memory, comprising:

a plurality of node contacts filling the node contact windows;

2. The memory of claim 1, wherein in a third isolation pillar located in a peripheral region, a top surface of a portion of the third isolation pillar is flush with a top surface of the first isolation pillar.

3. The memory of claim 1, wherein in a third isolation pillar located in a peripheral region, a top surface of a portion of the third isolation pillar is flush with a top surface of the second isolation pillar.

4. The memory of claim 1, wherein adjacent third isolation pillars are spaced with insulating filler pillars.

5. The memory of claim 1, further comprising an electrically conductive layer formed on at least a portion of the third isolation pillars, wherein a top surface of a portion of the third isolation pillars covered by the electrically conductive layer is flush with a top surface of the first isolation pillars.

6. The memory of claim 1, wherein a top surface of the second isolation pillar is lower than a top surface of the node contact.

7. The memory of claim 6, further comprising a first shielding layer filled at least between adjacent ones of the isolated contacts and on the second isolation pillars.

8. A memory, comprising:

9. The memory of claim 8, wherein the first isolation pillar falls in a memory region.

10. The memory of claim 8, wherein the second isolation pillars fall in a memory region and the third isolation pillars fall in a peripheral region.

11. The memory of claim 8, wherein the first and second isolation pillars define a plurality of node contact windows in the memory region;

and, the memory further comprises: the node contact windows are filled with a plurality of node contact parts which are arranged in a plurality of rows, each row of node contact parts is filled at the edge of the node contact window, two adjacent node contact parts are connected with each other, the two connected node contact parts form a combined contact part, and the isolation columns arranged at intervals between the two node contact parts in the combined contact part form first isolation columns.

12. The memory of claim 11, wherein a node contact portion of the plurality of node contact portions on a side of the combined contact portion away from the peripheral region constitutes an independent contact portion, an isolation pillar spaced between adjacent independent contact portions constitutes a second isolation pillar, and a first shielding layer is further formed on a top surface of the second isolation pillar.

13. The memory of claim 11, wherein two node contacts of the combination contacts connect at a top of the first isolation pillar and cover a top surface of the first isolation pillar.

14. The memory of claim 8, wherein the top of the third isolation pillar is further covered with a passivation layer.

15. The memory of claim 14, wherein an electrically conductive layer is further formed on a portion of the third isolation pillar, the passivation layer overlying the electrically conductive layer.

16. The memory of claim 8, wherein adjacent third isolation pillars are spaced with insulating filler pillars.