CN114063933A

CN114063933A - Block management method, memory controller and memory storage device

Info

Publication number: CN114063933A
Application number: CN202111456734.7A
Authority: CN
Inventors: 林家添
Original assignee: Shenzhen Baojiale Electronic Technology Co ltd
Current assignee: Shenzhen Baojiale Electronic Technology Co ltd
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2022-02-18
Anticipated expiration: 2041-12-02
Also published as: CN114063933B

Abstract

The invention provides a block management method, a memory controller and a memory storage device; the method comprises the following steps: the method comprises the steps of obtaining respective latest read time information of a plurality of entity blocks, dividing the entity blocks into a plurality of first groups according to the time information, dividing each first group into a plurality of second groups according to the number information of times that the entity blocks in the first groups are read in unit time, establishing a table for managing the number of times that the entity blocks in the unit time are read, carrying out sorting operation on the entity blocks in the second groups according to the table, enabling the arrangement sequence of the entity blocks in the second groups to be arranged according to the sequence of the number of times that the entity blocks are read from the first groups to the second groups, and establishing a logic-to-entity mapping table of the entity blocks in the second groups, wherein the number of times that the entity blocks are read from the second groups is arranged according to the sequence of the number of times that the entity blocks are read from the second groups to the third groups. Therefore, the read-write speed of the memory storage device can be improved.

Description

Block management method, memory controller and memory storage device

Technical Field

The present invention relates to the field of storage devices, and in particular, to a block management method, a memory controller, and a memory storage device.

Background

With the push of the internet, the digital popularization range is wider and wider, the data types are diversified, the structure is more and more complicated, the data volume is larger and larger, the impact on the reading performance of the server storage system is inevitably brought, and especially the requirements on the response time, the throughput, the unit time request processing capacity and the like of the storage system reading are higher and higher.

The digitization and the rapid application of big data in real-world situations make various application scenarios put higher demands on the storage system as a whole. The traditional load scene mainly based on writing gradually shifts towards the reading intensive direction, and is particularly embodied in the fields of e-commerce, various short and large video applications and the like.

The Nand flash memory is selected in the storage field of simple movable and embedded equipment due to the advantages of low power consumption, small size, shock resistance, falling resistance, high access speed and the like. The Nand Flash memory takes a block as an erasing unit and a page as a programming unit, new data written in must be erased into a block, the data are respectively written in a page and a page, and in the device taking the Nand Flash memory as a storage medium, the efficiency of garbage recycling management can be improved by effectively carrying out the distinguishing operation of cold data and hot data, so that the service life of the Nand Flash memory is prolonged, and the integral reading and writing performance of the device is improved.

If a mechanism exists, data frequently used by the system (namely, hot data) can be collectively read, so that the reading speed of the data is improved.

Based on this, the present application provides a method for managing entity blocks storing data, which can be used in various memory storage devices, preferably in a storage device of a server and an enterprise-level storage device, by performing detailed management on the entity blocks storing data to improve data reading speed.

Disclosure of Invention

The embodiment of the invention provides a block management method, a memory controller and a memory storage device; therefore, the read-write speed of the memory storage device is improved.

An embodiment of the present invention provides a block management method for a memory storage device, wherein the memory storage device includes a memory module, the memory module includes a plurality of physical blocks, the block management method includes: obtaining respective latest read time information of the plurality of physical blocks; dividing the plurality of physical blocks into a plurality of first groups according to the time information; dividing each first group into a plurality of second groups according to the information of the number of times that the entity blocks in the plurality of first groups are read in unit time; establishing a table for managing the times of reading the entity blocks in the unit time, wherein the table records the details of the times of reading the entity blocks in each second group in the unit time; sorting the entity blocks in the second group according to the table of the times of reading the entity blocks in the unit time, so that the entity blocks in the second group are arranged in the sequence of the times of reading; establishing a logic-to-entity mapping table of entity blocks in the second group, wherein the entity blocks are arranged in sequence from at least one read time; therefore, the read-write speed of the memory storage device is improved.

An embodiment of the present invention further provides a memory controller for controlling a memory storage device, wherein the memory storage device includes a memory module, the memory module includes a plurality of physical blocks, and the memory controller includes: a host interface for connecting to a host system; a memory interface for connecting to the memory module; and a memory control circuit connected to the host interface and the memory interface; wherein the memory control circuit is configured to obtain respective most recently read time information of the plurality of physical blocks; the memory control circuitry is also to divide the plurality of physical blocks into a plurality of first groups according to the time information; the memory control circuit is also used for dividing each first group into a plurality of second groups according to the information of the number of times the entity blocks in the plurality of first groups are read in unit time; the memory control circuit is further configured to establish a table for managing the number of times the physical blocks are read in a unit time, and details of the number of times the physical blocks in each second group are read in the unit time are recorded in the table; the memory control circuit is further used for carrying out sorting operation on the entity blocks in the second group according to the table of the number of times the entity blocks are read in the unit time, so that the arrangement sequence of the entity blocks in the second group is arranged according to the sequence of the number of times the entity blocks are read; the memory control circuit is further configured to establish a logical-to-physical mapping table of physical blocks in the second group, the physical blocks being arranged in a sequence of a plurality of read times.

An embodiment of the present invention further provides a memory storage device, including: a memory module comprising a plurality of physical blocks; a connection interface for connecting to a host system; and a memory controller connected to the memory module and the connection interface, wherein the memory controller is configured to obtain respective most recently read time information of the plurality of physical blocks; the memory controller is also used for dividing the plurality of entity blocks into a plurality of first groups according to the time information; the memory controller is also used for dividing each first group into a plurality of second groups according to the information of the number of times the entity blocks in the plurality of first groups are read in unit time; the memory controller is further configured to establish a table for managing the number of times the physical blocks are read in a unit time, and details of the number of times the physical blocks in each second group are read in the unit time are recorded in the table; the memory controller is further used for carrying out sorting operation on the entity blocks in the second group according to the table of the number of times the entity blocks are read in the unit time, so that the arrangement sequence of the entity blocks in the second group is arranged according to the sequence of the number of times the entity blocks are read; the memory controller is further configured to establish a logical-to-physical mapping table of physical blocks in the second group, the physical blocks being arranged in a sequence of a plurality of read times.

Based on the above, the latest read time information of the entity blocks is obtained, the entity blocks are divided into a plurality of first groups according to the time information, each first group is divided into a plurality of second groups according to the number information of times that the entity blocks in the plurality of first groups are read in unit time, a table for managing the number of times that the entity blocks in the unit time are read is established, the entity blocks in the second groups are sorted according to the table, so that the entity blocks in the second groups are arranged in the sequence of the number of times that the entity blocks are read, and a logical-to-entity mapping table of the entity blocks in the second groups is established. Therefore, the read-write speed of the memory storage device is improved.

Drawings

FIG. 1 is a schematic diagram of a memory storage device according to one embodiment of the present invention;

FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the invention;

FIG. 3 is a schematic diagram illustrating a management memory module according to an embodiment of the invention;

FIG. 4 is a diagram illustrating grouping and dividing physical blocks into a plurality of first groups within a unit time according to an embodiment of the invention;

FIG. 5 is a diagram illustrating a table of a first group queue according to an embodiment of the invention;

FIG. 6 is a diagram illustrating a first group queue sorted by the size of the time read according to an embodiment of the invention;

fig. 7 is a schematic diagram illustrating that a first group queue is divided into second groups according to different times per unit time according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a table of a second group queue according to an embodiment of the invention;

FIG. 9 is a diagram illustrating a table of a second group queue according to an embodiment of the invention;

FIG. 10 is a schematic diagram illustrating a management memory module according to an embodiment of the invention;

fig. 11 is a flow chart illustrating a block entitlement method in accordance with one embodiment of the present invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a memory storage device shown in accordance with an embodiment of the present invention. Referring to fig. 1, a memory storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 may be any type of computer system. For example. The host system 11 can be various electronic systems such as a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, and a digital camera. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 may include a solid state disk, a U-disk, a memory card, or other type of non-volatile storage device. The host system 11 may be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express), a Universal Serial Bus (USB), or other types of connection interfaces. Thus, the host system 11 may store data to the memory storage device 12 and/or read data from the memory storage device 12.

Memory storage device 12 may include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, the connection interface 121 may support connection interface standards such as SATA, PCI Express, or USB. The memory storage device 12 may communicate with the host system 11 via the connection interface 121.

The memory module 122 is used to store data. Memory module 122 may include memory module 122. The memory module 122 includes an array of memory cells. The memory cells in the memory module 122 store data in the form of voltages. For example, the memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi-Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, or other memory modules with similar characteristics.

The memory controller 123 is connected to the connection interface 121 and the memory module 122. Memory controller 123 may be used to control memory storage device 12. For example, the memory controller 123 can control the connection interface 121 and the memory module 122 for data access and data management. For example, the memory controller 123 may include a Central Processing Unit (CPU), or other Programmable general purpose or special purpose microprocessor, Digital Signal Processor (DSP), Programmable Logic controller (ASIC), Programmable Logic Device (PLD), or other similar Device or combination thereof.

In one embodiment, memory controller 123 is also referred to as a flash memory controller. In an embodiment, memory module 122 is also referred to as a flash memory module. The memory module 122 can receive a sequence of instructions from the memory controller 123 and access the memory cells according to the sequence of instructions.

FIG. 2 is a schematic block diagram of a memory controller according to an embodiment of the invention. Referring to fig. 2, the memory controller 123 includes a memory control circuit 1233, a host interface 1231, and a memory interface 1232.

The memory control circuit 1233 is used to control the overall operation of the memory controller 123. Specifically, the memory control circuit 1233 has a plurality of control commands, and the control commands are executed to write, read and erase data during operation of the memory storage device 12. When the operation of the memory control circuit 1233 is described below, the operation of the memory controller 123 is equivalently described.

In the present embodiment, the control instructions of the memory control circuit 1233 are operated in a firmware manner. For example, the memory control circuit 1233 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are programmed into the read only memory. When the memory storage device 12 is in operation, the control instructions are executed by the microprocessor unit to perform data writing, reading, and erasing operations.

In another embodiment, the control instructions of the memory control circuitry 1233 may also be stored in the form of program code in a particular region of the memory module 122 (e.g., a system region of the memory module dedicated to storing system data). Further, the memory control circuit 1233 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory controller 123 is enabled, the MCU first executes the boot code to load the control instructions stored in the memory module 122 into the RAM of the memory control circuit 1233. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another embodiment, the control instructions of the memory control circuit 1233 can also be operated in a hardware manner. For example, the memory control circuit 1233 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the memory module 122. The memory write circuit is configured to issue a write command sequence to the memory module 122 to write data into the memory module 122. The memory read circuit is used to issue a sequence of read commands to the memory module 122 to read data from the memory module 122. The memory erase circuit is used to issue an erase command sequence to the memory module 122 to erase data from the memory module 122. The data processing circuit is used for processing data to be written into the memory module 122 and data read from the memory module 122. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes, respectively, and are used to instruct the memory module 122 to perform corresponding operations of writing, reading, and erasing. In one embodiment, the memory control circuitry 1233 may also issue other types of command sequences to the memory module 122 to instruct the corresponding operations to be performed.

The host interface 1231 is electrically connected to the memory control circuit 1233 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted from the host system 11 are transmitted to the memory control circuit 1233 through the host interface 1231. In the present embodiment, the host interface 1231 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 1231 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 1232 is electrically connected to the memory control circuit 1233 and is used for accessing the memory module 122. That is, the data to be written into the memory module 122 is converted into a format accepted by the memory module 122 through the memory interface 1232. Specifically, if the memory control circuit 1233 is to access the memory module 122, the memory interface 1232 transmits a corresponding sequence of instructions. For example, the sequences of instructions may include a write sequence of instructions to indicate writing data, a read sequence of instructions to indicate reading data, an erase sequence of instructions to indicate erasing data, and corresponding sequences of instructions to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). Such sequences of instructions may be generated, for example, by memory control circuitry 1233 and transferred to memory module 122 via memory interface 1232. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

In this embodiment, the memory controller 123 may perform single-frame (single-frame) encoding on the data stored in the same physical program unit, or may perform multi-frame (multi-frame) encoding on the data stored in a plurality of physical program units. Depending on the encoding algorithm employed, the memory controller 123 may encode the data to be protected to generate corresponding error correction codes and/or error check codes.

In one embodiment, the memory controller 123 further includes a buffer 1235, an error checking and correcting circuit 1234 and a power management circuit 1236. The buffer 1235 is electrically connected to the memory control circuit 1233 and is used for temporarily storing data and instructions from the host system 11 or data from the memory module 122. The power management circuit 1236 is electrically connected to the memory control circuit 1233 and is used for controlling the power of the memory storage device 12. The error checking and correcting circuit 1234 is electrically connected to the memory control circuit 1233 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory control circuit 1233 receives a write command from the host system 11, the error checking and correcting circuit 1234 generates a corresponding Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for the data corresponding to the write command, and the memory control circuit 1233 writes the data corresponding to the write command and the corresponding error correcting code and/or error detecting code into the memory module 122. Thereafter, when the memory control circuit 1233 reads data from the memory module 122, the corresponding error correction code and/or error check code is simultaneously read, and the error checking and correcting circuit 1234 performs an error checking and correcting operation on the read data according to the error correction code and/or error check code.

FIG. 3 is a schematic diagram illustrating a management memory module according to an embodiment of the invention. Referring to fig. 1 to 3, the memory module 122 includes a plurality of physical blocks 301(0) - (301 a), each of the physical blocks 301(0) - (301 a) includes a plurality of memory cells for non-volatile data storage. Each physical block includes a plurality of memory cells and is used for non-volatile storage of data. For example, a physical block may include one or more physical blocks. Each physical block may include a plurality of physical programming units. A physical programming unit may include one or more physical pages. A plurality of memory cells in a physical programming cell can be programmed simultaneously to store data. In addition, all memory cells in a physical block can be erased simultaneously. The erased physical block is also referred to as a free physical block (or free block) and may be used to store new data (e.g., data from host system 11).

In one embodiment, the physical blocks 301(0) - (301A) may belong to the same memory die or to different memory dies. Each physical block is respectively provided with a plurality of physical programming units, wherein the physical programming units belonging to the same physical block can be independently written and simultaneously erased. However, it should be understood that the present invention is not limited thereto, and each physical block may be composed of 64 physical program units, 256 physical program units, or any other physical program units.

In more detail, the physical block is the minimum unit of erase. That is, each physical block contains one of the minimum number of and erased memory cells. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit field includes a plurality of physical access addresses for storing user data, and a redundancy (redundancy) bit field for storing system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physical block is a physical block, and the physical programming unit is a physical page (page) or a physical sector (sector), but the invention is not limited thereto.

Exemplarily, where a is a positive integer, which is the sequence number or address value of the physical block 301, such as 301(1) the physical block 301 with sequence number or address value of 2; 301(a) represents a physical block 301 with a sequence number or address value a + 1; the memory module 122 includes a plurality of physical blocks 301(0) - (301A), and specifically, the memory module 122 includes a total of A +1 physical blocks. For example, in the memory module 122 with a capacity size of 64G, a may be 1728, the number of physical program units in the physical block is 1254, and each physical program unit is 16 KB.

In one embodiment, the memory control circuitry 1233 logically groups the physical blocks 301(0) - (301A) into a data region 31, an idle region 33, a system region 35, and a replacement region 37.

It should be understood that, in describing the operation of the physical blocks of the memory module 122, it is a logical concept to operate the physical blocks by words such as "extract", "group", "partition", "associate", and the like. That is, the physical locations of the physical blocks of the memory module 122 are not changed, but the physical blocks of the memory module 122 are logically operated.

The physical blocks logically belonging to the data area 31 and the idle area 33 are used for storing data from the host system 11. Specifically, the physical block of the data area 31 is regarded as the physical block of the stored data, and the physical block of the spare area 33 is used to replace the physical block of the data area 31. That is, when receiving a write command and data to be written from the host system 11, the memory control circuit 1233 replaces the physical block of the data area 31 by extracting the physical block from the idle area 33 to write the data. When receiving a read command and data to be read from the host system 11, the memory control circuit 1233 reads data from the physical blocks in the data area 31 according to the corresponding logical-to-physical mapping table.

The physical blocks logically belonging to the system area 35 are used for recording system data. For example, the system data includes information about the manufacturer and model of the memory module 122, the number of physical blocks of the memory module 122, the number of physical programming units per physical block, and the like.

The physical blocks logically belonging to the replacement area 37 are used in the bad block replacement procedure to replace the damaged physical blocks. Specifically, if there are normal physical blocks in the replacement area 37 and the physical blocks in the data area 31 are damaged, the memory control circuit 1233 extracts the normal physical blocks from the replacement area 37 to replace the damaged physical blocks.

In one embodiment, the number of physical blocks in the data area 31, the idle area 33, the system area 35 and the replacement area 37 may vary according to different memory specifications. Moreover, it should be understood that the grouping relationship of the physical blocks associated with the data area 31, the idle area 33, the system area 35 and the replacement area 37 may dynamically change during the operation of the memory storage device 12. For example, when a physical block in the idle area 33 is damaged and replaced by a physical block in the replacement area 37, the physical block in the replacement area 37 is associated with the idle area 33.

In one embodiment, as shown in fig. 3, the memory control circuit 1233 may be configured with a plurality of logic units 302(0) - (302B) to map the entity blocks storing valid data of the entity blocks 301(0) - (301 a). For example, a logical unit may consist of one or more logical addresses. The mapping relationship between logical units and physical blocks can be recorded in a logical-to-physical mapping table (L2P table). The physical blocks logically belonging to the data area 31 and the idle area 33 are used for storing data from the host system 11.

The physical blocks logically belonging to the data area 31 and the idle area 33 are used for storing data from the host system 11. Specifically, the physical block of the data area 31 is regarded as the physical block of the stored data, and the physical block of the spare area 33 is used to replace the physical block of the data area 31. That is, when receiving a write command and data to be written from the host system 11, the memory control circuit 1233 extracts the physical block from the idle area 33 according to the corresponding logical-to-physical mapping table to write the data, so as to replace the physical block of the data area 31. When receiving a read command and data to be read from the host system 11, the memory control circuit 1233 reads data from the physical blocks in the data area 31 according to the corresponding logical-to-physical mapping table.

Based on this, the present application proposes a method for managing entity blocks storing data in the data area 31, which can be used in various storage devices, preferably in storage devices of servers and enterprise-level storage devices, by performing detailed management on the entity blocks storing data to improve the data reading speed.

In one embodiment, the physical blocks included in the data area 31 are 301(0) -302 (C), C < A.

The memory control circuit 1233 can obtain the data storage information of the physical blocks 301(0) - (302 (C)). For example, the address value information of the physical block storing the data, the address value information of the physical programming units storing the data in the physical block, and the entire physical programming units of which physical programming units only store the data in a partial capacity. In an embodiment, the data storage information of the physical block may also include other types of information as long as the data storage condition of the physical block can be reflected.

Illustratively, also in the above case of the memory module 122 with a capacity size of 64G, it has 1728 physical blocks, the number of physical program units in each physical block is 1254, and each physical program unit is 16KB in size. If the number of physical blocks in the data area 31 is 1200, the remaining physical blocks are grouped into the idle area 33, the system area 35 and the replacement area 37 by a certain number.

The memory control circuit 1233 can obtain the data storage information of the physical blocks 301(0) - (302) (1200) as follows: the entity blocks 301(100) store data, the entity programming units P1000 in the entity blocks 301(100) store data, and the entity programming units P1001-P1254 do not store data; the physical program unit P800 has a total physical program unit capacity of 16KB, and only stores 4KB of data.

In one embodiment, the memory control circuitry 1233 can obtain the data storage information of the physical blocks 301(0) - (302 (C)) as well as the time and the number of times the physical block was last read. The memory control circuit 1233 may divide the physical blocks 301(0) - (301C) into a plurality of groups according to the obtained data storage information.

Specifically, in one embodiment, the memory control circuit 1233 may divide the physical blocks 301(0) - (301 (C) into a plurality of first groups, which are denoted as 41 (1) -41 (M), according to the time T at which the physical blocks are recently read. Each first group may include one or more physical blocks, and the time value of each physical block that is read most recently can only belong to a certain first group. The time at which each of the first groups was most recently read is different. The number of the physical blocks included in each first group may be the same or different. At a certain time point, the physical blocks belonging to the same first group have the same latest read time value, while the physical blocks belonging to different first groups have different latest read time values. In addition, after the first group is divided, the first group to which a certain physical block belongs may be dynamically changed, rather than being permanently fixed.

For example, the memory control circuit 1233 divides the physical blocks 301(0) -301 (C) into 10 first groups 41 (1) -41 (10) according to the 10 time values of the data in the physical blocks that have been read recently. With 10 first groups as shown in figure 4. Specifically, the time values are T1 is less than or equal to 1S, T2 is more than or equal to 1S, T3 is more than or equal to 5S, T4 is more than or equal to 5S, T3 is more than or equal to 5S, T4 is more than 30S and more than or equal to 60S, T5 is more than or equal to 120S, T6 is more than 120S and less than or equal to 300S, T7 is more than 300S and less than or equal to 600S, T8 is more than or equal to 600S, T9 is more than or equal to 1800S, and T10 is more than 7200S. In FIG. 4, the group 41 (1) indicates that the physical blocks of the physical blocks 301(0) - (301C) whose data has been read recently with the time value T1 ≦ 1S are divided into a group including the physical blocks 301(0) - (301D); group 41 (2) indicates that the physical blocks 301(0) - (301C) whose data has been read recently with time value 1S < T2 ≦ 5S are divided into a group including the physical blocks 301(K) - (301 (E); similarly, the group 41 (3) indicates that the physical blocks of the physical blocks 301(0) - (301C) whose data has been read recently with the time value 5S < T3 ≦ 30S are divided into a group (not shown); similarly, the group 41 (4) indicates that the physical blocks of the physical blocks 301(0) - (301C) whose data has been read recently with the time value 30S < T4 ≦ 60S are divided into a group (not shown); similarly, the group 41 (5) indicates that the physical blocks of the physical blocks 301(0) - (301C) whose data has been read recently with the time value 60S < T5 ≦ 120S are divided into a group (not shown); similarly, the group 41 (6) indicates that the physical blocks of the physical blocks 301(0) - (301C) whose data has been read recently with the time value 120S < T6 ≦ 300S are divided into a group (not shown); similarly, the group 41 (7) indicates that the physical blocks of the physical blocks 301(0) - (301C) whose data has been read recently with the time value 300S < T7 ≦ 600S are divided into a group (not shown); similarly, the group 41 (8) represents that the physical blocks of the physical blocks 301(0) - (301C) whose data has been read recently with the time value 600S < T8 ≦ 1800S are divided into a group (not shown); similarly, the group 41 (9) indicates that the physical blocks of the physical blocks 301(0) - (301C) whose data has been read recently with the time value 1800S < T9 ≦ 7200S are divided into a group (not shown); group 41 (10) indicates that the physical blocks 301(0) - (301C) in which the data has been read recently with the time value of 7200S < T10 ≦ 21600S are divided into a group including the physical blocks 301(L) - (301C).

In one embodiment, the memory control circuit 1233 further establishes a table for managing the first group queues, and the table records a time detail of the latest data read of the physical blocks in each first group. Exemplary, 10 of the first groups 41 (1) -41 (10) are shown in FIG. 5.

In an embodiment, the number of the physical blocks in each first group is divided by the time of being read, so that it can be known that the number of the physical blocks in each first group may be the same or different. For example, the time in the group 41 (1) is the minimum, and the number of the physical blocks in the group 41 (1) may be the maximum or the minimum of all the 10 first groups. In general, it may depend on whether the data area stores large files or small files; the present application is not specifically limited herein.

In one embodiment, the number of first groups is greater than 1, i.e., there are a plurality of first groups. The memory control circuit 1233 may construct a first group queue according to the time corresponding to the first group, wherein the group with short time is arranged at the front of the group queue, the group with longest time is arranged at the tail of the group queue, and so on to manage all the first group queues, as shown in fig. 6.

In one embodiment, the memory control circuit 1233 establishes and maintains a first group queue after grouping the physical blocks in the data region 31 according to the time values at which the data was most recently read. Further, the memory control circuit 1233 may preset a time threshold and discard the first group of the first group queues exceeding the time threshold from the first group queue. For example, 41 (H) in the data area 31 is not read for more than 30 days, and as time is delayed, more data may be read for more than 30 days, and the original group for managing such data is disassembled and is generally divided into one group 41 (J) or no group division is performed on such data. The performance of the memory control circuit 1233 is focused on the management of the physical blocks with the smallest access time in the data area 31, so as to improve the reading speed of such data. On one hand, the group management in the first group queue is convenient, and the group queue with the same length has finer time-separated groups, so that the group management is more refined; on the other hand, the power consumption of the memory control circuit 1233 in managing the first group queue can be reduced.

In one embodiment, the physical block address values in each group may or may not be consecutive. For example, if the data is a large file, the large file needs to occupy a larger storage space, i.e. needs a plurality of physical blocks to store it; when the read time is used to divide the data, a first group 41 (F) with consecutive physical block address values is obtained; if the data is a small file, the small file only needs to occupy a small storage space, i.e. only needs fewer physical blocks to store the small file; when the read time is used to divide the data, a first group 41 (G) with discontinuous physical block address values is obtained.

In one embodiment, the memory control circuit 1233 may group the physical blocks in the data region 31 according to time, so as to obtain the groups 41 (1) -41 (M). Further, the memory control circuit 1233 may further divide each of the groups 41 (1) -41 (M) into a plurality of groups according to the number V of times the physical blocks in the groups 41 (1) -41 (M) are read in a unit time, so as to obtain a second group 51 (1) -51 (W). Each second group may include one or more physical blocks, and each physical block in each second group in each unit time can only belong to a certain second group by the number of times of being read recently. Further, the number of times of the most recent reading of each of the second groups per unit time is different. The number of the physical blocks included in each second group may be the same or different. At a certain time point, the physical blocks belonging to the same second group have the same number of times of being recently read, while the physical blocks belonging to different second groups have different numbers of times of being recently read. In addition, after the second group is divided, the second group to which a certain physical block belongs may be dynamically changed, rather than being permanently fixed.

For example, the values of V1, V2, and V3 respectively indicate the number of times data in 1S is read, and the values of V1, V2, and V3: v1 is less than or equal to 10, V2 is more than 10 and less than or equal to 50, and V3 is more than 50 and less than or equal to 100. The first group 41 (1) is further divided into groups according to V1 ≤ 10, 10 < V2 ≤ 50, and 50 < V3 ≤ 100 to obtain second groups 51 (1), 51 (2), 51 (3); as shown in fig. 7.

Further, in an embodiment, the memory control circuit 1233 further establishes a table managing the number of times the data in the physical blocks in the unit time is read, and the table records details of the number of times the data in the physical blocks in each second group is read in the unit time. Illustratively, as shown in FIG. 8, FIG. 8 shows a detailed description of the number of times data within 1S has been read.

Further, in one embodiment, the memory control circuit 1233 performs the sorting operation on the physical blocks in the second group according to the table of the number of times data in the physical blocks in the unit time is read, so that the physical blocks in the second group are arranged in the order of the number of times. And sorting the physical blocks in the second group so that the physical blocks with the largest times are arranged in the front of the second group queue. To improve the fineness of data management and thus speed at which subsequent data is read.

Illustratively, as shown in fig. 9, the group 51 (3) is arranged at the front of the queue of the group 41 (1) because the data in 1S is read more times than the data in 51 (2) and 51 (1); 51 (3) has more physical blocks 301(D) than other physical blocks in the group 51 (3), so that the physical blocks 301(D) are arranged at the front of the queue of the group 51 (3); similarly, the physical block 301 (N) in the group 51 (2) is also arranged in front of the group 51 (2); the physical block 301 (R) in the group 51 (1) is also arranged in front of the group 51 (1) in which it is located.

Further, the read command from the host system 11 can be divided into a continuous read operation mode and a random read operation mode. Wherein the random read operation mode indicates that the host system 11 is continuously issuing a plurality of read commands to the memory module 122 to respectively perform a plurality of read operations, and the mapping information required for each read operation is dispersedly stored in a plurality of different logical-to-physical mapping tables. In the related art, to perform the random read operation, the memory control circuit 1233 needs to read a plurality of different logical-to-physical mapping tables according to the logical addresses respectively corresponding to the plurality of read operations, which makes the speed of performing the random read operation slower and affects the speed of reading data. Specifically, the method manages the physical blocks, and then reestablishes the logical-to-physical mapping table of the managed physical blocks, so that the mapping information of the physical blocks with the largest number of data reading times in a unit time is stored in the same logical-to-physical mapping table, thereby increasing the reading speed of the data, even if the reading instruction of the data is a random reading operation instruction.

For example, as shown in fig. 10, the memory control circuit 1233 may configure a plurality of logic units 302 (S), 302 (T), and 302 (U) to map the entity blocks storing valid data among the entity blocks 301(X), 301(Y), and 301 (Z). For example, a logical unit may consist of one or more logical addresses. The mapping relationship between logical units and physical blocks can be recorded in a logical-to-physical mapping table (L2P table). The physical blocks 301(X), 301(Y), and 301(Z) represent physical blocks that are read a large number of times per unit time; wherein the magnitude relation of the number of times of reading in unit time is 301(X) > 301(Y) > 301 (Z).

Fig. 11 is a flowchart illustrating a block management method according to an embodiment of the invention. Referring to fig. 11, in step S100, respective latest read time information of the plurality of physical blocks is obtained;

in step S200, dividing the plurality of physical blocks into a plurality of first groups according to the time information; further, after dividing the plurality of physical blocks into a plurality of first groups according to the time information, a first group queue is also constructed, the group with short time is arranged in front of the group queue, and the group with longest time is arranged at the tail of the group queue; preferably, after the first group queue is constructed, a time threshold is preset and the first group in the first group queue exceeding the time threshold is eliminated from the first group queue.

In step S300, dividing each of the first groups into a plurality of second groups according to information of the number of times that the physical blocks in the first groups are read in a unit time; preferably, the most recently read time value of each physical block can only belong to a certain first group; the time that each first group was most recently read is different; preferably, each first group or second group may include one or more physical blocks, and the number of physical blocks included in each first group or second group may be the same or different.

In step S400, a table for managing the number of times the physical block is read in a unit time is established, and details of the number of times the physical block in each second group is read in the unit time are recorded in the table; in step S500, sorting the physical blocks in the second group according to the table of the number of times the physical blocks are read in the unit time, so that the arrangement order of the physical blocks in the second group is arranged according to the order of the number of times the physical blocks are read;

in step S600, a logical-to-physical mapping table of the physical blocks in the second group, which are arranged in order of the number of times of reading from the first group to the second group, is established.

However, the steps in fig. 11 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 11 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 11 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.

To sum up, the memory control circuit 1233 first divides the data in the physical block into a plurality of different first groups according to the latest reading time of the data in the physical block, and the memory control circuit 1233 can construct a first group queue according to the time corresponding to the first group, where the group with short time is arranged in front of the group queue, the group with longest time is arranged at the tail of the group queue, and so on to manage all the first group queues; then dividing each group in the first group according to different recently read times in preset time to obtain a second group of the recently read times in unit time; further, the memory control circuit 1233 performs a sorting operation on the physical blocks in the second group according to the table of the number of times data in the physical blocks in the unit time is read, so that the arrangement order of the physical blocks in the second group is arranged according to the order of the number of times. Sorting the physical blocks in the second group so that the physical blocks with the most times are arranged in the front of the second group queue; further, the method manages the entity blocks to improve the fineness of data management, and then reestablishes the logic-to-entity mapping table of the managed entity blocks, so that the mapping information of the entity blocks with the largest number of data reading times in a unit time is stored in the same logic-to-entity mapping table, and the reading speed of the data is improved even if the reading instruction of the data is a random reading operation instruction.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solution of the present invention, and not for limiting the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A block management method for a memory storage device, wherein the memory storage device comprises a memory module, the memory module comprises a plurality of physical blocks, the block management method comprises:

obtaining respective latest read time information of the plurality of physical blocks;

dividing the plurality of physical blocks into a plurality of first groups according to the time information;

dividing each first group into a plurality of second groups according to the information of the number of times that the entity blocks in the plurality of first groups are read in unit time;

establishing a table for managing the times of reading the entity blocks in the unit time, wherein the table records the details of the times of reading the entity blocks in each second group in the unit time;

sorting the entity blocks in the second group according to the table of the times of reading the entity blocks in the unit time, so that the entity blocks in the second group are arranged in the sequence of the times of reading;

and establishing a logic-to-entity mapping table of entity blocks in the second group, wherein the entity blocks are arranged in sequence from at least one read time.

2. A block management method according to claim 1, wherein said dividing the plurality of physical blocks into a plurality of first groups according to the time information further constructs a first group queue, a group with a shorter time is arranged at the front of the group queue, and a group with a longest time is arranged at the rear of the group queue.

3. A block management method according to claim 2, wherein after the first group queue is constructed, a time threshold is further preset and the first group in the first group queue exceeding the time threshold is discarded from the first group queue.

4. A block management method according to claim 1, wherein the most recently read time value of each physical block belongs to only a first group; the time at which each of the first groups was most recently read is different.

5. A block management method according to claim 1, wherein the number of times each physical block in each second group in each unit time has been read recently belongs to only one second group; the number of times of the most recent reading of each of the second groups per unit time is different.

6. A block management method according to claim 1, wherein each of the first groups or the second groups comprises one or more physical blocks, and the number of the physical blocks in each of the first groups or the second groups may be the same or different.

7. A memory controller for controlling a memory storage device, wherein the memory storage device comprises a memory module, the memory module comprises a plurality of physical blocks, and the memory controller comprises:

a host interface for connecting to a host system;

a memory interface for connecting to the memory module; and

a memory control circuit connected to the host interface and the memory interface;

wherein the memory control circuit is configured to obtain respective most recently read time information of the plurality of physical blocks;

the memory control circuitry is also to divide the plurality of physical blocks into a plurality of first groups according to the time information;

the memory control circuit is also used for dividing each first group into a plurality of second groups according to the information of the number of times the entity blocks in the plurality of first groups are read in unit time;

the memory control circuit is further configured to establish a table for managing the number of times the physical blocks are read in a unit time, and details of the number of times the physical blocks in each second group are read in the unit time are recorded in the table;

the memory control circuit is further used for carrying out sorting operation on the entity blocks in the second group according to the table of the number of times the entity blocks are read in the unit time, so that the arrangement sequence of the entity blocks in the second group is arranged according to the sequence of the number of times the entity blocks are read;

the memory control circuit is further configured to establish a logical-to-physical mapping table of physical blocks in the second group, the physical blocks being arranged in a sequence of a plurality of read times.

8. The memory controller of claim 7, wherein the first group queue is further constructed after the plurality of physical blocks are divided into a plurality of first groups according to the time information, the group with the shorter time is arranged at the front of the group queue, and the group with the longest time is arranged at the tail of the group queue.

9. The memory controller of claim 8, wherein a time threshold is also preset after the first group queue is constructed, and the first group of the first group queue exceeding the time threshold is eliminated from the first group queue.

10. The memory controller of claim 7, wherein the most recently read time value of each physical block belongs to only a first group; the time at which each of the first groups was most recently read is different.

11. The memory controller according to claim 7, wherein each physical block in each second group in each unit time is read only recently for a certain second group; the number of times of the most recent reading of each of the second groups per unit time is different.

12. The memory controller of claim 7, wherein each of the first group or the second group comprises one or more physical blocks, and the number of physical blocks in each of the first group or the second group may be the same or different.

13. A memory storage device, comprising:

a memory module comprising a plurality of physical blocks;

a connection interface for connecting to a host system; and

a memory controller connected to the memory module and the connection interface,

wherein the memory controller is configured to obtain respective most recently read time information of the plurality of physical blocks;

the memory controller is also used for dividing the plurality of entity blocks into a plurality of first groups according to the time information;

the memory controller is also used for dividing each first group into a plurality of second groups according to the information of the number of times the entity blocks in the plurality of first groups are read in unit time;

the memory controller is further configured to establish a table for managing the number of times the physical blocks are read in a unit time, and details of the number of times the physical blocks in each second group are read in the unit time are recorded in the table;

the memory controller is further used for carrying out sorting operation on the entity blocks in the second group according to the table of the number of times the entity blocks are read in the unit time, so that the arrangement sequence of the entity blocks in the second group is arranged according to the sequence of the number of times the entity blocks are read;

the memory controller is further configured to establish a logical-to-physical mapping table of physical blocks in the second group, the physical blocks being arranged in a sequence of a plurality of read times.

14. The memory storage device of claim 13, wherein the dividing of the plurality of physical blocks into a plurality of first groups according to the time information further comprises constructing a first group queue, wherein the groups with shorter time are arranged at the front of the group queue, and the groups with longest time are arranged at the tail of the group queue.

15. The memory storage device of claim 14, wherein after the first group queue is constructed, a time threshold is also preset and the first group of the first group queue exceeding the time threshold is eliminated from the first group queue.

16. The memory storage device of claim 13, wherein each physical block has been read only recently for a time value belonging to a first group; the time at which each of the first groups was most recently read is different.

17. The memory storage device of claim 13, wherein each physical block in each second group in each unit time is read only recently for a certain second group; the number of times of the most recent reading of each of the second groups per unit time is different.

18. The memory storage device of claim 13, wherein each first group or second group comprises one or more physical blocks, and wherein the number of physical blocks in each first group or second group may be the same or different.