CN114050816B

CN114050816B - Circuit for preventing I2C interface from backward flowing current

Info

Publication number: CN114050816B
Application number: CN202210029906.0A
Authority: CN
Inventors: 唐瑞
Original assignee: Shenzhen Betterlife Electronic Science And Technology Co ltd
Current assignee: Shenzhen Betterlife Electronic Science And Technology Co ltd
Priority date: 2022-01-12
Filing date: 2022-01-12
Publication date: 2022-04-22
Anticipated expiration: 2042-01-12
Also published as: CN114050816A

Abstract

The invention discloses a circuit for preventing an I2C interface from flowing backward current, relates to the technical field of analog circuits, and solves the technical problem of the I2C communication interface flowing backward current. The invention comprises a first switch gating circuit, a second switch gating circuit, a power tube connected between the first switch gating circuit and the second switch gating circuit, and a bias tube connected with the second switch gating circuit and the power tube; the bias tube is used for providing bias voltage for the power tube; the first switch gating circuit is used for providing an I2C interface voltage or a chip power supply voltage for the power tube; the second switch gating circuit is used for providing an I2C interface voltage or a bias voltage for the power tube. The invention can effectively prevent the I2C interface from backward flowing current into the chip power supply circuit, avoid ESD risk caused by changing the IO port circuit of the chip and ensure normal power-on and work of the chip.

Description

Circuit for preventing I2C interface from backward flowing current

Technical Field

The invention relates to the technical field of digital-analog hybrid chips, in particular to a circuit for preventing current from flowing backwards through an I2C interface.

Background

In the digital-analog mixed chip application, the communication of I2C is often required, so chip pins of SDA and SCL are reserved on the IO port for I2C communication. On an application board integrated with a plurality of chips, a master control controls the plurality of chips to select functions of the application board. As shown in fig. 1, after the power of the power supply voltage Vdd of a chip is cut off by the master, I2C still performs normal communication, i.e. the I2C port still has power.

Because the IO port has pull-up and pull-down capability, a parasitic diode leakage path also exists at the same time, the power supply voltage of the IO port is defined as IOVCC, as shown in fig. 2, which is a schematic diagram of a conventional chip I2C interface leakage path, and the parasitic diode of the PMOS pull-up transistor can leak to IOVCC and then to the chip ground Vss. This situation can cause the power-off chip to face a serious problem of the I2C port sinking current from the IO port of the chip. This causes unnecessary current consumption, and Vdd always has a voltage value, and at this time, Vdd power up of the chip cannot start to power up from 0V, which may cause the Vdd of the chip to go back and forth to reset up and down, and affect the normal power-up operation timing of the chip.

Disclosure of Invention

The invention aims to provide a circuit for preventing an I2C interface from backward flowing current so as to solve the technical problems in the prior art. The technical effects that can be produced by the preferred technical scheme in the technical schemes provided by the invention are described in detail in the following.

In order to achieve the purpose, the invention provides the following technical scheme:

the invention provides a circuit for preventing I2C interface from flowing backward current, which is used for preventing the current of a chip I2C interface from flowing backward to a circuit of a chip power supply end, and comprises a first switch gating circuit, a second switch gating circuit, a power tube connected between the first switch gating circuit and the second switch gating circuit, and a bias tube connected with the second switch gating circuit and the power tube; the bias tube is used for providing bias voltage for the power tube; the first switch gating circuit is used for providing an I2C interface voltage or a chip power supply voltage for the power tube; the second switch gating circuit is used for providing an I2C interface voltage or the bias voltage for the power tube; the source electrode of the bias tube is connected with the source electrode of the power tube and the first switch gating circuit and is connected with the power supply voltage of the chip; the drain electrode and the grid electrode of the bias tube are both connected with the second switch gating circuit, and the substrate of the bias tube is connected with a power supply; and the drains of the first switch gating circuit, the second switch gating circuit and the power tube are all connected and connected with the I2C interface voltage.

Preferably, the source, the substrate, and the drain of the power transistor are all connected to the first switch gating circuit, and the gate and the drain thereof are all connected to the second switch gating circuit.

Preferably, the first switch gating circuit includes a third NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; the source electrode and the substrate of the third NMOS tube are both grounded, and the drain electrode of the third NMOS tube is connected with the grid electrode of the fourth PMOS tube and the drain electrode of the sixth PMOS tube; the substrate and the source of the sixth PMOS tube MP6 are both connected with the source of the fifth PMOS tube and are connected with the I2C interface voltage; the grid electrode of the third NMOS tube and the grid electrode of the sixth PMOS tube are connected to a power-on reset signal of the chip; and the source electrode and the substrate of the fourth PMOS tube are connected with the drain electrode and the substrate of the fifth PMOS tube, and a first output port is arranged at the joint.

Preferably, the substrate of the power transistor is connected to the first output port, the drain of the power transistor is connected to the source of the fifth PMOS transistor, and the source of the power transistor is connected to the drain of the fourth PMOS transistor.

Preferably, the second switch gating circuit comprises a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a ninth PMOS transistor; the source electrode of the fourth NMOS tube is connected with the drain electrode of the seventh PMOS tube and is connected with the I2C interface voltage; the drain electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are connected in sequence; the drain electrode of the sixth NMOS tube is connected with the source electrode of the ninth PMOS tube and is connected with the bias voltage; the drain electrode of the ninth PMOS tube, the source electrode of the eighth PMOS tube, the drain electrode of the eighth PMOS tube and the source electrode of the seventh PMOS tube are sequentially connected; the substrate of the fourth NMOS tube, the substrate of the fifth NMOS tube and the substrate of the sixth NMOS tube are all grounded; the substrate of the ninth PMOS tube, the substrate of the eighth PMOS tube and the substrate of the seventh PMOS tube are connected and connected to the output voltage of the first output port; the drain electrode of the fourth NMOS tube is connected with the source electrode of the seventh PMOS tube, and a second output port is arranged at the connection position; and the drain electrode of the fifth NMOS tube is connected with the source electrode of the eighth PMOS tube.

Preferably, the second switch gating circuit further includes a seventh NMOS transistor and a tenth PMOS transistor; the grid electrode of the seventh NMOS tube is connected with the grid electrode of the tenth PMOS tube; the drain electrode of the seventh NMOS tube is connected with the drain electrode of the tenth PMOS tube, a third output port is arranged at the connection part, and the third output port is connected with the grid electrode of the sixth NMOS tube; the source electrode and the substrate of the seventh NMOS tube are both grounded, and the source electrode and the substrate of the tenth PMOS tube are both connected with the chip power supply voltage; the grid electrode of the fifth NMOS tube and the grid electrode of the seventh NMOS tube are both connected to the power supply voltage of the chip; and the grid electrode of the fourth NMOS tube and the grid electrode of the eighth PMOS tube are both connected with bias voltage.

Preferably, the gate of the power transistor is connected to the second output port, and the drain of the power transistor is further connected to the drain of the seventh NMOS transistor and the source of the fourth NMOS transistor; and the grid electrode and the drain electrode of the bias tube are connected with the drain electrode of the sixth NMOS tube and the source electrode of the ninth PMOS tube.

Preferably, the circuit for preventing the I2C interface from flowing backward current further comprises a gating MOS transistor; the source electrode and the substrate of the gating MOS tube are grounded, the drain electrode of the gating MOS tube is connected with the grid electrode of the power tube, and the grid electrode of the gating MOS tube is connected with a control signal; and the grid electrode of the ninth PMOS tube, the grid electrode of the seventh NMOS tube and the grid electrode of the tenth PMOS tube are all connected to the control signal.

The implementation of one of the technical schemes of the invention has the following advantages or beneficial effects:

according to the invention, the backflow prevention processing circuit is designed between the IO port power supply and the chip power supply, the backflow prevention processing circuit can effectively prevent the backflow current of the I2C interface from entering the chip power supply circuit, and the ESD risk caused by the change of the IO port circuit of the chip is effectively avoided, so that the normal power-on and work of the chip are ensured.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

FIG. 1 is a schematic diagram of a master control system architecture;

FIG. 2 is a schematic diagram of a conventional I2C port leakage path;

FIG. 3 is a schematic diagram of a power down path of the chip of the present invention according to an embodiment of the present invention;

FIG. 4 is a circuit schematic of an embodiment of the invention;

FIG. 5 is a schematic diagram of a first switch gating circuit in accordance with an embodiment of the present invention;

fig. 6 is a schematic diagram of a second switch gating circuit according to an embodiment of the invention.

Detailed Description

In order that the objects, aspects and advantages of the present invention will become more apparent, various exemplary embodiments will be described below with reference to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary embodiments in which the invention may be practiced. The same numbers in different drawings identify the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. It is to be understood that they are merely examples of processes, methods, apparatus, etc. consistent with certain aspects of the present disclosure as detailed in the appended claims, and that other embodiments may be used or structural and functional modifications may be made to the embodiments set forth herein without departing from the scope and spirit of the present disclosure.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," and the like are used in the orientations and positional relationships illustrated in the accompanying drawings for the purpose of facilitating the description of the present invention and simplifying the description, and do not indicate or imply that the elements so referred to must have a particular orientation, be constructed in a particular orientation, and be operated. The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "plurality" means two or more. The terms "coupled" and "connected" are to be construed broadly and may include, for example, a fixed connection, a removable connection, a unitary connection, a mechanical connection, an electrical connection, a communicative connection, a direct connection, an indirect connection via intermediate media, and may include, but are not limited to, a connection between two elements or an interactive relationship between two elements. The term "and/or" includes any and all combinations of one or more of the associated listed items. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In order to explain the technical solution of the present invention, the following description is made by way of specific examples, which only show the relevant portions of the embodiments of the present invention.

The first embodiment is as follows:

as shown in fig. 4, the present invention provides a circuit for preventing I2C interface from flowing backward current, which is used for preventing the current of the I2C interface from flowing backward to the power source terminal of the chip, and includes a first switch gating circuit, a second switch gating circuit, a power tube MP2 connected between the first switch gating circuit and the second switch gating circuit, and a bias tube MP3 connected to both the second switch gating circuit and the power tube MP 2. The bias tube MP3 is used to provide a bias voltage Vbp to the power tube MP2, the first switch-gating circuit is used to provide an I2C interface voltage IOVCC or a chip power supply voltage Vdd to the power tube MP2, and the second switch-gating circuit is used to provide an I2C interface voltage IOVCC or a bias voltage Vbp to the power tube MP 2. The invention aims to provide a circuit for preventing I2C interface backward flow current from flowing into a chip power supply Vdd, which can effectively prevent the problems of voltage and electric leakage of the chip power supply after the chip is powered off when I2C is normally communicated for power supply. The backflow prevention processing is carried out between the IO port power supply and the chip power supply, the backflow prevention processing is different from the conventional backflow prevention circuit designed at the IO port, and the ESD risk caused by changing the IO port circuit of the chip can be effectively avoided. ESD (Electro-Static discharge), i.e. electrostatic discharge risk. In fig. 3, MN1 is a pull-down MOS transistor of the IO port, MP1 is a pull-up MOS transistor of the IO port, and MP2 is a power PMOS transistor from the I2C interface voltage IOVCC to the chip power supply voltage Vdd. DN1 is the parasitic diode of MN1, DP1 is the parasitic diode of MP1, and DP2 is the parasitic diode of power tube MP 2. Vdn, Vdp and Vbias are the gate bias voltages of MN1, MP1 and MP2 tubes respectively.

As further shown in fig. 4, the source, the substrate, and the drain of the power transistor MP2 are all connected to the first switch gating circuit, and the gate and the drain thereof are all connected to the second switch gating circuit. The source of the bias transistor MP3 (POMS transistor) is connected to the source of the power transistor MP2 and the first switch gate circuit, and is connected to the chip power supply voltage Vdd, the drain and the gate of the bias transistor MP3 are connected to the second switch gate circuit, and the substrate of the bias transistor MP3 is connected to a power supply Vsub. The drains of the first switch gating circuit, the second switch gating circuit and the power tube MP2 are all connected, and the I2C interface voltage IOVCC is connected to the connection.

As shown in fig. 5, the first switch gating circuit includes a third NMOS transistor MN3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP 6. The source electrode and the substrate of the third NMOS transistor MN3 are grounded, and the drain electrode of the third NMOS transistor MN3 is connected with the gate electrode of the fourth PMOS transistor MP4 and the drain electrode of the sixth PMOS transistor MP 6; the substrate and the source of the sixth PMOS transistor MP6 are both connected to the source of the fifth PMOS transistor MP5, and the I2C interface voltage IOVCC is accessed; the grid of the third NMOS transistor MN3 and the grid of the sixth PMOS transistor MP6 are connected to the power-on reset signal Poc of the chip, the source of the fourth PMOS transistor MP4 is connected to the substrate, the drain of the fifth PMOS transistor MP5 and the substrate, and a first output port with an output voltage Vsub is disposed at the connection. Further, the substrate of the power transistor MP2 is connected to the first output port, the drain thereof is connected to the source of the fifth PMOS transistor MP5, and the source thereof is connected to the drain of the fourth PMOS transistor MP 4.

As shown in fig. 6, the second switch gating circuit includes a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, and a ninth PMOS transistor MP 9. Specifically, the source of the fourth NMOS transistor MN4 is connected to the drain of the seventh PMOS transistor MP7 and connected to the I2C interface voltage IOVCC, and the drain of the fourth NMOS transistor MN4, the source of the fifth NMOS transistor MN5, the drain of the fifth NMOS transistor MN5, and the source of the sixth NMOS transistor MN6 are sequentially connected; the drain electrode of the sixth NMOS transistor MN6 is connected with the source electrode of the ninth PMOS transistor MP9 and is connected with the bias voltage Vbp; the drain electrode of the ninth PMOS tube MP9, the source electrode of the eighth PMOS tube MP8, the drain electrode of the eighth PMOS tube MP8 and the source electrode of the seventh PMOS tube MP7 are connected in sequence; the substrate of the fourth NMOS transistor MN4, the substrate of the fifth NMOS transistor MN5 and the substrate of the sixth NMOS transistor MN6 are all grounded; the substrate of the ninth PMOS transistor MP9, the substrate of the eighth PMOS transistor MP8, and the substrate of the seventh PMOS transistor MP7 are all connected, and the output voltage Vsub of the first output port is connected; the drain electrode of the fourth NMOS transistor MN4 is connected to the source electrode of the seventh PMOS transistor MP7, a second output port is provided at the connection, and the drain electrode of the fifth NMOS transistor MN5 is connected to the source electrode of the eighth PMOS transistor MP 8.

More specifically, the second switch gating circuit further includes a seventh NMOS transistor MN7 and a tenth PMOS transistor MP 10. The gate of the seventh NMOS transistor MN7 is connected to the gate of the tenth PMOS transistor MP 10; the drain electrode of the seventh NMOS transistor MN7 is connected to the drain electrode of the tenth PMOS transistor MP10, and a third output port is provided at the connection, the third output port being connected to the gate electrode of the sixth NMOS transistor MN6 to provide a bias voltage for the sixth NMOS transistor MN 6; the source electrode and the substrate of the seventh NMOS transistor MN7 are both grounded, and the source electrode and the substrate of the tenth PMOS transistor MP10 are both connected with the chip power supply voltage Vdd; the grid electrode of the fifth NMOS transistor MN5 and the grid electrode of the seventh NMOS transistor MN7 are both connected to a chip power supply voltage Vdd; the gate of the fourth NMOS transistor MN4 and the gate of the eighth PMOS transistor MP8 are both connected to the bias voltage Pocb. Further, the gate of the power transistor MP2 is connected to the second output port to provide the bias voltage Vbias for the power transistor MP2, the drain of the power transistor MP2 is further connected to the drain of the seventh NMOS transistor MN7 and the source of the fourth NMOS transistor MN4, and the gate and the drain of the bias transistor MP3 are connected to the drain of the sixth NMOS transistor MN6 and the source of the ninth PMOS transistor MP 9.

The circuit for preventing the I2C interface from flowing backward current further includes a gating MOS transistor MN2, which is used to pull the Vbias voltage low, so that Vdd = IOVCC, to be compatible with different types of communication interface voltages. The source electrode and the substrate of the gating MOS transistor MN2 are grounded, the drain electrode of the gating MOS transistor MN2 is connected with the gate electrode of the power transistor MP2, and the gate electrode of the gating MOS transistor MP2 is connected with a control signal lOVCC-sel, and the gate electrode of the ninth PMOS transistor MP9, the gate electrode of the seventh NMOS transistor MN7 and the gate electrode of the tenth PMOS transistor MP10 are connected with the control signal lOVCC-sel.

It should be noted that: since the parasitic diode DP2 of the power transistor MP2 is a diode formed from drain to substrate, the I2C interface is prevented from sinking current into Vdd of the chip by designing the diode path and the channel path of DP 2. As shown in fig. 4, the substrate of the power transistor MP2 is gated, the bias transistor MP3 is used to provide the bias voltage Vbp to the power transistor MP2 when the chip is operating normally, and the substrate of the power transistor MP2 is also gated. The substrate ports of the power tube MP2 and the bias tube MP3 are connected to the Vsub voltage output by the first switch gating circuit, so that the substrate parasitic diode of the power tube MP2 is reversely biased to turn off the substrate leakage path. The gate voltage of the power transistor MP2 is provided by the second switch gating circuit, so that after the chip is powered off, the gate voltage of the power transistor MP2 is a high voltage, thereby turning off the channel leakage path of the power transistor MP 2. MN2 is a gating MOS transistor compatible with IOVCC = Vdd, and IOVCC _ sel is a control signal of gating MOS transistor MN 2.

Further, after the chip is powered off, by turning off the channel of the power transistor MP2 and the substrate path, no path exists between IOVCC and Vdd, so the chip power supply Vdd voltage gradually drops to 0V, and the whole chip has no leakage path. To account for the leakage of the substrate diode path, the first gating circuit in fig. 5 selects the IOVCC voltage and the Vdd voltage to provide the appropriate substrate voltage to the power transistor MP 2. The sixth PMOS transistor MP6 and the third NMOS transistor MN3 form an inverter, which receives the power-on reset signal Poc of the chip and outputs the power-on reset signal Poc. The power supply of the inverter is not connected to Vdd but to IOVCC. By doing so, after the chip is powered off, Pocb can reach the IOVCC voltage to turn off the fourth PMOS transistor MP4, so that Vsub = IOVCC. When the chip is working normally, Pocb =0V, Vsub = Vdd. Therefore, the substrate voltage for the power transistor MP2 is at a high level regardless of whether the chip is operating normally or is powered off. Therefore, when the chip works normally, the threshold voltage deviation caused by the substrate voltage deviation of the power tube MP2 is not influenced; when the power supply is off during abnormal operation, the substrate diode path of the power tube MP2 is closed, and the leakage path is closed. In order to solve the leakage of the channel path, the second switch gating circuit in fig. 6 is to turn off the channel leakage path of the power transistor MP2 when the chip is powered off. The gate voltage Vbias of the power tube MP2 is selected by Vbp and IOVCC voltage, when the chip is powered on and works normally, the switches of the seventh PMOS tube MP7 and the fourth NMOS tube MN4 are switched off, the switches of the eighth PMOS tube MP8, the fifth NMOS tube MN5, the ninth PMOS tube MP9 and the sixth NMOS tube MN6 are switched on, and Vbias = Vbp; when the chip is powered off, the switches of the seventh PMOS tube MP7 and the fourth NMOS tube MN4 are closed, the switches of the eighth PMOS tube MP8, the fifth NMOS tube MN5, the ninth PMOS tube MP9 and the sixth NMOS tube MN6 are opened, Vbias = IOVCC, and at the moment, the channel of the power tube MP2 is turned off, so that no electric leakage exists. IOVCC _ sel and IOVCC _ selb are one switch option compatible with the power supply of the IO port when the chip works normally, the default IOVCC _ sel is 0, namely the switches of the ninth PMS tube MP9 and the sixth NMOS tube MN6 are in a closed state. When IOVCC _ sel is 1, Vdd = IOVCC, and the nine PMS transistor MP9 and the sixth NMOS transistor MN6 are turned off. The switch in the second switch gating circuit uses a transmission gate, and since the gate voltage of the power transistor MP2 varies with the load change of IOVCC, a parallel connection of PMOS and NMOS, i.e., a transmission gate, is used as the switch. The substrates of the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, and the ninth PMOS transistor MP9 use the Vsub voltage outputted by the first switch gating circuit, and here, the substrate diode paths of the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, and the ninth PMOS transistor MP9 are switched off skillfully, and it is avoided that when the chip works normally, the power transistor MP2 drives a large current, and the IOVCC voltage is too low to leak to Vdd and Vss of the chip through the substrate diode paths of the PMOS transistors.

In summary, the channel path from IOVCC to Vdd and the substrate diode path are cut off in the abnormal operation mode of the chip, so that the voltage at the interface of the chip I2C is prevented from flowing back into the chip. The problem of chip leakage when I2C still communicates normally after the chip is powered off is successfully solved. Before the chip is powered on, if the I2C is powered on, the leakage path is cut off, the Vdd voltage cannot be charged to a voltage by the I2C interface voltage, and the chip Vdd is powered on from 0V, so that the normal power-on and normal working modes of the chip are ensured.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A circuit for preventing I2C interface from backward flowing current is used in a circuit for preventing the current of I2C interface from backward flowing to the power end of chip, and is characterized by comprising a first switch gating circuit, a second switch gating circuit, a power tube MP2 connected between the first switch gating circuit and the second switch gating circuit, and a bias tube MP3 connected with the second switch gating circuit and the power tube MP 2;

the bias tube MP3 is used for providing a bias voltage Vbp to the power tube MP 2; the first switch gating circuit is used for providing an I2C interface voltage IOVCC or a chip power supply voltage Vdd for the power tube MP 2; the second switch gating circuit is used for providing the I2C interface voltage IOVCC or the bias voltage Vbp to the power tube MP 2;

the source electrode of the bias tube MP3 is connected with the source electrode of the power tube MP2 and the first switch gating circuit, and is connected to the chip power supply voltage Vdd;

the drain and the gate of the bias tube MP3 are both connected with the second switch gating circuit, and the substrate of the bias tube MP3 is connected with a power supply Vsub;

the drains of the first switch gating circuit, the second switch gating circuit and the power tube MP2 are all connected and connected to the I2C interface voltage IOVCC.

2. The circuit for preventing I2C interface from backward flowing current according to claim 1, wherein the source, the substrate and the drain of the power transistor MP2 are all connected to the first switch gating circuit, and the gate and the drain are all connected to the second switch gating circuit.

3. The circuit for preventing the I2C interface from backward flowing of current as claimed in claim 2, wherein said first switch gating circuit comprises a third NMOS transistor MN3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5 and a sixth PMOS transistor MP 6;

the source electrode and the substrate of the third NMOS transistor MN3 are grounded, and the drain electrode of the third NMOS transistor MN3 is connected with the gate electrode of the fourth PMOS transistor MP4 and the drain electrode of the sixth PMOS transistor MP 6; the substrate and the source of the sixth PMOS transistor MP6 are both connected to the source of the fifth PMOS transistor MP5, and the I2C interface voltage IOVCC is accessed; the grid electrode of the third NMOS transistor MN3 and the grid electrode of the sixth PMOS transistor MP6 are connected to a power-on reset signal Poc of the chip;

the source electrode and the substrate of the fourth PMOS transistor MP4 are connected to the drain electrode and the substrate of the fifth PMOS transistor MP5, and a first output port is disposed at the connection.

4. The circuit of claim 3, wherein the substrate of the power transistor MP2 is connected to the first output port, the drain thereof is connected to the source of the fifth PMOS transistor MP5, and the source thereof is connected to the drain of the fourth PMOS transistor MP 4.

5. The circuit for preventing the I2C interface from backward flowing of current as claimed in claim 3, wherein the second switch gating circuit comprises a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, and a ninth PMOS transistor MP 9;

the source electrode of the fourth NMOS transistor MN4 is connected to the drain electrode of the seventh PMOS transistor MP7, and is connected to the I2C interface voltage IOVCC; the drain electrode of the fourth NMOS transistor MN4, the source electrode of the fifth NMOS transistor MN5, the drain electrode of the fifth NMOS transistor MN5 and the source electrode of the sixth NMOS transistor MN6 are sequentially connected;

the drain electrode of the sixth NMOS transistor MN6 is connected with the source electrode of the ninth PMOS transistor MP9 and is connected with the bias voltage Vbp; the drain electrode of the ninth PMOS tube MP9, the source electrode of the eighth PMOS tube MP8, the drain electrode of the eighth PMOS tube MP8 and the source electrode of the seventh PMOS tube MP7 are connected in sequence;

the substrate of the fourth NMOS transistor MN4, the substrate of the fifth NMOS transistor MN5 and the substrate of the sixth NMOS transistor MN6 are all grounded;

the substrate of the ninth PMOS transistor MP9, the substrate of the eighth PMOS transistor MP8, and the substrate of the seventh PMOS transistor MP7 are all connected, and the output voltage Vsub of the first output port is connected;

the drain electrode of the fourth NMOS transistor MN4 is connected with the source electrode of the seventh PMOS transistor MP7, and a second output port is arranged at the connection position;

the drain of the fifth NMOS transistor MN5 is connected to the source of the eighth PMOS transistor MP 8.

6. The circuit for preventing I2C interface from backward flowing of current as claimed in claim 5, wherein said second switch gating circuit further comprises a seventh NMOS transistor MN7 and a tenth PMOS transistor MP 10;

the gate of the seventh NMOS transistor MN7 is connected to the gate of the tenth PMOS transistor MP 10;

the drain of the seventh NMOS transistor MN7 is connected to the drain of the tenth PMOS transistor MP10, a third output port is provided at the connection, and the third output port is connected to the gate of the sixth NMOS transistor MN 6;

the source and the substrate of the seventh NMOS transistor MN7 are both grounded, and the source and the substrate of the tenth PMOS transistor MP10 are both connected to the chip power supply voltage Vdd;

the grid electrode of the fifth NMOS transistor MN5 and the grid electrode of the seventh NMOS transistor MN7 are both connected to the chip power supply voltage Vdd;

the grid electrode of the fourth NMOS transistor MN4 and the grid electrode of the eighth PMOS transistor MP8 are both connected with a bias voltage Pocb.

7. The circuit for preventing the I2C interface from flowing backwards according to claim 6, wherein a gate of the power transistor MP2 is connected to the second output port, and a drain of the power transistor MP2 is further connected to a drain of the seventh NMOS transistor MN7 and a source of a fourth NMOS transistor MN 4;

the gate and the drain of the bias transistor MP3 are connected to the drain of the sixth NMOS transistor MN6 and the source of the ninth PMOS transistor MP 9.

8. The circuit for preventing the I2C interface from backward flowing current according to claim 7, further comprising a gating MOS transistor MN 2;

the source electrode and the substrate of the gating MOS transistor MN2 are grounded, the drain electrode of the gating MOS transistor MN2 is connected with the gate electrode of the power transistor MP2, and the gate electrode of the gating MOS transistor MN is connected with a control signal lOVCC-sel;

the gate of the ninth PMOS transistor MP9, the gate of the seventh NMOS transistor MN7, and the gate of the tenth PMOS transistor MP10 are all connected to the control signal lOVCC-sel.