CN114050717A - Frequency domain synthesis type active EMI (electro-magnetic interference) canceller and cancellation method thereof - Google Patents

Frequency domain synthesis type active EMI (electro-magnetic interference) canceller and cancellation method thereof Download PDF

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CN114050717A
CN114050717A CN202111265625.7A CN202111265625A CN114050717A CN 114050717 A CN114050717 A CN 114050717A CN 202111265625 A CN202111265625 A CN 202111265625A CN 114050717 A CN114050717 A CN 114050717A
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signal
frequency
emi
dac
canceller
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姬军鹏
李刚
成凤娇
陈文洁
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Xian University of Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters

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Abstract

The invention discloses a frequency domain synthesis type active EMI (electro-magnetic interference) canceller which comprises an FPGA (field programmable gate array) chip, wherein the FPGA chip is also sequentially connected with a DAC (digital-to-analog converter), an operational amplifier and an injection circuit. The invention discloses a counteracting method of a frequency domain synthesis type active EMI counteractor, which comprises the following steps: the FPGA chip sends out an EMI offset signal
Figure DDA0003326872860000011
EMI cancellation signal
Figure DDA0003326872860000012
Injection link formed by DAC, operational amplifier and injection circuit
Figure DDA0003326872860000013
Becomes the signal of the final injection circuit
Figure DDA0003326872860000015
And switching power converter generationOf an EMI signal
Figure DDA0003326872860000014
Cancel each other out. The problems of large size and large power consumption of the traditional EMI filter are solved.

Description

Frequency domain synthesis type active EMI (electro-magnetic interference) canceller and cancellation method thereof
Technical Field
The invention belongs to the technical field of electromagnetic compatibility of switching power converters, relates to a frequency domain synthesis type active EMI (electro-magnetic interference) canceller, and further relates to a cancellation method of the canceller.
Background
The switching power converter has the advantages of small size, light weight, high efficiency and the like, and is widely applied to various fields. With the development of high frequency and integration of switching power converters, the problem of conducted EMI becomes more and more serious, and measures are required to be taken to suppress the conducted EMI. The traditional EMI suppression method suppresses EMI by connecting passive devices in series and parallel in a main circuit, but the traditional EMI suppression method has the defects of large volume, high power consumption, no pertinence in EMI suppression and poor suppression effect. The frequency domain synthesis type active EMI canceller designed by the invention can be used for specifying an interference source, generating an EMI cancellation signal suitable for an inhibited object and improving the EMI inhibition effect.
Disclosure of Invention
The invention aims to provide a frequency domain synthesis type active EMI canceller, which solves the problems of large volume and large power consumption of the traditional EMI filter.
The invention also provides a counteracting method of the frequency domain synthesis type active EMI counteractor.
The first technical scheme adopted by the invention is that the frequency domain synthesis type active EMI canceller comprises an FPGA chip, wherein the FPGA chip is also sequentially connected with a DAC, an operational amplifier and an injection circuit.
The first technical scheme of the invention is also characterized in that:
the output of the injection circuit is connected to a power line of the switching power converter, a control signal of the switching power converter is used as a trigger signal, and the DAC is connected with the FPGA chip through a parallel signal connecting line.
The second technical scheme adopted by the invention is that the counteracting method of the frequency domain synthesis type active EMI counteractor specifically comprises the following processes: the FPGA chip sends out an EMI offset signal
Figure BDA0003326872840000021
EMI cancellation signal
Figure BDA0003326872840000022
Injection link formed by DAC, operational amplifier and injection circuit
Figure BDA0003326872840000023
Becomes the signal of the final injection circuit
Figure BDA0003326872840000024
And EMI signal generated by switching power converter
Figure BDA0003326872840000025
Cancel each other out.
The second technical scheme of the invention is also characterized in that:
the resources of the FPGA chip comprise a logic unit and an internal memory;
the number of logical units L is calculated using the following formula (1):
Figure BDA0003326872840000026
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal separation of frequency, EsThe number of logic units occupied by programming to generate sine waves of one frequency point for the FPGA.
The sine wave information of the internal memory of the FPGA chip comprises frequency, amplitude and phase;
storage space M of frequency information1The following equation is obtained:
Figure BDA0003326872840000027
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal spacing of frequency, fezThe number of bytes occupied by the binary number is converted into the highest frequency;
storage space M of frequency information1From belowThe formula is obtained:
Figure BDA0003326872840000031
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal spacing of frequency, fezThe number of bytes occupied by the binary number is converted into the highest frequency;
storage space M for phase information3The following equation is obtained:
Figure BDA0003326872840000032
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal separation of frequency, PezThe number of bytes taken for the highest phase to convert to a binary number.
The invention has the following beneficial effects:
1. the EMI canceller adopts a cancellation mode of connecting a power line in parallel, so that the EMI canceller has small volume and light weight;
2. the counteracting method aims at a specific interference source, measures an actual EMI signal in a circuit, generates an EMI counteracting signal suitable for a restrained object, and has the advantages of high signal precision, good effect and pertinence.
Drawings
FIG. 1 is a schematic diagram of a frequency domain synthesized active EMI canceller according to the present invention;
FIG. 2 is a signal flow diagram of the frequency domain synthesized active EMI canceller of the present invention;
FIG. 3 is an injection transfer function of the frequency domain synthesis type active EMI canceller of the present invention
Figure BDA0003326872840000033
A measurement flow chart of (1);
FIG. 4 is a flow chart of conducted EMI measurement in a frequency domain synthesized active EMI canceller of the present invention;
FIG. 5 is a diagram of the detection transfer function in the frequency domain synthesis type active EMI canceller of the present invention
Figure BDA0003326872840000041
The measurement flow chart of (1).
In the figure, 1, an FPGA chip, 2, a DAC, 3, an operational amplifier and 4, an injection circuit.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The frequency domain synthesis type active EMI canceller adopts an off-line measurement and calculation method aiming at a specific interference source and EMI cancellation signals, considers the influence of signal delay and the high-frequency characteristic of a passive device on the EMI signals, ensures the precision of the EMI cancellation signals, improves the EMI inhibition effect and has pertinence.
The working principle of the frequency domain synthesis type active EMI canceller of the present invention is shown in FIG. 1.
The PC will calculate the EMI offset signal
Figure BDA0003326872840000042
The data of the FPGA are programmed into the FPGA and stored in an internal RAM of the FPGA chip 1, and the FPGA chip 1 takes a switching signal of a switching power converter as a trigger signal and calls the trigger signal from a memory
Figure BDA0003326872840000043
The digital signal is converted into an analog signal by the DAC2, the analog signal is converted into a power signal by the operational amplifier 3, and the power signal reaches the switching power converter by the injection circuit 4
Figure BDA0003326872840000044
And EMI signal generated by switching power converter
Figure BDA0003326872840000045
And offsetting to achieve the aim of inhibiting EMI. Wherein the injection circuit is responsible for isolation
Figure BDA0003326872840000046
And signals above 30MHz are isolated, and low-frequency power signals on the main circuit are isolated, so that the damage of the power signals on a power supply line to an output port of the operational amplifier is prevented.
The output of the injection circuit 4 is connected to the power line of the switching power converter, and the control signal of the switching power converter is used as a trigger signal.
The FPGA chip 1 utilizes the SMA interface to receive the control signal of the switching power converter and utilizes the JTAG interface to receive the EMI offset signal output by the PC end
Figure BDA0003326872840000051
Using the IO port to output an EMI cancellation signal
Figure BDA0003326872840000052
Feeding the DAC;
the DAC2 converts the digital signal output by the FPGA chip 1 into an analog signal, and the DAC is connected with the FPGA chip 1 through parallel signal connecting lines;
the operational amplifier 3 converts the analog signal output by the DAC2 into a power signal to increase the EMI cancellation signal
Figure BDA0003326872840000053
One end of the operational amplifier is connected with the output port of the DAC, and the other end of the operational amplifier is connected with the injection circuit;
the injection circuit is used as a low-pass filter to isolate signals above 30MHz and isolate power signals on the main circuit, one end of the injection circuit is connected with the output of the operational amplifier through a power line, and the other end of the injection circuit is connected with an output port.
EMI cancellation signal
Figure BDA0003326872840000054
The acquisition process is as follows:
the signal flow diagram for an EMI cancellation system is shown in fig. 2.
The EMI canceller sends an EMI cancellation signal through the FPGA chip 1
Figure BDA0003326872840000055
An injection link composed of DAC2, operational amplifier 3 and injection circuit 4
Figure BDA0003326872840000056
Becomes the signal of the final injection circuit
Figure BDA0003326872840000057
And EMI signal generated by switching power converter
Figure BDA0003326872840000058
The following equations can be obtained by offsetting each other:
Figure BDA0003326872840000059
wherein the content of the first and second substances,
Figure BDA00033268728400000510
ideally, the residual signal of the post-cancellation EMI is
Figure BDA00033268728400000511
The following formula can be obtained:
Figure BDA00033268728400000512
in the above formula, the first and second carbon atoms are,
Figure BDA00033268728400000513
cannot be directly obtained, and needs to pass through a detection circuit
Figure BDA00033268728400000514
Is obtained by a spectrum analyzer, and the EMI signal obtained here is not real but passes through a detection circuit
Figure BDA0003326872840000061
Shifted EMI signal
Figure BDA0003326872840000062
Thus, it is possible to provide
Figure BDA0003326872840000063
Can be obtained by the following formula:
Figure BDA0003326872840000064
in summary, the following formula can be obtained:
Figure BDA0003326872840000065
is obtained by the above formula
Figure BDA0003326872840000066
The calculation formula of (2) is as follows:
Figure BDA0003326872840000067
wherein a transfer function is injected
Figure BDA0003326872840000068
Conducted EMI
Figure BDA0003326872840000069
Detecting letter
Figure BDA00033268728400000610
And EMI cancellation signals
Figure BDA00033268728400000611
The acquisition method of (1) is as follows.
Step 1, injecting a transfer letter
Figure BDA00033268728400000612
The acquisition process is as follows:
a test platform is set up, as shown in fig. 3, wherein, DAC2, operational amplifier 3The injection link with the injection circuit 4 is the tested link.
Figure BDA00033268728400000613
The measurement process is as follows, the FPGA chip 1 sends out a test signal
Figure BDA00033268728400000614
Converted into signals through an injection link
Figure BDA00033268728400000615
Received by the spectrum analyzer, will
Figure BDA00033268728400000616
And transmitted to the PC. In PC, by formula
Figure BDA00033268728400000617
To obtain
Figure BDA00033268728400000618
I.e. the transfer of the link is injected and stored in the PC.
Step 2, conducting EMI information data
Figure BDA00033268728400000619
The acquisition process is as follows:
and (4) constructing a test platform, as shown in fig. 4, wherein the detection circuit is responsible for extracting the high-frequency conduction EMI signal transmitted on the power line and transmitting the high-frequency conduction EMI signal to the spectrum analyzer. EMI signal generated by switching power converter
Figure BDA00033268728400000620
After passing through the detection circuit, becomes a signal
Figure BDA00033268728400000621
Detected by the spectrum analyzer and transmitted to the PC.
Step 3, detecting the transfer letter
Figure BDA00033268728400000622
Is obtained as follows：
A test platform is set up, as shown in fig. 5, the FPGA chip 1 sends out a test signal
Figure BDA0003326872840000071
Figure BDA0003326872840000072
After the injection link and the detection link, the signals are received by a spectrum analyzer and become signals
Figure BDA0003326872840000073
Will be provided with
Figure BDA0003326872840000074
And
Figure BDA0003326872840000075
and transmitted to the PC. In PC, by formula
Figure BDA0003326872840000076
Obtaining a transmission letter of a detection link
Figure BDA0003326872840000077
And stored in the PC.
Step 4, EMI counteraction signal
Figure BDA0003326872840000078
The acquisition process is as follows:
in PC, by formula
Figure BDA0003326872840000079
Obtaining EMI offset signal
Figure BDA00033268728400000710
The design process of the EMI canceller is as follows:
step 1: the model selection design of the FPGA chip 1;
the FPGA chip 1 needs to undertake sending test signals
Figure BDA00033268728400000711
And storing the EMI cancellation signal
Figure BDA00033268728400000712
The FPGA chip 1 needs to have enough resources, and the resources of the FPGA chip mainly include logic units and internal memories.
1) Logic cells (LEs):
the number of logical units L is calculated by:
Figure BDA00033268728400000713
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFrequency, FPGA co-generation for signal spacing
Figure BDA00033268728400000714
Sine wave signal of individual frequency point, EsThe number of logic units occupied by programming to generate sine waves of one frequency point for the FPGA chip 1.
In the present invention, fstart＝150kHz，fend30MHz, corresponding to the test band of the conducted EMI national standard. For cost and accuracy reasons, the spacing frequency is designed to be fg100 Hz. Sine wave for programming to generate a frequency point needs to occupy EsThe resource of 0.1LEs, therefore, the present invention needs to occupy L logical units.
Figure BDA0003326872840000081
2) An internal memory RAM: the FPGA stores a sine wave of information including frequency, amplitude and phase, which is stored in binary form in internal RAM memory.
Storage space M of frequency information1The following equation is obtained:
Figure BDA0003326872840000082
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal spacing of frequency, fezThe number of bytes taken for the highest frequency conversion to binary numbers.
In the present invention, fstart＝150kHz，fend＝30MHz，fg100 Hz. The maximum frequency stored in the invention is 30MHz, the decimal number 30M is represented by 1110010011100001110000000 in binary, and f is occupiedez0.5 bytes, therefore, M is required to store all frequency information within a set frequency band1A byte.
Figure BDA0003326872840000083
Storage space M for amplitude information2The following equation is obtained:
Figure BDA0003326872840000084
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal spacing frequency, VezThe highest amplitude is converted to the number of bytes occupied by the binary number.
In the present invention, fstart＝150kHz，fend＝30MHz，fg100 Hz. The maximum amplitude of the EMI counteracting signal is 1V, for more accurate expression, 6 bits after the decimal point are reserved, and the expression mode of the amplitude information in the program is V-Vt×10-6Where V is the true voltage value, VtAre values stored in the FPGA. Therefore, the maximum amplitude stored in the present invention is 1000000, the corresponding binary number is 100110001001011010000000, and V is occupiedez0.5 bytes, therefore, M is required to store all amplitude information within a set frequency band2A byte.
Figure BDA0003326872840000091
Storage space M for phase information3The following equation is obtained:
Figure BDA0003326872840000092
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal separation of frequency, PezThe number of bytes taken for the highest phase to convert to a binary number.
In the present invention, fstart＝150kHz，fend＝30MHz，fg100 Hz. The phase stored in the invention is between 0 degree and 360 degrees, 4 bits after decimal point are reserved, and the FPGA can only store integer, so the expression mode of the phase information in the program is P-Pt×10-4Where P is the true phase value, PtThe values stored in the FPGA. Therefore, in the present invention, the maximum amplitude of the phase information is 3600000 and 1101101110111010000000 is represented in binary, and P is occupiedez0.5 bytes, therefore, M is required to store all amplitude information within a set frequency band3A byte.
Figure BDA0003326872840000093
Therefore, the FPGA chip 1 needs to occupy M ═ M1+M2+M3447750 bytes of storage space, i.e., 3498Kbits of storage space.
Based on the resource consideration of logic units LES and an internal memory RAM, the invention adopts an FPGA with the model number of EP4CE15, the logic units 114480LES and the RAM storage space 3888Kbits, thereby meeting the design requirements of the invention.
Step 2: and (3) model selection design of the DAC:
the DAC2 is a digital-to-analog converter and is responsible for converting the digital signals output by the FPGA into analog signals for output. The invention adopts a voltage type output DAC, and the performance indexes of the DAC mainly comprise a reference voltage range, a digit and a sampling rate.
1) Reference voltage VDACRange
Reference voltage VDACThe range of (A) is obtained by the following formula:
2Voff·max≤VDAC≤4Voff·max
wherein, Voff·maxIs the maximum amplitude of the EMI cancellation signal.
In the invention, the designed prototype generates the maximum EMI counteracting signal Voff·maxWhen 1V is satisfied, 2V is less than or equal to VDAC≤4V。
2) Number n of bitsbitsThe range of (A):
number n of bits of DACbitsThe range of (A) is obtained by the following formula:
Figure BDA0003326872840000101
wherein, VDAC,RMSIs the effective value of the maximum signal through the DAC, VDAC,NF,RMSIs the lowest limit value of the signal passing through the DAC.
In the present invention, the maximum amplitude V of the signal is passed through the DACDAC,maxWhen 1V, its effective value is
Figure BDA0003326872840000102
VDAC,NF,RMSAccording to the requirements of national standard GB/T21419-2013, set to be VDAC,NF,RMS56 dB/. mu.V. Thus, n in the present inventionbitsThe following equation should be satisfied:
Figure BDA0003326872840000103
3) sampling rate fDACRange of (1)
Sampling rate f of DACDACThe range of (A) is obtained by the following formula:
5fend≤fDAC≤10fend
wherein f isendThe maximum frequency of the EMI signal.
In the invention fendAt 30MHz, the sampling frequency satisfies the following equation:
150MHz≤fDAC≤300MHz
based on a reference voltage VDACN number of digitsbitsAnd a sampling rate fDACSelecting a DAC of model ISL5957, wherein VDAC＝±3.3V、nbits＝14、fDAC260MHz, meets the design requirements of the present invention.
And step 3, the selection design of the operational amplifier:
the operational amplifier converts the analog signal output by the DAC into a power signal for improving the EMI offset signal
Figure BDA0003326872840000111
The current of (2) improves the injection capability. The main performance indicators of an operational amplifier are gain bandwidth and slew rate.
1) Gain-bandwidth product GBW：
Gain-bandwidth product G of operational amplifierBWThe range of (A) is obtained by the following formula:
GBW≥Gain*fend
where Gain is the designed closed loop Gain, fendIs the maximum frequency of the passing signal.
In the present invention, Gain is 1, fend30 MHz. Thus, GBWSatisfies the following formula:
GBW≥30MHz
2) slew rate SR:
the range of slew rate SR of the operational amplifier is obtained by the following equation:
SR≥2*π*fend*Vin*Gain
wherein f isendFor maximum frequency of passing signal, VinGain is the designed closed loop Gain for the maximum amplitude of the pass signal.
In the present invention, fend＝30MHz，Vin＝1V，Gain1. Therefore, SR needs to satisfy the following equation:
SR≥2*π*30M*1*1≥188.4V/μs
based on gain-bandwidth product GBWAnd the slew rate SR, an operational amplifier model LT1365CN is selected, wherein GBW70MHz, and SR 1000V/mus, to meet the design requirement of the invention.
And 4, step 4: design of injection circuit
Injection circuit composed of resistor RinAnd a capacitor CinFormed in series, with the injection circuit resistance generally taken as Rin5 Ω, capacitance CinThe following equation is obtained:
Figure BDA0003326872840000121
wherein f isHIs the cut-off frequency.
In the present invention, fHAt 30MHz, a capacitor C is then injectedin＝1nF。

Claims (5)

1. A frequency domain synthesized active EMI canceller, comprising: the FPGA chip is also sequentially connected with a DAC, an operational amplifier and an injection circuit.
2. The frequency domain synthesized active EMI canceller of claim 1, wherein: the output of the injection circuit is connected to a power line of the switching power converter, a control signal of the switching power converter is used as a trigger signal, and the DAC is connected with the FPGA chip through a parallel signal connecting line.
3. A cancellation method of a frequency domain synthesis type active EMI canceller is characterized in that: the method specifically comprises the following steps: the FPGA chip sends out an EMI offset signal
Figure FDA0003326872830000011
EMI cancellation signal
Figure FDA0003326872830000012
Injection link formed by DAC, operational amplifier and injection circuit
Figure FDA0003326872830000013
Becomes the signal of the final injection circuit
Figure FDA0003326872830000014
Figure FDA0003326872830000015
And EMI signal generated by switching power converter
Figure FDA0003326872830000016
Cancel each other out.
4. The cancellation method of the frequency domain synthesized active EMI canceller of claim 3, wherein: the resources of the FPGA chip comprise a logic unit and an internal memory;
the number L of logic units is calculated using the following formula (1):
Figure FDA0003326872830000017
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal separation of frequency, EsThe number of logic units occupied by programming to generate sine waves of one frequency point for the FPGA.
5. The cancellation method of the frequency domain synthesized active EMI canceller of claim 4, wherein: one sine wave information of the internal memory of the FPGA chip comprises frequency, amplitude and phase;
storage space M of frequency information1The following equation is obtained:
Figure FDA0003326872830000021
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal spacing of frequency, fezThe number of bytes occupied by the binary number is converted into the highest frequency;
storage space M of frequency information1The following equation is obtained:
Figure FDA0003326872830000022
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal spacing of frequency, fezThe number of bytes occupied by the binary number is converted into the highest frequency;
storage space M for phase information3The following equation is obtained:
Figure FDA0003326872830000023
wherein f isstartIs the signal starting frequency, fendFor signal cut-off to frequency, fgFor signal separation of frequency, PezThe number of bytes taken for the highest phase to convert to a binary number.
CN202111265625.7A 2021-10-28 2021-10-28 Frequency domain synthesis type active EMI (electro-magnetic interference) canceller and cancellation method thereof Pending CN114050717A (en)

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